diff options
Diffstat (limited to 'arch/arm/cpu/armv7')
40 files changed, 882 insertions, 153 deletions
diff --git a/arch/arm/cpu/armv7/am33xx/sys_info.c b/arch/arm/cpu/armv7/am33xx/sys_info.c index 2ce682f6b1..781d83fc72 100644 --- a/arch/arm/cpu/armv7/am33xx/sys_info.c +++ b/arch/arm/cpu/armv7/am33xx/sys_info.c @@ -18,6 +18,7 @@ #include <asm/arch/cpu.h> #include <asm/arch/clock.h> #include <power/tps65910.h> +#include <linux/compiler.h> struct ctrl_stat *cstat = (struct ctrl_stat *)CTRL_BASE; @@ -51,11 +52,11 @@ u32 get_cpu_type(void) /** * get_board_rev() - setup to pass kernel board revision information - * returns:(bit[0-3] sub version, higher bit[7-4] is higher version) + * returns: 0 for the ATAG REVISION tag value. */ -u32 get_board_rev(void) +u32 __weak get_board_rev(void) { - return BOARD_REV_ID; + return 0; } /** diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c index a2c4032fed..0f9d8377ed 100644 --- a/arch/arm/cpu/armv7/cache_v7.c +++ b/arch/arm/cpu/armv7/cache_v7.c @@ -21,7 +21,8 @@ * to get size details from Current Cache Size ID Register(CCSIDR) */ static void set_csselr(u32 level, u32 type) -{ u32 csselr = level << 1 | type; +{ + u32 csselr = level << 1 | type; /* Write to Cache Size Selection Register(CSSELR) */ asm volatile ("mcr p15, 2, %0, c0, c0, 0" : : "r" (csselr)); @@ -49,7 +50,8 @@ static void v7_inval_dcache_level_setway(u32 level, u32 num_sets, u32 num_ways, u32 way_shift, u32 log2_line_len) { - int way, set, setway; + int way, set; + u32 setway; /* * For optimal assembly code: @@ -73,7 +75,8 @@ static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets, u32 num_ways, u32 way_shift, u32 log2_line_len) { - int way, set, setway; + int way, set; + u32 setway; /* * For optimal assembly code: @@ -134,7 +137,6 @@ static void v7_maint_dcache_level_setway(u32 level, u32 operation) static void v7_maint_dcache_all(u32 operation) { u32 level, cache_type, level_start_bit = 0; - u32 clidr = get_clidr(); for (level = 0; level < 7; level++) { @@ -147,8 +149,7 @@ static void v7_maint_dcache_all(u32 operation) } } -static void v7_dcache_clean_inval_range(u32 start, - u32 stop, u32 line_len) +static void v7_dcache_clean_inval_range(u32 start, u32 stop, u32 line_len) { u32 mva; @@ -256,7 +257,6 @@ void flush_dcache_all(void) */ void invalidate_dcache_range(unsigned long start, unsigned long stop) { - v7_dcache_maint_range(start, stop, ARMV7_DCACHE_INVAL_RANGE); v7_outer_cache_inval_range(start, stop); diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index d200531030..6c9c78c11a 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -312,6 +312,10 @@ static u32 get_ipg_per_clk(void) u32 reg, perclk_podf; reg = __raw_readl(&imx_ccm->cscmr1); +#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX)) + if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK) + return MXC_HCLK; /* OSC 24Mhz */ +#endif perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK; return get_ipg_clk() / (perclk_podf + 1); diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index dd5aaa286a..5fd2a63a1d 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -240,6 +240,18 @@ static void clear_mmdc_ch_mask(void) writel(0, &mxc_ccm->ccdr); } +#ifdef CONFIG_MX6SL +static void set_preclk_from_osc(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + u32 reg; + + reg = readl(&mxc_ccm->cscmr1); + reg |= MXC_CCM_CSCMR1_PER_CLK_SEL_MASK; + writel(reg, &mxc_ccm->cscmr1); +} +#endif + int arch_cpu_init(void) { init_aips(); @@ -255,6 +267,11 @@ int arch_cpu_init(void) if (mxc_get_clock(MXC_ARM_CLK) == 396000000) set_ahb_rate(132000000); + /* Set perclk to source from OSC 24MHz */ +#if defined(CONFIG_MX6SL) + set_preclk_from_osc(); +#endif + imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */ #ifdef CONFIG_APBH_DMA @@ -333,8 +350,8 @@ void boot_mode_apply(unsigned cfg_val) /* * cfg_val will be used for * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0] - * After reset, if GPR10[28] is 1, ROM will copy GPR9[25:0] - * to SBMR1, which will determine the boot device. + * After reset, if GPR10[28] is 1, ROM will use GPR9[25:0] + * instead of SBMR1 to determine the boot device. */ const struct boot_mode soc_boot_modes[] = { {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)}, diff --git a/arch/arm/cpu/armv7/omap3/Kconfig b/arch/arm/cpu/armv7/omap3/Kconfig index c215404469..a029379a4f 100644 --- a/arch/arm/cpu/armv7/omap3/Kconfig +++ b/arch/arm/cpu/armv7/omap3/Kconfig @@ -22,6 +22,9 @@ config TARGET_CM_T35 bool "CompuLab CM-T3530 and CM-T3730 boards" select SUPPORT_SPL +config TARGET_CM_T3517 + bool "CompuLab CM-T3517 boards" + config TARGET_DEVKIT8000 bool "TimLL OMAP3 Devkit8000" select SUPPORT_SPL @@ -98,6 +101,7 @@ source "board/teejet/mt_ventoux/Kconfig" source "board/ti/sdp3430/Kconfig" source "board/ti/beagle/Kconfig" source "board/compulab/cm_t35/Kconfig" +source "board/compulab/cm_t3517/Kconfig" source "board/timll/devkit8000/Kconfig" source "board/ti/evm/Kconfig" source "board/isee/igep00x0/Kconfig" diff --git a/arch/arm/cpu/armv7/rmobile/Kconfig b/arch/arm/cpu/armv7/rmobile/Kconfig index c46a0cc9b8..8444d4224a 100644 --- a/arch/arm/cpu/armv7/rmobile/Kconfig +++ b/arch/arm/cpu/armv7/rmobile/Kconfig @@ -23,6 +23,11 @@ endchoice config SYS_SOC default "rmobile" +config RMOBILE_EXTRAM_BOOT + bool "Enable boot from RAM" + depends on TARGET_ALT || TARGET_KOELSCH || TARGET_LAGER + default n + source "board/atmark-techno/armadillo-800eva/Kconfig" source "board/renesas/koelsch/Kconfig" source "board/renesas/lager/Kconfig" diff --git a/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S b/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S index 879e0e097f..d47546a11d 100644 --- a/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S +++ b/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S @@ -60,17 +60,10 @@ do_lowlevel_init: cmp r1, #3 /* has already been set up */ bicne r0, r0, #0xe7 orrne r0, r0, #0x83 /* L2CTLR[7:6] + L2CTLR[2:0] */ - - ldr r2, =0xFF000044 /* PRR */ - ldr r1, [r2] - and r1, r1, #0x7F00 - lsrs r1, r1, #8 - cmp r1, #0x45 /* 0x45 is ID of r8a7790 */ - bne L2CTLR_5_SKIP +#if defined(CONFIG_R8A7790) orrne r0, r0, #0x20 /* L2CTLR[5] */ -L2CTLR_5_SKIP: +#endif mcrne p15, 1, r0, c9, c0, 2 - _exit_init_l2_a15: ldr r3, =(CONFIG_SYS_INIT_SP_ADDR) sub sp, r3, #4 diff --git a/arch/arm/cpu/armv7/socfpga/clock_manager.c b/arch/arm/cpu/armv7/socfpga/clock_manager.c index d869f47c88..fa3b93a257 100644 --- a/arch/arm/cpu/armv7/socfpga/clock_manager.c +++ b/arch/arm/cpu/armv7/socfpga/clock_manager.c @@ -507,6 +507,19 @@ unsigned int cm_get_qspi_controller_clk_hz(void) return clock; } +unsigned int cm_get_spi_controller_clk_hz(void) +{ + uint32_t reg, clock = 0; + + clock = cm_get_per_vco_clk_hz(); + + /* get the clock prior L4 SP divider (periph_base_clk) */ + reg = readl(&clock_manager_base->per_pll.perbaseclk); + clock /= (reg + 1); + + return clock; +} + static void cm_print_clock_quick_summary(void) { printf("MPU %10ld kHz\n", cm_get_mpu_clk_hz() / 1000); @@ -518,6 +531,7 @@ static void cm_print_clock_quick_summary(void) printf("MMC %8d kHz\n", cm_get_mmc_controller_clk_hz() / 1000); printf("QSPI %8d kHz\n", cm_get_qspi_controller_clk_hz() / 1000); printf("UART %8d kHz\n", cm_get_l4_sp_clk_hz() / 1000); + printf("SPI %8d kHz\n", cm_get_spi_controller_clk_hz() / 1000); } int set_cpu_clk_info(void) diff --git a/arch/arm/cpu/armv7/socfpga/misc.c b/arch/arm/cpu/armv7/socfpga/misc.c index 8c3e5f7cd4..73cffd3a8d 100644 --- a/arch/arm/cpu/armv7/socfpga/misc.c +++ b/arch/arm/cpu/armv7/socfpga/misc.c @@ -202,6 +202,12 @@ int arch_early_init_r(void) /* Add device descriptor to FPGA device table */ socfpga_fpga_add(); + +#ifdef CONFIG_DESIGNWARE_SPI + /* Get Designware SPI controller out of reset */ + socfpga_spim_enable(); +#endif + return 0; } diff --git a/arch/arm/cpu/armv7/socfpga/reset_manager.c b/arch/arm/cpu/armv7/socfpga/reset_manager.c index 1d3a95d0c8..af9db850fe 100644 --- a/arch/arm/cpu/armv7/socfpga/reset_manager.c +++ b/arch/arm/cpu/armv7/socfpga/reset_manager.c @@ -104,3 +104,12 @@ void socfpga_emac_reset(int enable) #endif } } + +/* SPI Master enable (its held in reset by the preloader) */ +void socfpga_spim_enable(void) +{ + const void *reset = &reset_manager_base->per_mod_reset; + + clrbits_le32(reset, 1 << RSTMGR_PERMODRST_SPIM0_LSB); + clrbits_le32(reset, 1 << RSTMGR_PERMODRST_SPIM1_LSB); +} diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile index 24f1daee64..3b6ae47329 100644 --- a/arch/arm/cpu/armv7/sunxi/Makefile +++ b/arch/arm/cpu/armv7/sunxi/Makefile @@ -11,13 +11,14 @@ obj-y += timer.o obj-y += board.o obj-y += clock.o obj-y += pinmux.o -obj-$(CONFIG_SUN6I) += prcm.o -obj-$(CONFIG_SUN8I) += prcm.o -obj-$(CONFIG_SUN4I) += clock_sun4i.o -obj-$(CONFIG_SUN5I) += clock_sun4i.o -obj-$(CONFIG_SUN6I) += clock_sun6i.o -obj-$(CONFIG_SUN7I) += clock_sun4i.o -obj-$(CONFIG_SUN8I) += clock_sun6i.o +obj-$(CONFIG_MACH_SUN6I) += prcm.o +obj-$(CONFIG_MACH_SUN8I) += prcm.o +obj-$(CONFIG_MACH_SUN6I) += p2wi.o +obj-$(CONFIG_MACH_SUN4I) += clock_sun4i.o +obj-$(CONFIG_MACH_SUN5I) += clock_sun4i.o +obj-$(CONFIG_MACH_SUN6I) += clock_sun6i.o +obj-$(CONFIG_MACH_SUN7I) += clock_sun4i.o +obj-$(CONFIG_MACH_SUN8I) += clock_sun6i.o ifndef CONFIG_SPL_BUILD obj-y += cpu_info.o @@ -27,9 +28,10 @@ endif endif ifdef CONFIG_SPL_BUILD -obj-$(CONFIG_SUN4I) += dram.o -obj-$(CONFIG_SUN5I) += dram.o -obj-$(CONFIG_SUN7I) += dram.o +obj-$(CONFIG_MACH_SUN4I) += dram_sun4i.o +obj-$(CONFIG_MACH_SUN5I) += dram_sun4i.o +obj-$(CONFIG_MACH_SUN6I) += dram_sun6i.o +obj-$(CONFIG_MACH_SUN7I) += dram_sun4i.o ifdef CONFIG_SPL_FEL obj-y += start.o endif diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c index 06eb6768e8..9b3e80c24a 100644 --- a/arch/arm/cpu/armv7/sunxi/board.c +++ b/arch/arm/cpu/armv7/sunxi/board.c @@ -51,7 +51,7 @@ u32 spl_boot_mode(void) int gpio_init(void) { #if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F) -#if defined(CONFIG_SUN4I) || defined(CONFIG_SUN7I) +#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) /* disable GPB22,23 as uart0 tx,rx to avoid conflict */ sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT); sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT); @@ -59,23 +59,23 @@ int gpio_init(void) sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF2_UART0_TX); sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF4_UART0_RX); sunxi_gpio_set_pull(SUNXI_GPF(4), 1); -#elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_SUN4I) || defined(CONFIG_SUN7I)) +#elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)) sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB22_UART0_TX); sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB23_UART0_RX); sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP); -#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_SUN5I) +#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN5I) sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB19_UART0_TX); sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB20_UART0_RX); sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP); -#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_SUN6I) +#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN6I) sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH20_UART0_TX); sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH21_UART0_RX); sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP); -#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_SUN5I) +#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I) sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG3_UART1_TX); sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG4_UART1_RX); sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP); -#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_SUN8I) +#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I) sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL2_R_UART_TX); sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL3_R_UART_RX); sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP); @@ -88,7 +88,7 @@ int gpio_init(void) void reset_cpu(ulong addr) { -#if defined(CONFIG_SUN4I) || defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I) +#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I) static const struct sunxi_wdog *wdog = &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog; @@ -100,7 +100,7 @@ void reset_cpu(ulong addr) /* sun5i sometimes gets stuck without this */ writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode); } -#else /* CONFIG_SUN6I || CONFIG_SUN8I || .. */ +#else /* CONFIG_MACH_SUN6I || CONFIG_MACH_SUN8I || .. */ static const struct sunxi_wdog *wdog = ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog; @@ -114,8 +114,13 @@ void reset_cpu(ulong addr) /* do some early init */ void s_init(void) { -#if !defined CONFIG_SPL_BUILD && (defined CONFIG_SUN7I || \ - defined CONFIG_SUN6I || defined CONFIG_SUN8I) +#if defined CONFIG_SPL_BUILD && defined CONFIG_MACH_SUN6I + /* Magic (undocmented) value taken from boot0, without this DRAM + * access gets messed up (seems cache related) */ + setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800); +#endif +#if !defined CONFIG_SPL_BUILD && (defined CONFIG_MACH_SUN7I || \ + defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I) /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */ asm volatile( "mrc p15, 0, r0, c1, c0, 1\n" diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c index 4a0d64fb30..a0e49d179f 100644 --- a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c +++ b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c @@ -35,7 +35,7 @@ void clock_init_safe(void) APB0_DIV_1 << APB0_DIV_SHIFT | CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT, &ccm->cpu_ahb_apb0_cfg); -#ifdef CONFIG_SUN7I +#ifdef CONFIG_MACH_SUN7I setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_DMA); #endif writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg); diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c index 1eae9767d0..16ab6f3729 100644 --- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c +++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c @@ -16,6 +16,33 @@ #include <asm/arch/prcm.h> #include <asm/arch/sys_proto.h> +#ifdef CONFIG_SPL_BUILD +void clock_init_safe(void) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + struct sunxi_prcm_reg * const prcm = + (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE; + + /* Set PLL ldo voltage without this PLL6 does not work properly */ + clrsetbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK, + PRCM_PLL_CTRL_LDO_KEY); + clrsetbits_le32(&prcm->pll_ctrl1, ~PRCM_PLL_CTRL_LDO_KEY_MASK, + PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN | + PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140)); + clrbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK); + + clock_set_pll1(408000000); + + writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div); + + writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg); + + writel(MBUS_CLK_DEFAULT, &ccm->mbus0_clk_cfg); + writel(MBUS_CLK_DEFAULT, &ccm->mbus1_clk_cfg); +} +#endif + void clock_init_uart(void) { struct sunxi_ccm_reg *const ccm = @@ -65,6 +92,56 @@ int clock_twi_onoff(int port, int state) return 0; } +#ifdef CONFIG_SPL_BUILD +void clock_set_pll1(unsigned int clk) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + int k = 1; + int m = 1; + + if (clk > 1152000000) { + k = 2; + } else if (clk > 768000000) { + k = 3; + m = 2; + } + + /* Switch to 24MHz clock while changing PLL1 */ + writel(AXI_DIV_3 << AXI_DIV_SHIFT | + ATB_DIV_2 << ATB_DIV_SHIFT | + CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT, + &ccm->cpu_axi_cfg); + + /* PLL1 rate = 24000000 * n * k / m */ + writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_MAGIC | + CCM_PLL1_CTRL_N(clk / (24000000 * k / m)) | + CCM_PLL1_CTRL_K(k) | CCM_PLL1_CTRL_M(m), &ccm->pll1_cfg); + sdelay(200); + + /* Switch CPU to PLL1 */ + writel(AXI_DIV_3 << AXI_DIV_SHIFT | + ATB_DIV_2 << ATB_DIV_SHIFT | + CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT, + &ccm->cpu_axi_cfg); +} +#endif + +void clock_set_pll5(unsigned int clk) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + const int k = 2; + const int m = 1; + + /* PLL5 rate = 24000000 * n * k / m */ + writel(CCM_PLL5_CTRL_EN | CCM_PLL5_CTRL_UPD | + CCM_PLL5_CTRL_N(clk / (24000000 * k / m)) | + CCM_PLL5_CTRL_K(k) | CCM_PLL5_CTRL_M(m), &ccm->pll5_cfg); + + udelay(5500); +} + unsigned int clock_get_pll6(void) { struct sunxi_ccm_reg *const ccm = diff --git a/arch/arm/cpu/armv7/sunxi/cpu_info.c b/arch/arm/cpu/armv7/sunxi/cpu_info.c index 4f2a09cd2e..41b9add297 100644 --- a/arch/arm/cpu/armv7/sunxi/cpu_info.c +++ b/arch/arm/cpu/armv7/sunxi/cpu_info.c @@ -13,9 +13,9 @@ #ifdef CONFIG_DISPLAY_CPUINFO int print_cpuinfo(void) { -#ifdef CONFIG_SUN4I +#ifdef CONFIG_MACH_SUN4I puts("CPU: Allwinner A10 (SUN4I)\n"); -#elif defined CONFIG_SUN5I +#elif defined CONFIG_MACH_SUN5I u32 val = readl(SUNXI_SID_BASE + 0x08); switch ((val >> 12) & 0xf) { case 0: puts("CPU: Allwinner A12 (SUN5I)\n"); break; @@ -23,11 +23,11 @@ int print_cpuinfo(void) case 7: puts("CPU: Allwinner A10s (SUN5I)\n"); break; default: puts("CPU: Allwinner A1X (SUN5I)\n"); } -#elif defined CONFIG_SUN6I +#elif defined CONFIG_MACH_SUN6I puts("CPU: Allwinner A31 (SUN6I)\n"); -#elif defined CONFIG_SUN7I +#elif defined CONFIG_MACH_SUN7I puts("CPU: Allwinner A20 (SUN7I)\n"); -#elif defined CONFIG_SUN8I +#elif defined CONFIG_MACH_SUN8I puts("CPU: Allwinner A23 (SUN8I)\n"); #else #warning Please update cpu_info.c with correct CPU information diff --git a/arch/arm/cpu/armv7/sunxi/dram.c b/arch/arm/cpu/armv7/sunxi/dram_sun4i.c index 3cf3cbf19a..dc9fdb930b 100644 --- a/arch/arm/cpu/armv7/sunxi/dram.c +++ b/arch/arm/cpu/armv7/sunxi/dram_sun4i.c @@ -74,7 +74,7 @@ static void mctl_ddr3_reset(void) struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; -#ifdef CONFIG_SUN4I +#ifdef CONFIG_MACH_SUN4I struct sunxi_timer_reg *timer = (struct sunxi_timer_reg *)SUNXI_TIMER_BASE; u32 reg_val; @@ -113,7 +113,7 @@ static void mctl_set_drive(void) { struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; -#ifdef CONFIG_SUN7I +#ifdef CONFIG_MACH_SUN7I clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3) | (0x3 << 28), #else clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3), @@ -202,7 +202,7 @@ static void mctl_enable_dllx(u32 phase) } static u32 hpcr_value[32] = { -#ifdef CONFIG_SUN5I +#ifdef CONFIG_MACH_SUN5I 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -212,7 +212,7 @@ static u32 hpcr_value[32] = { 0x0301, 0x0301, 0x0301, 0x0301, 0x0301, 0x0301, 0x0301, 0 #endif -#ifdef CONFIG_SUN4I +#ifdef CONFIG_MACH_SUN4I 0x0301, 0x0301, 0x0301, 0x0301, 0x0301, 0x0301, 0, 0, 0, 0, 0, 0, @@ -222,7 +222,7 @@ static u32 hpcr_value[32] = { 0x1035, 0x1031, 0x0731, 0x1035, 0x1031, 0x0301, 0x0301, 0x0731 #endif -#ifdef CONFIG_SUN7I +#ifdef CONFIG_MACH_SUN7I 0x0301, 0x0301, 0x0301, 0x0301, 0x0301, 0x0301, 0x0301, 0x0301, 0, 0, 0, 0, @@ -304,7 +304,7 @@ static void mctl_setup_dram_clock(u32 clk, u32 mbus_clk) setbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_DDR_CLK); -#if defined(CONFIG_SUN4I) || defined(CONFIG_SUN7I) +#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) /* reset GPS */ clrbits_le32(&ccm->gps_clk_cfg, CCM_GPS_CTRL_RESET | CCM_GPS_CTRL_GATE); setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_GPS); @@ -318,7 +318,7 @@ static void mctl_setup_dram_clock(u32 clk, u32 mbus_clk) /* PLL5P and PLL6 are the potential clock sources for MBUS */ pll6x_clk = clock_get_pll6() / 1000000; -#ifdef CONFIG_SUN7I +#ifdef CONFIG_MACH_SUN7I pll6x_clk *= 2; /* sun7i uses PLL6*2, sun5i uses just PLL6 */ #endif pll5p_clk = clock_get_pll5p() / 1000000; @@ -348,7 +348,7 @@ static void mctl_setup_dram_clock(u32 clk, u32 mbus_clk) * open DRAMC AHB & DLL register clock * close it first */ -#if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I) +#if defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I) clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM | CCM_AHB_GATE_DLL); #else clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM); @@ -356,7 +356,7 @@ static void mctl_setup_dram_clock(u32 clk, u32 mbus_clk) udelay(22); /* then open it */ -#if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I) +#if defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I) setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM | CCM_AHB_GATE_DLL); #else setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM); @@ -417,7 +417,7 @@ static int dramc_scan_readpipe(void) static void dramc_clock_output_en(u32 on) { -#if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I) +#if defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I) struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; if (on) @@ -425,7 +425,7 @@ static void dramc_clock_output_en(u32 on) else clrbits_le32(&dram->mcr, DRAM_MCR_DCLK_OUT); #endif -#ifdef CONFIG_SUN4I +#ifdef CONFIG_MACH_SUN4I struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; if (on) setbits_le32(&ccm->dram_clk_cfg, CCM_DRAM_CTRL_DCLK_OUT); @@ -527,7 +527,7 @@ static void mctl_set_impedance(u32 zq, u32 odt_en) u32 reg_val; u32 zprog = zq & 0xFF, zdata = (zq >> 8) & 0xFFFFF; -#ifndef CONFIG_SUN7I +#ifndef CONFIG_MACH_SUN7I /* Appears that some kind of automatically initiated default * ZQ calibration is already in progress at this point on sun4i/sun5i * hardware, but not on sun7i. So it is reasonable to wait for its @@ -539,7 +539,7 @@ static void mctl_set_impedance(u32 zq, u32 odt_en) if (!odt_en) return; -#ifdef CONFIG_SUN7I +#ifdef CONFIG_MACH_SUN7I /* Enabling ODT in SDR_IOCR on sun7i hardware results in a deadlock * unless bit 24 is set in SDR_ZQCR1. Not much is known about the * SDR_ZQCR1 register, but there are hints indicating that it might @@ -597,7 +597,7 @@ static unsigned long dramc_init_helper(struct dram_para *para) /* dram clock off */ dramc_clock_output_en(0); -#ifdef CONFIG_SUN4I +#ifdef CONFIG_MACH_SUN4I /* select dram controller 1 */ writel(DRAM_CSEL_MAGIC, &dram->csel); #endif @@ -654,7 +654,7 @@ static unsigned long dramc_init_helper(struct dram_para *para) writel(para->tpr2, &dram->tpr2); reg_val = DRAM_MR_BURST_LENGTH(0x0); -#if (defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)) +#if (defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)) reg_val |= DRAM_MR_POWER_DOWN; #endif reg_val |= DRAM_MR_CAS_LAT(para->cas - 4); @@ -668,7 +668,7 @@ static unsigned long dramc_init_helper(struct dram_para *para) /* disable drift compensation and set passive DQS window mode */ clrsetbits_le32(&dram->ccr, DRAM_CCR_DQS_DRIFT_COMP, DRAM_CCR_DQS_GATE); -#ifdef CONFIG_SUN7I +#ifdef CONFIG_MACH_SUN7I /* Command rate timing mode 2T & 1T */ if (para->tpr4 & 0x1) setbits_le32(&dram->ccr, DRAM_CCR_COMMAND_RATE_1T); @@ -718,7 +718,7 @@ unsigned long dramc_init(struct dram_para *para) /* try to autodetect the DRAM bus width and density */ para->io_width = 16; para->bus_width = 32; -#if defined(CONFIG_SUN4I) || defined(CONFIG_SUN5I) +#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) /* only A0-A14 address lines on A10/A13, limiting max density to 4096 */ para->density = 4096; #else diff --git a/arch/arm/cpu/armv7/sunxi/dram_sun6i.c b/arch/arm/cpu/armv7/sunxi/dram_sun6i.c new file mode 100644 index 0000000000..10a62416d2 --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/dram_sun6i.c @@ -0,0 +1,435 @@ +/* + * Sun6i platform dram controller init. + * + * (C) Copyright 2007-2012 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * Berg Xing <bergxing@allwinnertech.com> + * Tom Cubie <tangliang@allwinnertech.com> + * + * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <errno.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/dram.h> +#include <asm/arch/prcm.h> + +/* DRAM clk & zq defaults, maybe turn these into Kconfig options ? */ +#define DRAM_CLK_DEFAULT 312000000 +#define DRAM_ZQ_DEFAULT 0x78 + +struct dram_sun6i_para { + u8 bus_width; + u8 chan; + u8 rank; + u8 rows; + u16 page_size; +}; + +/* + * Wait up to 1s for value to be set in given part of reg. + */ +static void await_completion(u32 *reg, u32 mask, u32 val) +{ + unsigned long tmo = timer_get_us() + 1000000; + + while ((readl(reg) & mask) != val) { + if (timer_get_us() > tmo) + panic("Timeout initialising DRAM\n"); + } +} + +static void mctl_sys_init(void) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + const int dram_clk_div = 2; + + clock_set_pll5(DRAM_CLK_DEFAULT * dram_clk_div); + + clrsetbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_DIV0_MASK, + CCM_DRAMCLK_CFG_DIV0(dram_clk_div) | CCM_DRAMCLK_CFG_RST | + CCM_DRAMCLK_CFG_UPD); + await_completion(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_UPD, 0); + + writel(MDFS_CLK_DEFAULT, &ccm->mdfs_clk_cfg); + + /* deassert mctl reset */ + setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL); + + /* enable mctl clock */ + setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL); +} + +static void mctl_dll_init(int ch_index, struct dram_sun6i_para *para) +{ + struct sunxi_mctl_phy_reg *mctl_phy; + + if (ch_index == 0) + mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE; + else + mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY1_BASE; + + /* disable + reset dlls */ + writel(MCTL_DLLCR_DISABLE, &mctl_phy->acdllcr); + writel(MCTL_DLLCR_DISABLE, &mctl_phy->dx0dllcr); + writel(MCTL_DLLCR_DISABLE, &mctl_phy->dx1dllcr); + if (para->bus_width == 32) { + writel(MCTL_DLLCR_DISABLE, &mctl_phy->dx2dllcr); + writel(MCTL_DLLCR_DISABLE, &mctl_phy->dx3dllcr); + } + udelay(2); + + /* enable + reset dlls */ + writel(0, &mctl_phy->acdllcr); + writel(0, &mctl_phy->dx0dllcr); + writel(0, &mctl_phy->dx1dllcr); + if (para->bus_width == 32) { + writel(0, &mctl_phy->dx2dllcr); + writel(0, &mctl_phy->dx3dllcr); + } + udelay(22); + + /* enable and release reset of dlls */ + writel(MCTL_DLLCR_NRESET, &mctl_phy->acdllcr); + writel(MCTL_DLLCR_NRESET, &mctl_phy->dx0dllcr); + writel(MCTL_DLLCR_NRESET, &mctl_phy->dx1dllcr); + if (para->bus_width == 32) { + writel(MCTL_DLLCR_NRESET, &mctl_phy->dx2dllcr); + writel(MCTL_DLLCR_NRESET, &mctl_phy->dx3dllcr); + } + udelay(22); +} + +static bool mctl_rank_detect(u32 *gsr0, int rank) +{ + const u32 done = MCTL_DX_GSR0_RANK0_TRAIN_DONE << rank; + const u32 err = MCTL_DX_GSR0_RANK0_TRAIN_ERR << rank; + + await_completion(gsr0, done, done); + await_completion(gsr0 + 0x10, done, done); + + return !(readl(gsr0) & err) && !(readl(gsr0 + 0x10) & err); +} + +static void mctl_channel_init(int ch_index, struct dram_sun6i_para *para) +{ + struct sunxi_mctl_com_reg * const mctl_com = + (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; + struct sunxi_mctl_ctl_reg *mctl_ctl; + struct sunxi_mctl_phy_reg *mctl_phy; + + if (ch_index == 0) { + mctl_ctl = (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE; + } else { + mctl_ctl = (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL1_BASE; + mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY1_BASE; + } + + writel(MCTL_MCMD_NOP, &mctl_ctl->mcmd); + await_completion(&mctl_ctl->mcmd, MCTL_MCMD_BUSY, 0); + + /* PHY initialization */ + writel(MCTL_PGCR, &mctl_phy->pgcr); + writel(MCTL_MR0, &mctl_phy->mr0); + writel(MCTL_MR1, &mctl_phy->mr1); + writel(MCTL_MR2, &mctl_phy->mr2); + writel(MCTL_MR3, &mctl_phy->mr3); + + writel((MCTL_TITMSRST << 18) | (MCTL_TDLLLOCK << 6) | MCTL_TDLLSRST, + &mctl_phy->ptr0); + /* Unknown magic performed by boot0 */ + if ((readl(SUNXI_RTC_BASE + 0x20c) & 3) == 2) + setbits_le32(&mctl_phy->ptr0, 1 << 18); + + writel((MCTL_TDINIT1 << 19) | MCTL_TDINIT0, &mctl_phy->ptr1); + writel((MCTL_TDINIT3 << 17) | MCTL_TDINIT2, &mctl_phy->ptr2); + + writel((MCTL_TCCD << 31) | (MCTL_TRC << 25) | (MCTL_TRRD << 21) | + (MCTL_TRAS << 16) | (MCTL_TRCD << 12) | (MCTL_TRP << 8) | + (MCTL_TWTR << 5) | (MCTL_TRTP << 2) | (MCTL_TMRD << 0), + &mctl_phy->dtpr0); + + writel((MCTL_TDQSCKMAX << 27) | (MCTL_TDQSCK << 24) | + (MCTL_TRFC << 16) | (MCTL_TRTODT << 11) | + ((MCTL_TMOD - 12) << 9) | (MCTL_TFAW << 3) | (0 << 2) | + (MCTL_TAOND << 0), &mctl_phy->dtpr1); + + writel((MCTL_TDLLK << 19) | (MCTL_TCKE << 15) | (MCTL_TXPDLL << 10) | + (MCTL_TEXSR << 0), &mctl_phy->dtpr2); + + writel(1, &mctl_ctl->dfitphyupdtype0); + writel(MCTL_DCR_DDR3, &mctl_phy->dcr); + writel(MCTL_DSGCR, &mctl_phy->dsgcr); + writel(MCTL_DXCCR, &mctl_phy->dxccr); + writel(MCTL_DX_GCR | MCTL_DX_GCR_EN, &mctl_phy->dx0gcr); + writel(MCTL_DX_GCR | MCTL_DX_GCR_EN, &mctl_phy->dx1gcr); + writel(MCTL_DX_GCR | MCTL_DX_GCR_EN, &mctl_phy->dx2gcr); + writel(MCTL_DX_GCR | MCTL_DX_GCR_EN, &mctl_phy->dx3gcr); + + await_completion(&mctl_phy->pgsr, 0x03, 0x03); + + writel(DRAM_ZQ_DEFAULT, &mctl_phy->zq0cr1); + + setbits_le32(&mctl_phy->pir, MCTL_PIR_CLEAR_STATUS); + writel(MCTL_PIR_STEP1, &mctl_phy->pir); + udelay(10); + await_completion(&mctl_phy->pgsr, 0x1f, 0x1f); + + /* rank detect */ + if (!mctl_rank_detect(&mctl_phy->dx0gsr0, 1)) { + para->rank = 1; + clrbits_le32(&mctl_phy->pgcr, MCTL_PGCR_RANK); + } + + /* + * channel detect, check channel 1 dx0 and dx1 have rank 0, if not + * assume nothing is connected to channel 1. + */ + if (ch_index == 1 && !mctl_rank_detect(&mctl_phy->dx0gsr0, 0)) { + para->chan = 1; + clrbits_le32(&mctl_com->ccr, MCTL_CCR_CH1_CLK_EN); + return; + } + + /* bus width detect, if dx2 and dx3 don't have rank 0, assume 16 bit */ + if (!mctl_rank_detect(&mctl_phy->dx2gsr0, 0)) { + para->bus_width = 16; + para->page_size = 2048; + setbits_le32(&mctl_phy->dx2dllcr, MCTL_DLLCR_DISABLE); + setbits_le32(&mctl_phy->dx3dllcr, MCTL_DLLCR_DISABLE); + clrbits_le32(&mctl_phy->dx2gcr, MCTL_DX_GCR_EN); + clrbits_le32(&mctl_phy->dx3gcr, MCTL_DX_GCR_EN); + } + + setbits_le32(&mctl_phy->pir, MCTL_PIR_CLEAR_STATUS); + writel(MCTL_PIR_STEP2, &mctl_phy->pir); + udelay(10); + await_completion(&mctl_phy->pgsr, 0x11, 0x11); + + if (readl(&mctl_phy->pgsr) & MCTL_PGSR_TRAIN_ERR_MASK) + panic("Training error initialising DRAM\n"); + + /* Move to configure state */ + writel(MCTL_SCTL_CONFIG, &mctl_ctl->sctl); + await_completion(&mctl_ctl->sstat, 0x07, 0x01); + + /* Set number of clks per micro-second */ + writel(DRAM_CLK_DEFAULT / 1000000, &mctl_ctl->togcnt1u); + /* Set number of clks per 100 nano-seconds */ + writel(DRAM_CLK_DEFAULT / 10000000, &mctl_ctl->togcnt100n); + /* Set memory timing registers */ + writel(MCTL_TREFI, &mctl_ctl->trefi); + writel(MCTL_TMRD, &mctl_ctl->tmrd); + writel(MCTL_TRFC, &mctl_ctl->trfc); + writel((MCTL_TPREA << 16) | MCTL_TRP, &mctl_ctl->trp); + writel(MCTL_TRTW, &mctl_ctl->trtw); + writel(MCTL_TAL, &mctl_ctl->tal); + writel(MCTL_TCL, &mctl_ctl->tcl); + writel(MCTL_TCWL, &mctl_ctl->tcwl); + writel(MCTL_TRAS, &mctl_ctl->tras); + writel(MCTL_TRC, &mctl_ctl->trc); + writel(MCTL_TRCD, &mctl_ctl->trcd); + writel(MCTL_TRRD, &mctl_ctl->trrd); + writel(MCTL_TRTP, &mctl_ctl->trtp); + writel(MCTL_TWR, &mctl_ctl->twr); + writel(MCTL_TWTR, &mctl_ctl->twtr); + writel(MCTL_TEXSR, &mctl_ctl->texsr); + writel(MCTL_TXP, &mctl_ctl->txp); + writel(MCTL_TXPDLL, &mctl_ctl->txpdll); + writel(MCTL_TZQCS, &mctl_ctl->tzqcs); + writel(MCTL_TZQCSI, &mctl_ctl->tzqcsi); + writel(MCTL_TDQS, &mctl_ctl->tdqs); + writel(MCTL_TCKSRE, &mctl_ctl->tcksre); + writel(MCTL_TCKSRX, &mctl_ctl->tcksrx); + writel(MCTL_TCKE, &mctl_ctl->tcke); + writel(MCTL_TMOD, &mctl_ctl->tmod); + writel(MCTL_TRSTL, &mctl_ctl->trstl); + writel(MCTL_TZQCL, &mctl_ctl->tzqcl); + writel(MCTL_TMRR, &mctl_ctl->tmrr); + writel(MCTL_TCKESR, &mctl_ctl->tckesr); + writel(MCTL_TDPD, &mctl_ctl->tdpd); + + /* Unknown magic performed by boot0 */ + setbits_le32(&mctl_ctl->dfiodtcfg, 1 << 3); + clrbits_le32(&mctl_ctl->dfiodtcfg1, 0x1f); + + /* Select 16/32-bits mode for MCTL */ + if (para->bus_width == 16) + setbits_le32(&mctl_ctl->ppcfg, 1); + + /* Set DFI timing registers */ + writel(MCTL_TCWL, &mctl_ctl->dfitphywrl); + writel(MCTL_TCL - 1, &mctl_ctl->dfitrdden); + writel(MCTL_DFITPHYRDL, &mctl_ctl->dfitphyrdl); + writel(MCTL_DFISTCFG0, &mctl_ctl->dfistcfg0); + + writel(MCTL_MCFG_DDR3, &mctl_ctl->mcfg); + + /* DFI update configuration register */ + writel(MCTL_DFIUPDCFG_UPD, &mctl_ctl->dfiupdcfg); + + /* Move to access state */ + writel(MCTL_SCTL_ACCESS, &mctl_ctl->sctl); + await_completion(&mctl_ctl->sstat, 0x07, 0x03); +} + +static void mctl_com_init(struct dram_sun6i_para *para) +{ + struct sunxi_mctl_com_reg * const mctl_com = + (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; + struct sunxi_mctl_phy_reg * const mctl_phy1 = + (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY1_BASE; + struct sunxi_prcm_reg * const prcm = + (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE; + + writel(MCTL_CR_UNKNOWN | MCTL_CR_CHANNEL(para->chan) | MCTL_CR_DDR3 | + ((para->bus_width == 32) ? MCTL_CR_BUSW32 : MCTL_CR_BUSW16) | + MCTL_CR_PAGE_SIZE(para->page_size) | MCTL_CR_ROW(para->rows) | + MCTL_CR_BANK(1) | MCTL_CR_RANK(para->rank), &mctl_com->cr); + + /* Unknown magic performed by boot0 */ + setbits_le32(&mctl_com->dbgcr, (1 << 6)); + + if (para->chan == 1) { + /* Shutdown channel 1 */ + setbits_le32(&mctl_phy1->aciocr, MCTL_ACIOCR_DISABLE); + setbits_le32(&mctl_phy1->dxccr, MCTL_DXCCR_DISABLE); + clrbits_le32(&mctl_phy1->dsgcr, MCTL_DSGCR_ENABLE); + /* + * CH0 ?? this is what boot0 does. Leave as is until we can + * confirm this. + */ + setbits_le32(&prcm->vdd_sys_pwroff, + PRCM_VDD_SYS_DRAM_CH0_PAD_HOLD_PWROFF); + } +} + +static void mctl_port_cfg(void) +{ + struct sunxi_mctl_com_reg * const mctl_com = + (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + /* enable DRAM AXI clock for CPU access */ + setbits_le32(&ccm->axi_gate, 1 << AXI_GATE_OFFSET_DRAM); + + /* Bunch of magic writes performed by boot0 */ + writel(0x00400302, &mctl_com->rmcr[0]); + writel(0x01000307, &mctl_com->rmcr[1]); + writel(0x00400302, &mctl_com->rmcr[2]); + writel(0x01000307, &mctl_com->rmcr[3]); + writel(0x01000307, &mctl_com->rmcr[4]); + writel(0x01000303, &mctl_com->rmcr[6]); + writel(0x01000303, &mctl_com->mmcr[0]); + writel(0x00400310, &mctl_com->mmcr[1]); + writel(0x01000307, &mctl_com->mmcr[2]); + writel(0x01000303, &mctl_com->mmcr[3]); + writel(0x01800303, &mctl_com->mmcr[4]); + writel(0x01800303, &mctl_com->mmcr[5]); + writel(0x01800303, &mctl_com->mmcr[6]); + writel(0x01800303, &mctl_com->mmcr[7]); + writel(0x01000303, &mctl_com->mmcr[8]); + writel(0x00000002, &mctl_com->mmcr[15]); + writel(0x00000310, &mctl_com->mbagcr[0]); + writel(0x00400310, &mctl_com->mbagcr[1]); + writel(0x00400310, &mctl_com->mbagcr[2]); + writel(0x00000307, &mctl_com->mbagcr[3]); + writel(0x00000317, &mctl_com->mbagcr[4]); + writel(0x00000307, &mctl_com->mbagcr[5]); +} + +static bool mctl_mem_matches(u32 offset) +{ + const int match_count = 64; + int i, matches = 0; + + for (i = 0; i < match_count; i++) { + if (readl(CONFIG_SYS_SDRAM_BASE + i * 4) == + readl(CONFIG_SYS_SDRAM_BASE + offset + i * 4)) + matches++; + } + + return matches == match_count; +} + +unsigned long sunxi_dram_init(void) +{ + struct sunxi_mctl_com_reg * const mctl_com = + (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; + u32 offset; + int bank, bus, columns; + + /* Set initial parameters, these get modified by the autodetect code */ + struct dram_sun6i_para para = { + .bus_width = 32, + .chan = 2, + .rank = 2, + .page_size = 4096, + .rows = 16, + }; + + mctl_sys_init(); + + mctl_dll_init(0, ¶); + mctl_dll_init(1, ¶); + + setbits_le32(&mctl_com->ccr, + MCTL_CCR_MASTER_CLK_EN | + MCTL_CCR_CH0_CLK_EN | + MCTL_CCR_CH1_CLK_EN); + + mctl_channel_init(0, ¶); + mctl_channel_init(1, ¶); + mctl_com_init(¶); + mctl_port_cfg(); + + /* + * Change to 1 ch / sequence / 8192 byte pages / 16 rows / + * 8 bit banks / 1 rank mode. + */ + clrsetbits_le32(&mctl_com->cr, + MCTL_CR_CHANNEL_MASK | MCTL_CR_PAGE_SIZE_MASK | + MCTL_CR_ROW_MASK | MCTL_CR_BANK_MASK | MCTL_CR_RANK_MASK, + MCTL_CR_CHANNEL(1) | MCTL_CR_SEQUENCE | + MCTL_CR_PAGE_SIZE(8192) | MCTL_CR_ROW(16) | + MCTL_CR_BANK(1) | MCTL_CR_RANK(1)); + + /* Detect and set page size */ + for (columns = 7; columns < 20; columns++) { + if (mctl_mem_matches(1 << columns)) + break; + } + bus = (para.bus_width == 32) ? 2 : 1; + columns -= bus; + para.page_size = (1 << columns) * (bus << 1); + clrsetbits_le32(&mctl_com->cr, MCTL_CR_PAGE_SIZE_MASK, + MCTL_CR_PAGE_SIZE(para.page_size)); + + /* Detect and set rows */ + for (para.rows = 11; para.rows < 16; para.rows++) { + offset = 1 << (para.rows + columns + bus); + if (mctl_mem_matches(offset)) + break; + } + clrsetbits_le32(&mctl_com->cr, MCTL_CR_ROW_MASK, + MCTL_CR_ROW(para.rows)); + + /* Detect bank size */ + offset = 1 << (para.rows + columns + bus + 2); + bank = mctl_mem_matches(offset) ? 0 : 1; + + /* Restore interleave, chan and rank values, set bank size */ + clrsetbits_le32(&mctl_com->cr, + MCTL_CR_CHANNEL_MASK | MCTL_CR_SEQUENCE | + MCTL_CR_BANK_MASK | MCTL_CR_RANK_MASK, + MCTL_CR_CHANNEL(para.chan) | MCTL_CR_BANK(bank) | + MCTL_CR_RANK(para.rank)); + + return 1 << (para.rank + para.rows + bank + columns + para.chan + bus); +} diff --git a/arch/arm/cpu/armv7/sunxi/p2wi.c b/arch/arm/cpu/armv7/sunxi/p2wi.c new file mode 100644 index 0000000000..48613bd0ea --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/p2wi.c @@ -0,0 +1,117 @@ +/* + * Sunxi A31 Power Management Unit + * + * (C) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl> + * http://linux-sunxi.org + * + * Based on sun6i sources and earlier U-Boot Allwiner A10 SPL work + * + * (C) Copyright 2006-2013 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * Berg Xing <bergxing@allwinnertech.com> + * Tom Cubie <tangliang@allwinnertech.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <errno.h> +#include <asm/io.h> +#include <asm/arch/cpu.h> +#include <asm/arch/gpio.h> +#include <asm/arch/p2wi.h> +#include <asm/arch/prcm.h> +#include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> + +void p2wi_init(void) +{ + struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUNXI_P2WI_BASE; + + /* Enable p2wi and PIO clk, and de-assert their resets */ + prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_P2WI); + + sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUNXI_GPL0_R_P2WI_SCK); + sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUNXI_GPL1_R_P2WI_SDA); + + /* Reset p2wi controller and set clock to CLKIN(12)/8 = 1.5 MHz */ + writel(P2WI_CTRL_RESET, &p2wi->ctrl); + sdelay(0x100); + writel(P2WI_CC_SDA_OUT_DELAY(1) | P2WI_CC_CLK_DIV(8), + &p2wi->cc); +} + +int p2wi_change_to_p2wi_mode(u8 slave_addr, u8 ctrl_reg, u8 init_data) +{ + struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUNXI_P2WI_BASE; + unsigned long tmo = timer_get_us() + 1000000; + + writel(P2WI_PM_DEV_ADDR(slave_addr) | + P2WI_PM_CTRL_ADDR(ctrl_reg) | + P2WI_PM_INIT_DATA(init_data) | + P2WI_PM_INIT_SEND, + &p2wi->pm); + + while ((readl(&p2wi->pm) & P2WI_PM_INIT_SEND)) { + if (timer_get_us() > tmo) + return -ETIME; + } + + return 0; +} + +static int p2wi_await_trans(void) +{ + struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUNXI_P2WI_BASE; + unsigned long tmo = timer_get_us() + 1000000; + int ret; + u8 reg; + + while (1) { + reg = readl(&p2wi->status); + if (reg & P2WI_STAT_TRANS_ERR) { + ret = -EIO; + break; + } + if (reg & P2WI_STAT_TRANS_DONE) { + ret = 0; + break; + } + if (timer_get_us() > tmo) { + ret = -ETIME; + break; + } + } + writel(reg, &p2wi->status); /* Clear status bits */ + return ret; +} + +int p2wi_read(const u8 addr, u8 *data) +{ + struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUNXI_P2WI_BASE; + int ret; + + writel(P2WI_DATADDR_BYTE_1(addr), &p2wi->dataddr0); + writel(P2WI_DATA_NUM_BYTES(1) | + P2WI_DATA_NUM_BYTES_READ, &p2wi->numbytes); + writel(P2WI_STAT_TRANS_DONE, &p2wi->status); + writel(P2WI_CTRL_TRANS_START, &p2wi->ctrl); + + ret = p2wi_await_trans(); + + *data = readl(&p2wi->data0) & P2WI_DATA_BYTE_1_MASK; + return ret; +} + +int p2wi_write(const u8 addr, u8 data) +{ + struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUNXI_P2WI_BASE; + + writel(P2WI_DATADDR_BYTE_1(addr), &p2wi->dataddr0); + writel(P2WI_DATA_BYTE_1(data), &p2wi->data0); + writel(P2WI_DATA_NUM_BYTES(1), &p2wi->numbytes); + writel(P2WI_STAT_TRANS_DONE, &p2wi->status); + writel(P2WI_CTRL_TRANS_START, &p2wi->ctrl); + + return p2wi_await_trans(); +} diff --git a/arch/arm/cpu/armv7/sunxi/pinmux.c b/arch/arm/cpu/armv7/sunxi/pinmux.c index 1f2843fcac..b026f78ca5 100644 --- a/arch/arm/cpu/armv7/sunxi/pinmux.c +++ b/arch/arm/cpu/armv7/sunxi/pinmux.c @@ -10,32 +10,42 @@ #include <asm/io.h> #include <asm/arch/gpio.h> -int sunxi_gpio_set_cfgpin(u32 pin, u32 val) +void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val) { - u32 bank = GPIO_BANK(pin); - u32 index = GPIO_CFG_INDEX(pin); - u32 offset = GPIO_CFG_OFFSET(pin); - struct sunxi_gpio *pio = BANK_TO_GPIO(bank); + u32 index = GPIO_CFG_INDEX(bank_offset); + u32 offset = GPIO_CFG_OFFSET(bank_offset); clrsetbits_le32(&pio->cfg[0] + index, 0xf << offset, val << offset); - - return 0; } -int sunxi_gpio_get_cfgpin(u32 pin) +void sunxi_gpio_set_cfgpin(u32 pin, u32 val) { - u32 cfg; u32 bank = GPIO_BANK(pin); - u32 index = GPIO_CFG_INDEX(pin); - u32 offset = GPIO_CFG_OFFSET(pin); struct sunxi_gpio *pio = BANK_TO_GPIO(bank); + sunxi_gpio_set_cfgbank(pio, pin, val); +} + +int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset) +{ + u32 index = GPIO_CFG_INDEX(bank_offset); + u32 offset = GPIO_CFG_OFFSET(bank_offset); + u32 cfg; + cfg = readl(&pio->cfg[0] + index); cfg >>= offset; return cfg & 0xf; } +int sunxi_gpio_get_cfgpin(u32 pin) +{ + u32 bank = GPIO_BANK(pin); + struct sunxi_gpio *pio = BANK_TO_GPIO(bank); + + return sunxi_gpio_get_cfgbank(pio, pin); +} + int sunxi_gpio_set_drv(u32 pin, u32 val) { u32 bank = GPIO_BANK(pin); diff --git a/arch/arm/cpu/armv7/sunxi/psci.S b/arch/arm/cpu/armv7/sunxi/psci.S index 0084c811f3..b9ea78b84e 100644 --- a/arch/arm/cpu/armv7/sunxi/psci.S +++ b/arch/arm/cpu/armv7/sunxi/psci.S @@ -87,8 +87,8 @@ psci_cpu_on: str r2, [r0] dsb - movw r0, #(SUNXI_CPUCFG_BASE & 0xffff) - movt r0, #(SUNXI_CPUCFG_BASE >> 16) + movw r0, #(SUN7I_CPUCFG_BASE & 0xffff) + movt r0, #(SUN7I_CPUCFG_BASE >> 16) @ CPU mask and r1, r1, #3 @ only care about first cluster diff --git a/arch/arm/cpu/armv7/tegra-common/Kconfig b/arch/arm/cpu/armv7/tegra-common/Kconfig index 3ea6d7651c..1446452c23 100644 --- a/arch/arm/cpu/armv7/tegra-common/Kconfig +++ b/arch/arm/cpu/armv7/tegra-common/Kconfig @@ -20,10 +20,6 @@ endchoice config USE_PRIVATE_LIBGCC default y if SPL_BUILD -config SYS_CPU - default "arm720t" if SPL_BUILD - default "armv7" if !SPL_BUILD - source "arch/arm/cpu/armv7/tegra20/Kconfig" source "arch/arm/cpu/armv7/tegra30/Kconfig" source "arch/arm/cpu/armv7/tegra114/Kconfig" diff --git a/arch/arm/cpu/armv7/uniphier/Kconfig b/arch/arm/cpu/armv7/uniphier/Kconfig index 524b193e58..36b7f11fbe 100644 --- a/arch/arm/cpu/armv7/uniphier/Kconfig +++ b/arch/arm/cpu/armv7/uniphier/Kconfig @@ -23,4 +23,40 @@ config MACH_PH1_SLD8 endchoice +config CMD_PINMON + bool "Enable boot mode pins monitor command" + depends on !SPL_BUILD + default y + help + The command "pinmon" shows the state of the boot mode pins. + The boot mode pins are latched when the system reset is deasserted + and determine which device the system should load a boot image from. + +config SOC_INIT + bool + default SPL_BUILD + +config DRAM_INIT + bool + default SPL_BUILD + +choice + prompt "DDR3 Frequency select" + depends on DRAM_INIT + +config DDR_FREQ_1600 + bool "DDR3 1600" + depends on MACH_PH1_PRO4 || MACH_PH1_LD4 + +config DDR_FREQ_1333 + bool "DDR3 1333" + depends on MACH_PH1_LD4 || MACH_PH1_SLD8 + +endchoice + +config DDR_FREQ + int + default 1333 if DDR_FREQ_1333 + default 1600 if DDR_FREQ_1600 + endmenu diff --git a/arch/arm/cpu/armv7/uniphier/Makefile b/arch/arm/cpu/armv7/uniphier/Makefile index 7cedddaadc..0f64d2591c 100644 --- a/arch/arm/cpu/armv7/uniphier/Makefile +++ b/arch/arm/cpu/armv7/uniphier/Makefile @@ -8,11 +8,12 @@ obj-$(CONFIG_SPL_BUILD) += spl.o obj-y += timer.o obj-y += reset.o obj-y += cache_uniphier.o +obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o obj-y += dram_init.o obj-$(CONFIG_DISPLAY_CPUINFO) += cpu_info.o obj-$(CONFIG_BOARD_LATE_INIT) += board_late_init.o obj-$(CONFIG_UNIPHIER_SMP) += smp.o -obj-$(if $(CONFIG_SPL_BUILD),,y) += cmd_pinmon.o +obj-$(CONFIG_CMD_PINMON) += cmd_pinmon.o obj-y += board_common.o obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += support_card.o diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/board_postclk_init.c b/arch/arm/cpu/armv7/uniphier/board_postclk_init.c index 4302277dfc..89e44bb95b 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/board_postclk_init.c +++ b/arch/arm/cpu/armv7/uniphier/board_postclk_init.c @@ -5,11 +5,13 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#include <common.h> +#include <linux/compiler.h> #include <asm/arch/led.h> #include <asm/arch/board.h> -void bcu_init(void); +void __weak bcu_init(void) +{ +}; void sbc_init(void); void sg_init(void); void pll_init(void); @@ -18,12 +20,15 @@ void clkrst_init(void); int board_postclk_init(void) { +#ifdef CONFIG_SOC_INIT bcu_init(); sbc_init(); sg_init(); + uniphier_board_reset(); + pll_init(); uniphier_board_init(); @@ -33,7 +38,7 @@ int board_postclk_init(void) clkrst_init(); led_write(B, 2, , ); - +#endif pin_init(); led_write(B, 3, , ); diff --git a/arch/arm/cpu/armv7/uniphier/dram_init.c b/arch/arm/cpu/armv7/uniphier/dram_init.c index 5465a0e6bf..7de657b7af 100644 --- a/arch/arm/cpu/armv7/uniphier/dram_init.c +++ b/arch/arm/cpu/armv7/uniphier/dram_init.c @@ -16,7 +16,7 @@ int dram_init(void) DECLARE_GLOBAL_DATA_PTR; gd->ram_size = CONFIG_SYS_SDRAM_SIZE; -#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) +#ifdef CONFIG_DRAM_INIT led_write(B, 4, , ); { diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile b/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile index 781b511a97..fba1cc7498 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile +++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile @@ -5,7 +5,7 @@ obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o obj-y += platdevice.o obj-y += boot-mode.o -obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o bcu_init.o \ - sbc_init.o sg_init.o pll_init.o clkrst_init.o pinctrl.o -obj-$(CONFIG_SPL_BUILD) += pll_spectrum.o \ - umc_init.o +obj-$(CONFIG_SOC_INIT) += bcu_init.o sbc_init.o sg_init.o pll_init.o \ + clkrst_init.o +obj-$(CONFIG_BOARD_POSTCLK_INIT) += pinctrl.o +obj-$(CONFIG_DRAM_INIT) += pll_spectrum.o umc_init.o diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/platdevice.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/platdevice.c index 0047223181..62f5b0148d 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/platdevice.c +++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/platdevice.c @@ -13,3 +13,16 @@ SERIAL_DEVICE(0, 0x54006800, UART_MASTER_CLK) SERIAL_DEVICE(1, 0x54006900, UART_MASTER_CLK) SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK) SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK) + +/* USB : TODO for Masahiro Yamada: move base address to Device Tree */ +struct uniphier_ehci_platform_data uniphier_ehci_platdata[] = { + { + .base = 0x5a800100, + }, + { + .base = 0x5a810100, + }, + { + .base = 0x5a820100, + }, +}; diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.c index 1344ac1caa..ebcbaabf65 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.c +++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.c @@ -149,10 +149,6 @@ int umc_init(void) CONFIG_SDRAM1_SIZE / 0x08000000); } -#if CONFIG_DDR_FREQ != 1333 && CONFIG_DDR_FREQ != 1600 -#error Unsupported DDR Frequency. -#endif - #if (CONFIG_SDRAM0_SIZE == 0x08000000 || CONFIG_SDRAM0_SIZE == 0x10000000) && \ (CONFIG_SDRAM1_SIZE == 0x08000000 || CONFIG_SDRAM1_SIZE == 0x10000000) && \ CONFIG_DDR_NUM_CH0 == 1 && CONFIG_DDR_NUM_CH1 == 1 diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile b/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile index e11f4f6d8b..74129bc86a 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile +++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile @@ -5,7 +5,6 @@ obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o obj-y += platdevice.o obj-y += boot-mode.o -obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o sbc_init.o \ - sg_init.o pll_init.o clkrst_init.o pinctrl.o -obj-$(CONFIG_SPL_BUILD) += pll_spectrum.o \ - umc_init.o +obj-$(CONFIG_SOC_INIT) += sbc_init.o sg_init.o pll_init.o clkrst_init.o +obj-$(CONFIG_BOARD_POSTCLK_INIT) += pinctrl.o +obj-$(CONFIG_DRAM_INIT) += pll_spectrum.o umc_init.o diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/board_postclk_init.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/board_postclk_init.c deleted file mode 100644 index 7198829988..0000000000 --- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/board_postclk_init.c +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (C) 2012-2014 Panasonic Corporation - * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/arch/led.h> -#include <asm/arch/board.h> - -void sbc_init(void); -void sg_init(void); -void pll_init(void); -void pin_init(void); -void clkrst_init(void); - -int board_postclk_init(void) -{ - sbc_init(); - - sg_init(); - - pll_init(); - - uniphier_board_init(); - - led_write(B, 1, , ); - - clkrst_init(); - - led_write(B, 2, , ); - - pin_init(); - - led_write(B, 3, , ); - - return 0; -} diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/pinctrl.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/pinctrl.c index 503c247d6b..4e3d47615b 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/pinctrl.c +++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/pinctrl.c @@ -41,5 +41,12 @@ void pin_init(void) sg_set_pinsel(54, 0); /* NRYBY0 -> NRYBY0 */ #endif +#ifdef CONFIG_USB_EHCI_UNIPHIER + sg_set_pinsel(184, 0); /* USB2VBUS -> USB2VBUS */ + sg_set_pinsel(185, 0); /* USB2OD -> USB2OD */ + sg_set_pinsel(187, 0); /* USB3VBUS -> USB3VBUS */ + sg_set_pinsel(188, 0); /* USB3OD -> USB3OD */ +#endif + writel(1, SG_LOADPINCTRL); } diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/platdevice.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/platdevice.c index 6da921e920..1843d0469f 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/platdevice.c +++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/platdevice.c @@ -13,3 +13,13 @@ SERIAL_DEVICE(0, 0x54006800, UART_MASTER_CLK) SERIAL_DEVICE(1, 0x54006900, UART_MASTER_CLK) SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK) SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK) + +/* USB : TODO for Masahiro Yamada: move base address to Device Tree */ +struct uniphier_ehci_platform_data uniphier_ehci_platdata[] = { + { + .base = 0x5a800100, + }, + { + .base = 0x5a810100, + }, +}; diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c index dd462875bb..328b2f4d9a 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c +++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c @@ -122,10 +122,6 @@ int umc_init(void) CONFIG_SDRAM1_SIZE / 0x08000000); } -#if CONFIG_DDR_FREQ != 1600 -#error Unsupported DDR frequency. -#endif - #if ((CONFIG_SDRAM0_SIZE == 0x20000000 && CONFIG_DDR_NUM_CH0 == 2) || \ (CONFIG_SDRAM0_SIZE == 0x10000000 && CONFIG_DDR_NUM_CH0 == 1)) && \ ((CONFIG_SDRAM1_SIZE == 0x20000000 && CONFIG_DDR_NUM_CH1 == 2) || \ diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile b/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile index 781b511a97..fba1cc7498 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile +++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile @@ -5,7 +5,7 @@ obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o obj-y += platdevice.o obj-y += boot-mode.o -obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o bcu_init.o \ - sbc_init.o sg_init.o pll_init.o clkrst_init.o pinctrl.o -obj-$(CONFIG_SPL_BUILD) += pll_spectrum.o \ - umc_init.o +obj-$(CONFIG_SOC_INIT) += bcu_init.o sbc_init.o sg_init.o pll_init.o \ + clkrst_init.o +obj-$(CONFIG_BOARD_POSTCLK_INIT) += pinctrl.o +obj-$(CONFIG_DRAM_INIT) += pll_spectrum.o umc_init.o diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/board_postclk_init.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/board_postclk_init.c deleted file mode 100644 index 287b33c21d..0000000000 --- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/board_postclk_init.c +++ /dev/null @@ -1 +0,0 @@ -#include "../ph1-ld4/board_postclk_init.c" diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/platdevice.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/platdevice.c index 59d054a310..72ec599f69 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/platdevice.c +++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/platdevice.c @@ -13,3 +13,16 @@ SERIAL_DEVICE(0, 0x54006800, UART_MASTER_CLK) SERIAL_DEVICE(1, 0x54006900, UART_MASTER_CLK) SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK) SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK) + +/* USB : TODO for Masahiro Yamada: move base address to Device Tree */ +struct uniphier_ehci_platform_data uniphier_ehci_platdata[] = { + { + .base = 0x5a800100, + }, + { + .base = 0x5a810100, + }, + { + .base = 0x5a820100, + }, +}; diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/umc_init.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/umc_init.c index ff2dcb1640..a44f999fbf 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/umc_init.c +++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/umc_init.c @@ -129,10 +129,6 @@ int umc_init(void) CONFIG_SDRAM1_SIZE / 0x08000000); } -#if CONFIG_DDR_FREQ != 1333 -#error Unsupported DDR frequency. -#endif - #if (CONFIG_SDRAM0_SIZE == 0x08000000 || CONFIG_SDRAM0_SIZE == 0x10000000) && \ (CONFIG_SDRAM1_SIZE == 0x08000000 || CONFIG_SDRAM1_SIZE == 0x10000000) && \ CONFIG_DDR_NUM_CH0 == 1 && CONFIG_DDR_NUM_CH1 == 1 diff --git a/arch/arm/cpu/armv7/uniphier/reset.c b/arch/arm/cpu/armv7/uniphier/reset.c index b0dc9673b4..50d1fed647 100644 --- a/arch/arm/cpu/armv7/uniphier/reset.c +++ b/arch/arm/cpu/armv7/uniphier/reset.c @@ -8,14 +8,11 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/sc-regs.h> -#include <asm/arch/board.h> void reset_cpu(unsigned long ignored) { u32 tmp; - uniphier_board_reset(); - writel(5, SC_IRQTIMSET); /* default value */ tmp = readl(SC_SLFRSTSEL); diff --git a/arch/arm/cpu/armv7/zynq/Kconfig b/arch/arm/cpu/armv7/zynq/Kconfig index f418cd6d99..3a52535ce0 100644 --- a/arch/arm/cpu/armv7/zynq/Kconfig +++ b/arch/arm/cpu/armv7/zynq/Kconfig @@ -15,6 +15,9 @@ config TARGET_ZYNQ_ZC70X config TARGET_ZYNQ_ZC770 bool "Zynq ZC770 Board" +config TARGET_ZYNQ_ZYBO + bool "Zynq Zybo Board" + endchoice config SYS_BOARD @@ -31,5 +34,6 @@ config SYS_CONFIG_NAME default "zynq_microzed" if TARGET_ZYNQ_MICROZED default "zynq_zc70x" if TARGET_ZYNQ_ZC70X default "zynq_zc770" if TARGET_ZYNQ_ZC770 + default "zynq_zybo" if TARGET_ZYNQ_ZYBO endif diff --git a/arch/arm/cpu/armv7/zynq/ddrc.c b/arch/arm/cpu/armv7/zynq/ddrc.c index 1ea086d520..d74f8dbbc4 100644 --- a/arch/arm/cpu/armv7/zynq/ddrc.c +++ b/arch/arm/cpu/armv7/zynq/ddrc.c @@ -40,6 +40,7 @@ void zynq_ddrc_init(void) * first stage bootloader. To get ECC to work all memory has * been initialized by writing any value. */ + /* cppcheck-suppress nullPointer */ memset((void *)0, 0, 1 * 1024 * 1024); } else { puts("ECC disabled "); |