diff options
Diffstat (limited to 'arch/arm/cpu/armv7')
| -rw-r--r-- | arch/arm/cpu/armv7/Makefile | 2 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/lowlevel_init.S | 10 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/sunxi/psci.c | 25 |
3 files changed, 27 insertions, 10 deletions
diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index 5fac252c0e..45dd3caec6 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -12,11 +12,9 @@ obj-y += cache_v7.o cache_v7_asm.o obj-y += cpu.o cp15.o obj-y += syslib.o -ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_MX7)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_ARCH_SUNXI)$(CONFIG_ARCH_SOCFPGA)$(CONFIG_ARCH_MX7ULP)$(CONFIG_ARCH_LS1021A),) ifneq ($(CONFIG_SKIP_LOWLEVEL_INIT),y) obj-y += lowlevel_init.o endif -endif obj-$(CONFIG_ARM_SMCCC) += smccc-call.o obj-$(CONFIG_ARMV7_NONSEC) += nonsec_virt.o virt-v7.o virt-dt.o diff --git a/arch/arm/cpu/armv7/lowlevel_init.S b/arch/arm/cpu/armv7/lowlevel_init.S index 658934d664..64f105864f 100644 --- a/arch/arm/cpu/armv7/lowlevel_init.S +++ b/arch/arm/cpu/armv7/lowlevel_init.S @@ -15,7 +15,14 @@ #include <config.h> #include <linux/linkage.h> -ENTRY(lowlevel_init) +.pushsection .text.s_init, "ax" +WEAK(s_init) + bx lr +ENDPROC(s_init) +.popsection + +.pushsection .text.lowlevel_init, "ax" +WEAK(lowlevel_init) /* * Setup a temporary stack. Global data is not available yet. */ @@ -61,3 +68,4 @@ ENTRY(lowlevel_init) bl s_init pop {ip, pc} ENDPROC(lowlevel_init) +.popsection diff --git a/arch/arm/cpu/armv7/sunxi/psci.c b/arch/arm/cpu/armv7/sunxi/psci.c index b3a34de1aa..18da9cb864 100644 --- a/arch/arm/cpu/armv7/sunxi/psci.c +++ b/arch/arm/cpu/armv7/sunxi/psci.c @@ -118,6 +118,23 @@ static void __secure sunxi_power_switch(u32 *clamp, u32 *pwroff, bool on, } } +#ifdef CONFIG_MACH_SUN8I_R40 +/* secondary core entry address is programmed differently on R40 */ +static void __secure sunxi_set_entry_address(void *entry) +{ + writel((u32)entry, + SUNXI_SRAMC_BASE + SUN8I_R40_SRAMC_SOFT_ENTRY_REG0); +} +#else +static void __secure sunxi_set_entry_address(void *entry) +{ + struct sunxi_cpucfg_reg *cpucfg = + (struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE; + + writel((u32)entry, &cpucfg->priv0); +} +#endif + #ifdef CONFIG_MACH_SUN7I /* sun7i (A20) is different from other single cluster SoCs */ static void __secure sunxi_cpu_set_power(int __always_unused cpu, bool on) @@ -236,13 +253,7 @@ int __secure psci_cpu_on(u32 __always_unused unused, u32 mpidr, u32 pc) psci_save_target_pc(cpu, pc); /* Set secondary core power on PC */ -#ifdef CONFIG_MACH_SUN8I_R40 - /* secondary core entry address is programmed differently */ - writel((u32)&psci_cpu_entry, - SUNXI_SRAMC_BASE + SUN8I_R40_SRAMC_SOFT_ENTRY_REG0); -#else - writel((u32)&psci_cpu_entry, &cpucfg->priv0); -#endif + sunxi_set_entry_address(&psci_cpu_entry); /* Assert reset on target CPU */ writel(0, &cpucfg->cpu[cpu].rst); |