diff options
Diffstat (limited to 'arch/arm/cpu/armv7')
| -rw-r--r-- | arch/arm/cpu/armv7/sunxi/board.c | 4 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/sunxi/dram_sun4i.c | 4 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/sunxi/dram_sun8i_a23.c | 19 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/sunxi/dram_sun8i_a33.c | 6 |
4 files changed, 18 insertions, 15 deletions
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c index 6718ae2205..e6730c0dfa 100644 --- a/arch/arm/cpu/armv7/sunxi/board.c +++ b/arch/arm/cpu/armv7/sunxi/board.c @@ -68,6 +68,10 @@ static int gpio_init(void) sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1); sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1); sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP); +#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I) + sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2); + sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2); + sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP); #elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I) sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART); sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART); diff --git a/arch/arm/cpu/armv7/sunxi/dram_sun4i.c b/arch/arm/cpu/armv7/sunxi/dram_sun4i.c index c736fa3b47..f7b4915037 100644 --- a/arch/arm/cpu/armv7/sunxi/dram_sun4i.c +++ b/arch/arm/cpu/armv7/sunxi/dram_sun4i.c @@ -508,7 +508,7 @@ static void mctl_ddr3_initialize(void) /* * Perform impedance calibration on the DRAM controller side of the wire. */ -static void mctl_set_impedance(u32 zq, u32 odt_en) +static void mctl_set_impedance(u32 zq, bool odt_en) { struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; u32 reg_val; @@ -556,7 +556,7 @@ static void mctl_set_impedance(u32 zq, u32 odt_en) clrbits_le32(&dram->zqcr0, DRAM_ZQCR0_ZCAL); /* Set I/O configure register */ - writel(DRAM_IOCR_ODT_EN(odt_en), &dram->iocr); + writel(DRAM_IOCR_ODT_EN, &dram->iocr); } static unsigned long dramc_init_helper(struct dram_para *para) diff --git a/arch/arm/cpu/armv7/sunxi/dram_sun8i_a23.c b/arch/arm/cpu/armv7/sunxi/dram_sun8i_a23.c index 3d7964d1af..165c052122 100644 --- a/arch/arm/cpu/armv7/sunxi/dram_sun8i_a23.c +++ b/arch/arm/cpu/armv7/sunxi/dram_sun8i_a23.c @@ -26,12 +26,14 @@ #include <asm/arch/clock.h> #include <asm/arch/dram.h> #include <asm/arch/prcm.h> +#include <linux/kconfig.h> static const struct dram_para dram_para = { .clock = CONFIG_DRAM_CLK, .type = 3, .zq = CONFIG_DRAM_ZQ, - .odt_en = 1, + .odt_en = IS_ENABLED(CONFIG_DRAM_ODT_EN), + .odt_correction = CONFIG_DRAM_ODT_CORRECTION, .para1 = 0, /* not used (only used when tpr13 bit 31 is set */ .para2 = 0, /* not used (only used when tpr13 bit 31 is set */ .mr0 = 6736, @@ -97,7 +99,6 @@ static void mctl_init(u32 *bus_width) (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; struct sunxi_mctl_phy_reg * const mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE; - int correction; if (dram_para.tpr13 & 0x20) writel(0x40b, &mctl_phy->dcr); @@ -138,7 +139,7 @@ static void mctl_init(u32 *bus_width) writel(0x01000081, &mctl_phy->dtcr); - if (dram_para.clock <= 240 || !(dram_para.odt_en & 0x01)) { + if (dram_para.clock <= 240 || !dram_para.odt_en) { clrbits_le32(&mctl_phy->dx0gcr, 0x600); clrbits_le32(&mctl_phy->dx1gcr, 0x600); } @@ -251,13 +252,11 @@ static void mctl_init(u32 *bus_width) } else *bus_width = 16; - correction = (dram_para.odt_en >> 8) & 0xff; - if (correction) { - if (dram_para.odt_en & 0x80000000) - correction = -correction; - - mctl_apply_odt_correction(&mctl_phy->dx0lcdlr1, correction); - mctl_apply_odt_correction(&mctl_phy->dx1lcdlr1, correction); + if (dram_para.odt_correction) { + mctl_apply_odt_correction(&mctl_phy->dx0lcdlr1, + dram_para.odt_correction); + mctl_apply_odt_correction(&mctl_phy->dx1lcdlr1, + dram_para.odt_correction); } mctl_await_completion(&mctl_ctl->statr, 0x01, 0x01); diff --git a/arch/arm/cpu/armv7/sunxi/dram_sun8i_a33.c b/arch/arm/cpu/armv7/sunxi/dram_sun8i_a33.c index d03f00dc4b..ebba438319 100644 --- a/arch/arm/cpu/armv7/sunxi/dram_sun8i_a33.c +++ b/arch/arm/cpu/armv7/sunxi/dram_sun8i_a33.c @@ -14,12 +14,12 @@ #include <asm/arch/clock.h> #include <asm/arch/dram.h> #include <asm/arch/prcm.h> +#include <linux/kconfig.h> /* PLL runs at 2x dram-clk, controller runs at PLL / 4 (dram-clk / 2) */ #define DRAM_CLK_MUL 2 #define DRAM_CLK_DIV 4 #define DRAM_SIGMA_DELTA_ENABLE 1 -#define DRAM_ODT_EN 0 struct dram_para { u8 cs1; @@ -195,7 +195,7 @@ static int mctl_train_dram(struct dram_para *para) (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; mctl_data_train_cfg(para); - mctl_set_pir(0x1f3); + mctl_set_pir(0x5f3); return ((readl(&mctl_ctl->pgsr0) >> 20) & 0xff) ? -EIO : 0; } @@ -215,7 +215,7 @@ static int mctl_channel_init(struct dram_para *para) clrbits_le32(&mctl_ctl->pgcr0, 0x3f << 0); /* Set ODT */ - if ((CONFIG_DRAM_CLK > 400) && DRAM_ODT_EN) { + if ((CONFIG_DRAM_CLK > 400) && IS_ENABLED(CONFIG_DRAM_ODT_EN)) { setbits_le32(DXnGCR0(0), 0x3 << 9); setbits_le32(DXnGCR0(1), 0x3 << 9); } else { |