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-rw-r--r--arch/arm/cpu/armv7/exynos/clock.c84
-rw-r--r--arch/arm/cpu/armv7/exynos/pinmux.c7
-rw-r--r--arch/arm/cpu/armv7/omap-common/boot-common.c13
-rw-r--r--arch/arm/cpu/armv7/tegra124/Makefile6
-rw-r--r--arch/arm/cpu/armv7/tegra124/config.mk10
-rw-r--r--arch/arm/cpu/armv7/zynq/Makefile2
-rw-r--r--arch/arm/cpu/armv7/zynq/clk.c664
-rw-r--r--arch/arm/cpu/armv7/zynq/cpu.c14
-rw-r--r--arch/arm/cpu/armv7/zynq/slcr.c17
-rw-r--r--arch/arm/cpu/armv7/zynq/spl.c69
-rw-r--r--arch/arm/cpu/armv7/zynq/timer.c14
-rw-r--r--arch/arm/cpu/armv7/zynq/u-boot-spl.lds61
-rw-r--r--arch/arm/cpu/armv7/zynq/u-boot.lds99
13 files changed, 976 insertions, 84 deletions
diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
index 5bde9d180b..1fea4d6663 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -26,7 +26,7 @@ struct clk_bit_info {
};
/* src_bit div_bit prediv_bit */
-static struct clk_bit_info clk_bit_info[PERIPH_ID_COUNT] = {
+static struct clk_bit_info clk_bit_info[] = {
{0, 0, -1},
{4, 4, -1},
{8, 8, -1},
@@ -870,7 +870,6 @@ static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
struct exynos4_clock *clk =
(struct exynos4_clock *)samsung_get_base_clock();
unsigned int addr;
- unsigned int val;
/*
* CLK_DIV_FSYS1
@@ -890,10 +889,8 @@ static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
dev_index -= 2;
}
- val = readl(addr);
- val &= ~(0xff << ((dev_index << 4) + 8));
- val |= (div & 0xff) << ((dev_index << 4) + 8);
- writel(val, addr);
+ clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8),
+ (div & 0xff) << ((dev_index << 4) + 8));
}
/* exynos4x12: set the mmc clock */
@@ -902,7 +899,6 @@ static void exynos4x12_set_mmc_clk(int dev_index, unsigned int div)
struct exynos4x12_clock *clk =
(struct exynos4x12_clock *)samsung_get_base_clock();
unsigned int addr;
- unsigned int val;
/*
* CLK_DIV_FSYS1
@@ -917,10 +913,8 @@ static void exynos4x12_set_mmc_clk(int dev_index, unsigned int div)
dev_index -= 2;
}
- val = readl(addr);
- val &= ~(0xff << ((dev_index << 4) + 8));
- val |= (div & 0xff) << ((dev_index << 4) + 8);
- writel(val, addr);
+ clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8),
+ (div & 0xff) << ((dev_index << 4) + 8));
}
/* exynos5: set the mmc clock */
@@ -929,7 +923,6 @@ static void exynos5_set_mmc_clk(int dev_index, unsigned int div)
struct exynos5_clock *clk =
(struct exynos5_clock *)samsung_get_base_clock();
unsigned int addr;
- unsigned int val;
/*
* CLK_DIV_FSYS1
@@ -944,10 +937,8 @@ static void exynos5_set_mmc_clk(int dev_index, unsigned int div)
dev_index -= 2;
}
- val = readl(addr);
- val &= ~(0xff << ((dev_index << 4) + 8));
- val |= (div & 0xff) << ((dev_index << 4) + 8);
- writel(val, addr);
+ clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8),
+ (div & 0xff) << ((dev_index << 4) + 8));
}
/* exynos5: set the mmc clock */
@@ -956,7 +947,7 @@ static void exynos5420_set_mmc_clk(int dev_index, unsigned int div)
struct exynos5420_clock *clk =
(struct exynos5420_clock *)samsung_get_base_clock();
unsigned int addr;
- unsigned int val, shift;
+ unsigned int shift;
/*
* CLK_DIV_FSYS1
@@ -967,10 +958,7 @@ static void exynos5420_set_mmc_clk(int dev_index, unsigned int div)
addr = (unsigned int)&clk->div_fsys1;
shift = dev_index * 10;
- val = readl(addr);
- val &= ~(0x3ff << shift);
- val |= (div & 0x3ff) << shift;
- writel(val, addr);
+ clrsetbits_le32(addr, 0x3ff << shift, (div & 0x3ff) << shift);
}
/* get_lcd_clk: return lcd clock frequency */
@@ -1061,7 +1049,6 @@ void exynos4_set_lcd_clk(void)
{
struct exynos4_clock *clk =
(struct exynos4_clock *)samsung_get_base_clock();
- unsigned int cfg = 0;
/*
* CLK_GATE_BLOCK
@@ -1073,9 +1060,7 @@ void exynos4_set_lcd_clk(void)
* CLK_LCD1 [5]
* CLK_GPS [7]
*/
- cfg = readl(&clk->gate_block);
- cfg |= 1 << 4;
- writel(cfg, &clk->gate_block);
+ setbits_le32(&clk->gate_block, 1 << 4);
/*
* CLK_SRC_LCD0
@@ -1085,10 +1070,7 @@ void exynos4_set_lcd_clk(void)
* MIPI0_SEL [12:15]
* set lcd0 src clock 0x6: SCLK_MPLL
*/
- cfg = readl(&clk->src_lcd0);
- cfg &= ~(0xf);
- cfg |= 0x6;
- writel(cfg, &clk->src_lcd0);
+ clrsetbits_le32(&clk->src_lcd0, 0xf, 0x6);
/*
* CLK_GATE_IP_LCD0
@@ -1100,9 +1082,7 @@ void exynos4_set_lcd_clk(void)
* CLK_PPMULCD0 [5]
* Gating all clocks for FIMD0
*/
- cfg = readl(&clk->gate_ip_lcd0);
- cfg |= 1 << 0;
- writel(cfg, &clk->gate_ip_lcd0);
+ setbits_le32(&clk->gate_ip_lcd0, 1 << 0);
/*
* CLK_DIV_LCD0
@@ -1114,16 +1094,13 @@ void exynos4_set_lcd_clk(void)
* MIPI0_PRE_RATIO [23:20]
* set fimd ratio
*/
- cfg &= ~(0xf);
- cfg |= 0x1;
- writel(cfg, &clk->div_lcd0);
+ clrsetbits_le32(&clk->div_lcd0, 0xf, 0x1);
}
void exynos5_set_lcd_clk(void)
{
struct exynos5_clock *clk =
(struct exynos5_clock *)samsung_get_base_clock();
- unsigned int cfg = 0;
/*
* CLK_GATE_BLOCK
@@ -1135,9 +1112,7 @@ void exynos5_set_lcd_clk(void)
* CLK_LCD1 [5]
* CLK_GPS [7]
*/
- cfg = readl(&clk->gate_block);
- cfg |= 1 << 4;
- writel(cfg, &clk->gate_block);
+ setbits_le32(&clk->gate_block, 1 << 4);
/*
* CLK_SRC_LCD0
@@ -1147,10 +1122,7 @@ void exynos5_set_lcd_clk(void)
* MIPI0_SEL [12:15]
* set lcd0 src clock 0x6: SCLK_MPLL
*/
- cfg = readl(&clk->src_disp1_0);
- cfg &= ~(0xf);
- cfg |= 0x6;
- writel(cfg, &clk->src_disp1_0);
+ clrsetbits_le32(&clk->src_disp1_0, 0xf, 0x6);
/*
* CLK_GATE_IP_LCD0
@@ -1162,9 +1134,7 @@ void exynos5_set_lcd_clk(void)
* CLK_PPMULCD0 [5]
* Gating all clocks for FIMD0
*/
- cfg = readl(&clk->gate_ip_disp1);
- cfg |= 1 << 0;
- writel(cfg, &clk->gate_ip_disp1);
+ setbits_le32(&clk->gate_ip_disp1, 1 << 0);
/*
* CLK_DIV_LCD0
@@ -1176,16 +1146,13 @@ void exynos5_set_lcd_clk(void)
* MIPI0_PRE_RATIO [23:20]
* set fimd ratio
*/
- cfg &= ~(0xf);
- cfg |= 0x0;
- writel(cfg, &clk->div_disp1_0);
+ clrsetbits_le32(&clk->div_disp1_0, 0xf, 0x0);
}
void exynos4_set_mipi_clk(void)
{
struct exynos4_clock *clk =
(struct exynos4_clock *)samsung_get_base_clock();
- unsigned int cfg = 0;
/*
* CLK_SRC_LCD0
@@ -1195,10 +1162,7 @@ void exynos4_set_mipi_clk(void)
* MIPI0_SEL [12:15]
* set mipi0 src clock 0x6: SCLK_MPLL
*/
- cfg = readl(&clk->src_lcd0);
- cfg &= ~(0xf << 12);
- cfg |= (0x6 << 12);
- writel(cfg, &clk->src_lcd0);
+ clrsetbits_le32(&clk->src_lcd0, 0xf << 12, 0x6 << 12);
/*
* CLK_SRC_MASK_LCD0
@@ -1208,9 +1172,7 @@ void exynos4_set_mipi_clk(void)
* MIPI0_MASK [12]
* set src mask mipi0 0x1: Unmask
*/
- cfg = readl(&clk->src_mask_lcd0);
- cfg |= (0x1 << 12);
- writel(cfg, &clk->src_mask_lcd0);
+ setbits_le32(&clk->src_mask_lcd0, 0x1 << 12);
/*
* CLK_GATE_IP_LCD0
@@ -1222,9 +1184,7 @@ void exynos4_set_mipi_clk(void)
* CLK_PPMULCD0 [5]
* Gating all clocks for MIPI0
*/
- cfg = readl(&clk->gate_ip_lcd0);
- cfg |= 1 << 3;
- writel(cfg, &clk->gate_ip_lcd0);
+ setbits_le32(&clk->gate_ip_lcd0, 1 << 3);
/*
* CLK_DIV_LCD0
@@ -1236,9 +1196,7 @@ void exynos4_set_mipi_clk(void)
* MIPI0_PRE_RATIO [23:20]
* set mipi ratio
*/
- cfg &= ~(0xf << 16);
- cfg |= (0x1 << 16);
- writel(cfg, &clk->div_lcd0);
+ clrsetbits_le32(&clk->div_lcd0, 0xf << 16, 0x1 << 16);
}
/*
diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c
index 904177a149..645c497370 100644
--- a/arch/arm/cpu/armv7/exynos/pinmux.c
+++ b/arch/arm/cpu/armv7/exynos/pinmux.c
@@ -751,12 +751,7 @@ static int exynos5_pinmux_decode_periph_id(const void *blob, int node)
if (err)
return PERIPH_ID_NONE;
- /* check for invalid peripheral id */
- if ((PERIPH_ID_SDMMC4 > cell[1]) || (cell[1] < PERIPH_ID_UART0))
- return cell[1];
-
- debug(" invalid peripheral id\n");
- return PERIPH_ID_NONE;
+ return cell[1];
}
int pinmux_decode_periph_id(const void *blob, int node)
diff --git a/arch/arm/cpu/armv7/omap-common/boot-common.c b/arch/arm/cpu/armv7/omap-common/boot-common.c
index 69fff323d3..52e0f4a6cf 100644
--- a/arch/arm/cpu/armv7/omap-common/boot-common.c
+++ b/arch/arm/cpu/armv7/omap-common/boot-common.c
@@ -66,7 +66,18 @@ u32 spl_boot_device(void)
u32 spl_boot_mode(void)
{
- return gd->arch.omap_boot_params.omap_bootmode;
+ u32 val = gd->arch.omap_boot_params.omap_bootmode;
+
+ if (val == MMCSD_MODE_RAW)
+ return MMCSD_MODE_RAW;
+ else if (val == MMCSD_MODE_FAT)
+ return MMCSD_MODE_FAT;
+ else
+#ifdef CONFIG_SUPPORT_EMMC_BOOT
+ return MMCSD_MODE_EMMCBOOT;
+#else
+ return MMCSD_MODE_UNDEFINED;
+#endif
}
void spl_board_init(void)
diff --git a/arch/arm/cpu/armv7/tegra124/Makefile b/arch/arm/cpu/armv7/tegra124/Makefile
new file mode 100644
index 0000000000..7f127b1ee5
--- /dev/null
+++ b/arch/arm/cpu/armv7/tegra124/Makefile
@@ -0,0 +1,6 @@
+#
+# (C) Copyright 2013-2014
+# NVIDIA Corporation <www.nvidia.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
diff --git a/arch/arm/cpu/armv7/tegra124/config.mk b/arch/arm/cpu/armv7/tegra124/config.mk
new file mode 100644
index 0000000000..2f1c645c69
--- /dev/null
+++ b/arch/arm/cpu/armv7/tegra124/config.mk
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2013
+# NVIDIA Corporation <www.nvidia.com>
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+CONFIG_ARCH_DEVICE_TREE := tegra124
diff --git a/arch/arm/cpu/armv7/zynq/Makefile b/arch/arm/cpu/armv7/zynq/Makefile
index d382d49eb0..3363a3c71b 100644
--- a/arch/arm/cpu/armv7/zynq/Makefile
+++ b/arch/arm/cpu/armv7/zynq/Makefile
@@ -12,3 +12,5 @@ obj-y := timer.o
obj-y += cpu.o
obj-y += ddrc.o
obj-y += slcr.o
+obj-y += clk.o
+obj-$(CONFIG_SPL_BUILD) += spl.o
diff --git a/arch/arm/cpu/armv7/zynq/clk.c b/arch/arm/cpu/armv7/zynq/clk.c
new file mode 100644
index 0000000000..d2885dc2b9
--- /dev/null
+++ b/arch/arm/cpu/armv7/zynq/clk.c
@@ -0,0 +1,664 @@
+/*
+ * Copyright (C) 2013 Soren Brinkmann <soren.brinkmann@xilinx.com>
+ * Copyright (C) 2013 Xilinx, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <errno.h>
+#include <clk.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/clk.h>
+
+/* Board oscillator frequency */
+#ifndef CONFIG_ZYNQ_PS_CLK_FREQ
+# define CONFIG_ZYNQ_PS_CLK_FREQ 33333333UL
+#endif
+
+/* Register bitfield defines */
+#define PLLCTRL_FBDIV_MASK 0x7f000
+#define PLLCTRL_FBDIV_SHIFT 12
+#define PLLCTRL_BPFORCE_MASK (1 << 4)
+#define PLLCTRL_PWRDWN_MASK 2
+#define PLLCTRL_PWRDWN_SHIFT 1
+#define PLLCTRL_RESET_MASK 1
+#define PLLCTRL_RESET_SHIFT 0
+
+#define ZYNQ_CLK_MAXDIV 0x3f
+#define CLK_CTRL_DIV1_SHIFT 20
+#define CLK_CTRL_DIV1_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV1_SHIFT)
+#define CLK_CTRL_DIV0_SHIFT 8
+#define CLK_CTRL_DIV0_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV0_SHIFT)
+#define CLK_CTRL_SRCSEL_SHIFT 4
+#define CLK_CTRL_SRCSEL_MASK (0x3 << CLK_CTRL_SRCSEL_SHIFT)
+
+#define CLK_CTRL_DIV2X_SHIFT 26
+#define CLK_CTRL_DIV2X_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV2X_SHIFT)
+#define CLK_CTRL_DIV3X_SHIFT 20
+#define CLK_CTRL_DIV3X_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV3X_SHIFT)
+
+#define ZYNQ_CLKMUX_SEL_0 0
+#define ZYNQ_CLKMUX_SEL_1 1
+#define ZYNQ_CLKMUX_SEL_2 2
+#define ZYNQ_CLKMUX_SEL_3 3
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct clk;
+
+/**
+ * struct clk_ops:
+ * @set_rate: Function pointer to set_rate() implementation
+ * @get_rate: Function pointer to get_rate() implementation
+ */
+struct clk_ops {
+ int (*set_rate)(struct clk *clk, unsigned long rate);
+ unsigned long (*get_rate)(struct clk *clk);
+};
+
+/**
+ * struct clk:
+ * @name: Clock name
+ * @frequency: Currenct frequency
+ * @parent: Parent clock
+ * @flags: Clock flags
+ * @reg: Clock control register
+ * @ops: Clock operations
+ */
+struct clk {
+ char *name;
+ unsigned long frequency;
+ enum zynq_clk parent;
+ unsigned int flags;
+ u32 *reg;
+ struct clk_ops ops;
+};
+#define ZYNQ_CLK_FLAGS_HAS_2_DIVS 1
+
+static struct clk clks[clk_max];
+
+/**
+ * __zynq_clk_cpu_get_parent() - Decode clock multiplexer
+ * @srcsel: Mux select value
+ * Returns the clock identifier associated with the selected mux input.
+ */
+static int __zynq_clk_cpu_get_parent(unsigned int srcsel)
+{
+ unsigned int ret;
+
+ switch (srcsel) {
+ case ZYNQ_CLKMUX_SEL_0:
+ case ZYNQ_CLKMUX_SEL_1:
+ ret = armpll_clk;
+ break;
+ case ZYNQ_CLKMUX_SEL_2:
+ ret = ddrpll_clk;
+ break;
+ case ZYNQ_CLKMUX_SEL_3:
+ ret = iopll_clk;
+ break;
+ default:
+ ret = armpll_clk;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * ddr2x_get_rate() - Get clock rate of DDR2x clock
+ * @clk: Clock handle
+ * Returns the current clock rate of @clk.
+ */
+static unsigned long ddr2x_get_rate(struct clk *clk)
+{
+ u32 clk_ctrl = readl(clk->reg);
+ u32 div = (clk_ctrl & CLK_CTRL_DIV2X_MASK) >> CLK_CTRL_DIV2X_SHIFT;
+
+ return DIV_ROUND_CLOSEST(zynq_clk_get_rate(clk->parent), div);
+}
+
+/**
+ * ddr3x_get_rate() - Get clock rate of DDR3x clock
+ * @clk: Clock handle
+ * Returns the current clock rate of @clk.
+ */
+static unsigned long ddr3x_get_rate(struct clk *clk)
+{
+ u32 clk_ctrl = readl(clk->reg);
+ u32 div = (clk_ctrl & CLK_CTRL_DIV3X_MASK) >> CLK_CTRL_DIV3X_SHIFT;
+
+ return DIV_ROUND_CLOSEST(zynq_clk_get_rate(clk->parent), div);
+}
+
+static void init_ddr_clocks(void)
+{
+ u32 div0, div1;
+ unsigned long prate = zynq_clk_get_rate(ddrpll_clk);
+ u32 clk_ctrl = readl(&slcr_base->ddr_clk_ctrl);
+
+ /* DDR2x */
+ clks[ddr2x_clk].reg = &slcr_base->ddr_clk_ctrl;
+ clks[ddr2x_clk].parent = ddrpll_clk;
+ clks[ddr2x_clk].name = "ddr_2x";
+ clks[ddr2x_clk].frequency = ddr2x_get_rate(&clks[ddr2x_clk]);
+ clks[ddr2x_clk].ops.get_rate = ddr2x_get_rate;
+
+ /* DDR3x */
+ clks[ddr3x_clk].reg = &slcr_base->ddr_clk_ctrl;
+ clks[ddr3x_clk].parent = ddrpll_clk;
+ clks[ddr3x_clk].name = "ddr_3x";
+ clks[ddr3x_clk].frequency = ddr3x_get_rate(&clks[ddr3x_clk]);
+ clks[ddr3x_clk].ops.get_rate = ddr3x_get_rate;
+
+ /* DCI */
+ clk_ctrl = readl(&slcr_base->dci_clk_ctrl);
+ div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
+ div1 = (clk_ctrl & CLK_CTRL_DIV1_MASK) >> CLK_CTRL_DIV1_SHIFT;
+ clks[dci_clk].reg = &slcr_base->dci_clk_ctrl;
+ clks[dci_clk].parent = ddrpll_clk;
+ clks[dci_clk].frequency = DIV_ROUND_CLOSEST(
+ DIV_ROUND_CLOSEST(prate, div0), div1);
+ clks[dci_clk].name = "dci";
+
+ gd->bd->bi_ddr_freq = clks[ddr3x_clk].frequency / 1000000;
+}
+
+static void init_cpu_clocks(void)
+{
+ int clk_621;
+ u32 reg, div, srcsel;
+ enum zynq_clk parent;
+
+ reg = readl(&slcr_base->arm_clk_ctrl);
+ clk_621 = readl(&slcr_base->clk_621_true) & 1;
+ div = (reg & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
+ srcsel = (reg & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT;
+ parent = __zynq_clk_cpu_get_parent(srcsel);
+
+ /* cpu clocks */
+ clks[cpu_6or4x_clk].reg = &slcr_base->arm_clk_ctrl;
+ clks[cpu_6or4x_clk].parent = parent;
+ clks[cpu_6or4x_clk].frequency = DIV_ROUND_CLOSEST(
+ zynq_clk_get_rate(parent), div);
+ clks[cpu_6or4x_clk].name = "cpu_6or4x";
+
+ clks[cpu_3or2x_clk].reg = &slcr_base->arm_clk_ctrl;
+ clks[cpu_3or2x_clk].parent = cpu_6or4x_clk;
+ clks[cpu_3or2x_clk].frequency = zynq_clk_get_rate(cpu_6or4x_clk) / 2;
+ clks[cpu_3or2x_clk].name = "cpu_3or2x";
+
+ clks[cpu_2x_clk].reg = &slcr_base->arm_clk_ctrl;
+ clks[cpu_2x_clk].parent = cpu_6or4x_clk;
+ clks[cpu_2x_clk].frequency = zynq_clk_get_rate(cpu_6or4x_clk) /
+ (2 + clk_621);
+ clks[cpu_2x_clk].name = "cpu_2x";
+
+ clks[cpu_1x_clk].reg = &slcr_base->arm_clk_ctrl;
+ clks[cpu_1x_clk].parent = cpu_6or4x_clk;
+ clks[cpu_1x_clk].frequency = zynq_clk_get_rate(cpu_6or4x_clk) /
+ (4 + 2 * clk_621);
+ clks[cpu_1x_clk].name = "cpu_1x";
+}
+
+/**
+ * periph_calc_two_divs() - Calculate clock dividers
+ * @cur_rate: Current clock rate
+ * @tgt_rate: Target clock rate
+ * @prate: Parent clock rate
+ * @div0: First divider (output)
+ * @div1: Second divider (output)
+ * Returns the actual clock rate possible.
+ *
+ * Calculates clock dividers for clocks with two 6-bit dividers.
+ */
+static unsigned long periph_calc_two_divs(unsigned long cur_rate,
+ unsigned long tgt_rate, unsigned long prate, u32 *div0,
+ u32 *div1)
+{
+ long err, best_err = (long)(~0UL >> 1);
+ unsigned long rate, best_rate = 0;
+ u32 d0, d1;
+
+ for (d0 = 1; d0 <= ZYNQ_CLK_MAXDIV; d0++) {
+ for (d1 = 1; d1 <= ZYNQ_CLK_MAXDIV >> 1; d1++) {
+ rate = DIV_ROUND_CLOSEST(DIV_ROUND_CLOSEST(prate, d0),
+ d1);
+ err = abs(rate - tgt_rate);
+
+ if (err < best_err) {
+ *div0 = d0;
+ *div1 = d1;
+ best_err = err;
+ best_rate = rate;
+ }
+ }
+ }
+
+ return best_rate;
+}
+
+/**
+ * zynq_clk_periph_set_rate() - Set clock rate
+ * @clk: Handle of the peripheral clock
+ * @rate: New clock rate
+ * Sets the clock frequency of @clk to @rate. Returns zero on success.
+ */
+static int zynq_clk_periph_set_rate(struct clk *clk,
+ unsigned long rate)
+{
+ u32 ctrl, div0 = 0, div1 = 0;
+ unsigned long prate, new_rate, cur_rate = clk->frequency;
+
+ ctrl = readl(clk->reg);
+ prate = zynq_clk_get_rate(clk->parent);
+ ctrl &= ~CLK_CTRL_DIV0_MASK;
+
+ if (clk->flags & ZYNQ_CLK_FLAGS_HAS_2_DIVS) {
+ ctrl &= ~CLK_CTRL_DIV1_MASK;
+ new_rate = periph_calc_two_divs(cur_rate, rate, prate, &div0,
+ &div1);
+ ctrl |= div1 << CLK_CTRL_DIV1_SHIFT;
+ } else {
+ div0 = DIV_ROUND_CLOSEST(prate, rate);
+ div0 &= ZYNQ_CLK_MAXDIV;
+ new_rate = DIV_ROUND_CLOSEST(rate, div0);
+ }
+
+ /* write new divs to hardware */
+ ctrl |= div0 << CLK_CTRL_DIV0_SHIFT;
+ writel(ctrl, clk->reg);
+
+ /* update frequency in clk framework */
+ clk->frequency = new_rate;
+
+ return 0;
+}
+
+/**
+ * zynq_clk_periph_get_rate() - Get clock rate
+ * @clk: Handle of the peripheral clock
+ * Returns the current clock rate of @clk.
+ */
+static unsigned long zynq_clk_periph_get_rate(struct clk *clk)
+{
+ u32 clk_ctrl = readl(clk->reg);
+ u32 div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
+ u32 div1 = 1;
+
+ if (clk->flags & ZYNQ_CLK_FLAGS_HAS_2_DIVS)
+ div1 = (clk_ctrl & CLK_CTRL_DIV1_MASK) >> CLK_CTRL_DIV1_SHIFT;
+
+ /* a register value of zero == division by 1 */
+ if (!div0)
+ div0 = 1;
+ if (!div1)
+ div1 = 1;
+
+ return
+ DIV_ROUND_CLOSEST(
+ DIV_ROUND_CLOSEST(zynq_clk_get_rate(clk->parent), div0),
+ div1);
+}
+
+/**
+ * __zynq_clk_periph_get_parent() - Decode clock multiplexer
+ * @srcsel: Mux select value
+ * Returns the clock identifier associated with the selected mux input.
+ */
+static enum zynq_clk __zynq_clk_periph_get_parent(u32 srcsel)
+{
+ switch (srcsel) {
+ case ZYNQ_CLKMUX_SEL_0:
+ case ZYNQ_CLKMUX_SEL_1:
+ return iopll_clk;
+ case ZYNQ_CLKMUX_SEL_2:
+ return armpll_clk;
+ case ZYNQ_CLKMUX_SEL_3:
+ return ddrpll_clk;
+ default:
+ return 0;
+ }
+}
+
+/**
+ * zynq_clk_periph_get_parent() - Decode clock multiplexer
+ * @clk: Clock handle
+ * Returns the clock identifier associated with the selected mux input.
+ */
+static enum zynq_clk zynq_clk_periph_get_parent(struct clk *clk)
+{
+ u32 clk_ctrl = readl(clk->reg);
+ u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT;
+
+ return __zynq_clk_periph_get_parent(srcsel);
+}
+
+/**
+ * zynq_clk_register_periph_clk() - Set up a peripheral clock with the framework
+ * @clk: Pointer to struct clk for the clock
+ * @ctrl: Clock control register
+ * @name: PLL name
+ * @two_divs: Indicates whether the clock features one or two dividers
+ */
+static int zynq_clk_register_periph_clk(struct clk *clk, u32 *ctrl, char *name,
+ bool two_divs)
+{
+ clk->name = name;
+ clk->reg = ctrl;
+ if (two_divs)
+ clk->flags = ZYNQ_CLK_FLAGS_HAS_2_DIVS;
+ clk->parent = zynq_clk_periph_get_parent(clk);
+ clk->frequency = zynq_clk_periph_get_rate(clk);
+ clk->ops.get_rate = zynq_clk_periph_get_rate;
+ clk->ops.set_rate = zynq_clk_periph_set_rate;
+
+ return 0;
+}
+
+static void init_periph_clocks(void)
+{
+ zynq_clk_register_periph_clk(&clks[gem0_clk], &slcr_base->gem0_clk_ctrl,
+ "gem0", 1);
+ zynq_clk_register_periph_clk(&clks[gem1_clk], &slcr_base->gem1_clk_ctrl,
+ "gem1", 1);
+
+ zynq_clk_register_periph_clk(&clks[smc_clk], &slcr_base->smc_clk_ctrl,
+ "smc", 0);
+
+ zynq_clk_register_periph_clk(&clks[lqspi_clk],
+ &slcr_base->lqspi_clk_ctrl, "lqspi", 0);
+
+ zynq_clk_register_periph_clk(&clks[sdio0_clk],
+ &slcr_base->sdio_clk_ctrl, "sdio0", 0);
+ zynq_clk_register_periph_clk(&clks[sdio1_clk],
+ &slcr_base->sdio_clk_ctrl, "sdio1", 0);
+
+ zynq_clk_register_periph_clk(&clks[spi0_clk], &slcr_base->spi_clk_ctrl,
+ "spi0", 0);
+ zynq_clk_register_periph_clk(&clks[spi1_clk], &slcr_base->spi_clk_ctrl,
+ "spi1", 0);
+
+ zynq_clk_register_periph_clk(&clks[uart0_clk],
+ &slcr_base->uart_clk_ctrl, "uart0", 0);
+ zynq_clk_register_periph_clk(&clks[uart1_clk],
+ &slcr_base->uart_clk_ctrl, "uart1", 0);
+
+ zynq_clk_register_periph_clk(&clks[dbg_trc_clk],
+ &slcr_base->dbg_clk_ctrl, "dbg_trc", 0);
+ zynq_clk_register_periph_clk(&clks[dbg_apb_clk],
+ &slcr_base->dbg_clk_ctrl, "dbg_apb", 0);
+
+ zynq_clk_register_periph_clk(&clks[pcap_clk],
+ &slcr_base->pcap_clk_ctrl, "pcap", 0);
+
+ zynq_clk_register_periph_clk(&clks[fclk0_clk],
+ &slcr_base->fpga0_clk_ctrl, "fclk0", 1);
+ zynq_clk_register_periph_clk(&clks[fclk1_clk],
+ &slcr_base->fpga1_clk_ctrl, "fclk1", 1);
+ zynq_clk_register_periph_clk(&clks[fclk2_clk],
+ &slcr_base->fpga2_clk_ctrl, "fclk2", 1);
+ zynq_clk_register_periph_clk(&clks[fclk3_clk],
+ &slcr_base->fpga3_clk_ctrl, "fclk3", 1);
+}
+
+/**
+ * zynq_clk_register_aper_clk() - Set up a APER clock with the framework
+ * @clk: Pointer to struct clk for the clock
+ * @ctrl: Clock control register
+ * @name: PLL name
+ */
+static void zynq_clk_register_aper_clk(struct clk *clk, u32 *ctrl, char *name)
+{
+ clk->name = name;
+ clk->reg = ctrl;
+ clk->parent = cpu_1x_clk;
+ clk->frequency = zynq_clk_get_rate(clk->parent);
+}
+
+static void init_aper_clocks(void)
+{
+ zynq_clk_register_aper_clk(&clks[usb0_aper_clk],
+ &slcr_base->aper_clk_ctrl, "usb0_aper");
+ zynq_clk_register_aper_clk(&clks[usb1_aper_clk],
+ &slcr_base->aper_clk_ctrl, "usb1_aper");
+
+ zynq_clk_register_aper_clk(&clks[gem0_aper_clk],
+ &slcr_base->aper_clk_ctrl, "gem0_aper");
+ zynq_clk_register_aper_clk(&clks[gem1_aper_clk],
+ &slcr_base->aper_clk_ctrl, "gem1_aper");
+
+ zynq_clk_register_aper_clk(&clks[sdio0_aper_clk],
+ &slcr_base->aper_clk_ctrl, "sdio0_aper");
+ zynq_clk_register_aper_clk(&clks[sdio1_aper_clk],
+ &slcr_base->aper_clk_ctrl, "sdio1_aper");
+
+ zynq_clk_register_aper_clk(&clks[spi0_aper_clk],
+ &slcr_base->aper_clk_ctrl, "spi0_aper");
+ zynq_clk_register_aper_clk(&clks[spi1_aper_clk],
+ &slcr_base->aper_clk_ctrl, "spi1_aper");
+
+ zynq_clk_register_aper_clk(&clks[can0_aper_clk],
+ &slcr_base->aper_clk_ctrl, "can0_aper");
+ zynq_clk_register_aper_clk(&clks[can1_aper_clk],
+ &slcr_base->aper_clk_ctrl, "can1_aper");
+
+ zynq_clk_register_aper_clk(&clks[i2c0_aper_clk],
+ &slcr_base->aper_clk_ctrl, "i2c0_aper");
+ zynq_clk_register_aper_clk(&clks[i2c1_aper_clk],
+ &slcr_base->aper_clk_ctrl, "i2c1_aper");
+
+ zynq_clk_register_aper_clk(&clks[uart0_aper_clk],
+ &slcr_base->aper_clk_ctrl, "uart0_aper");
+ zynq_clk_register_aper_clk(&clks[uart1_aper_clk],
+ &slcr_base->aper_clk_ctrl, "uart1_aper");
+
+ zynq_clk_register_aper_clk(&clks[gpio_aper_clk],
+ &slcr_base->aper_clk_ctrl, "gpio_aper");
+
+ zynq_clk_register_aper_clk(&clks[lqspi_aper_clk],
+ &slcr_base->aper_clk_ctrl, "lqspi_aper");
+
+ zynq_clk_register_aper_clk(&clks[smc_aper_clk],
+ &slcr_base->aper_clk_ctrl, "smc_aper");
+}
+
+/**
+ * __zynq_clk_pll_get_rate() - Get PLL rate
+ * @addr: Address of the PLL's control register
+ * Returns the current PLL output rate.
+ */
+static unsigned long __zynq_clk_pll_get_rate(u32 *addr)
+{
+ u32 reg, mul, bypass;
+
+ reg = readl(addr);
+ bypass = reg & PLLCTRL_BPFORCE_MASK;
+ if (bypass)
+ mul = 1;
+ else
+ mul = (reg & PLLCTRL_FBDIV_MASK) >> PLLCTRL_FBDIV_SHIFT;
+
+ return CONFIG_ZYNQ_PS_CLK_FREQ * mul;
+}
+
+/**
+ * zynq_clk_pll_get_rate() - Get PLL rate
+ * @pll: Handle of the PLL
+ * Returns the current clock rate of @pll.
+ */
+static unsigned long zynq_clk_pll_get_rate(struct clk *pll)
+{
+ return __zynq_clk_pll_get_rate(pll->reg);
+}
+
+/**
+ * zynq_clk_register_pll() - Set up a PLL with the framework
+ * @clk: Pointer to struct clk for the PLL
+ * @ctrl: PLL control register
+ * @name: PLL name
+ * @prate: PLL input clock rate
+ */
+static void zynq_clk_register_pll(struct clk *clk, u32 *ctrl, char *name,
+ unsigned long prate)
+{
+ clk->name = name;
+ clk->reg = ctrl;
+ clk->frequency = zynq_clk_pll_get_rate(clk);
+ clk->ops.get_rate = zynq_clk_pll_get_rate;
+}
+
+/**
+ * clkid_2_register() - Get clock control register
+ * @id: Clock identifier of one of the PLLs
+ * Returns the address of the requested PLL's control register.
+ */
+static u32 *clkid_2_register(enum zynq_clk id)
+{
+ switch (id) {
+ case armpll_clk:
+ return &slcr_base->arm_pll_ctrl;
+ case ddrpll_clk:
+ return &slcr_base->ddr_pll_ctrl;
+ case iopll_clk:
+ return &slcr_base->io_pll_ctrl;
+ default:
+ return &slcr_base->io_pll_ctrl;
+ }
+}
+
+/* API */
+/**
+ * zynq_clk_early_init() - Early init for the clock framework
+ *
+ * This function is called from before relocation and sets up the CPU clock
+ * frequency in the global data struct.
+ */
+void zynq_clk_early_init(void)
+{
+ u32 reg = readl(&slcr_base->arm_clk_ctrl);
+ u32 div = (reg & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
+ u32 srcsel = (reg & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT;
+ enum zynq_clk parent = __zynq_clk_cpu_get_parent(srcsel);
+ u32 *pllreg = clkid_2_register(parent);
+ unsigned long prate = __zynq_clk_pll_get_rate(pllreg);
+
+ if (!div)
+ div = 1;
+
+ gd->cpu_clk = DIV_ROUND_CLOSEST(prate, div);
+}
+
+/**
+ * get_uart_clk() - Get UART input frequency
+ * @dev_index: UART ID
+ * Returns UART input clock frequency in Hz.
+ *
+ * Compared to zynq_clk_get_rate() this function is designed to work before
+ * relocation and can be called when the serial UART is set up.
+ */
+unsigned long get_uart_clk(int dev_index)
+{
+ u32 reg = readl(&slcr_base->uart_clk_ctrl);
+ u32 div = (reg & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
+ u32 srcsel = (reg & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT;
+ enum zynq_clk parent = __zynq_clk_periph_get_parent(srcsel);
+ u32 *pllreg = clkid_2_register(parent);
+ unsigned long prate = __zynq_clk_pll_get_rate(pllreg);
+
+ if (!div)
+ div = 1;
+
+ return DIV_ROUND_CLOSEST(prate, div);
+}
+
+/**
+ * set_cpu_clk_info() - Initialize clock framework
+ * Always returns zero.
+ *
+ * This function is called from common code after relocation and sets up the
+ * clock framework. The framework must not be used before this function had been
+ * called.
+ */
+int set_cpu_clk_info(void)
+{
+ zynq_clk_register_pll(&clks[armpll_clk], &slcr_base->arm_pll_ctrl,
+ "armpll", CONFIG_ZYNQ_PS_CLK_FREQ);
+ zynq_clk_register_pll(&clks[ddrpll_clk], &slcr_base->ddr_pll_ctrl,
+ "ddrpll", CONFIG_ZYNQ_PS_CLK_FREQ);
+ zynq_clk_register_pll(&clks[iopll_clk], &slcr_base->io_pll_ctrl,
+ "iopll", CONFIG_ZYNQ_PS_CLK_FREQ);
+
+ init_ddr_clocks();
+ init_cpu_clocks();
+ init_periph_clocks();
+ init_aper_clocks();
+
+ gd->bd->bi_arm_freq = gd->cpu_clk / 1000000;
+ gd->bd->bi_dsp_freq = 0;
+
+ return 0;
+}
+
+/**
+ * zynq_clk_get_rate() - Get clock rate
+ * @clk: Clock identifier
+ * Returns the current clock rate of @clk on success or zero for an invalid
+ * clock id.
+ */
+unsigned long zynq_clk_get_rate(enum zynq_clk clk)
+{
+ if (clk < 0 || clk >= clk_max)
+ return 0;
+
+ return clks[clk].frequency;
+}
+
+/**
+ * zynq_clk_set_rate() - Set clock rate
+ * @clk: Clock identifier
+ * @rate: Requested clock rate
+ * Passes on the return value from the clock's set_rate() function or negative
+ * errno.
+ */
+int zynq_clk_set_rate(enum zynq_clk clk, unsigned long rate)
+{
+ if (clk < 0 || clk >= clk_max)
+ return -ENODEV;
+
+ if (clks[clk].ops.set_rate)
+ return clks[clk].ops.set_rate(&clks[clk], rate);
+
+ return -ENXIO;
+}
+
+/**
+ * zynq_clk_get_name() - Get clock name
+ * @clk: Clock identifier
+ * Returns the name of @clk.
+ */
+const char *zynq_clk_get_name(enum zynq_clk clk)
+{
+ return clks[clk].name;
+}
+
+/**
+ * soc_clk_dump() - Print clock frequencies
+ * Returns zero on success
+ *
+ * Implementation for the clk dump command.
+ */
+int soc_clk_dump(void)
+{
+ int i;
+
+ printf("clk\t\tfrequency\n");
+ for (i = 0; i < clk_max; i++) {
+ const char *name = zynq_clk_get_name(i);
+ if (name)
+ printf("%10s%20lu\n", name, zynq_clk_get_rate(i));
+ }
+
+ return 0;
+}
diff --git a/arch/arm/cpu/armv7/zynq/cpu.c b/arch/arm/cpu/armv7/zynq/cpu.c
index 9af340e75e..7626b5c1a3 100644
--- a/arch/arm/cpu/armv7/zynq/cpu.c
+++ b/arch/arm/cpu/armv7/zynq/cpu.c
@@ -6,6 +6,7 @@
*/
#include <common.h>
#include <asm/io.h>
+#include <asm/arch/clk.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/hardware.h>
@@ -16,7 +17,7 @@ void lowlevel_init(void)
int arch_cpu_init(void)
{
zynq_slcr_unlock();
-
+#ifndef CONFIG_SPL_BUILD
/* Device config APB, unlock the PCAP */
writel(0x757BDF0D, &devcfg_base->unlock);
writel(0xFFFFFFFF, &devcfg_base->rom_shadow);
@@ -34,7 +35,8 @@ int arch_cpu_init(void)
/* Urgent write, ports S2/S3 */
writel(0xC, &slcr_base->ddr_urgent);
#endif
-
+#endif
+ zynq_clk_early_init();
zynq_slcr_lock();
return 0;
@@ -46,3 +48,11 @@ void reset_cpu(ulong addr)
while (1)
;
}
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+ /* Enable D-cache. I-cache is already enabled in start.S */
+ dcache_enable();
+}
+#endif
diff --git a/arch/arm/cpu/armv7/zynq/slcr.c b/arch/arm/cpu/armv7/zynq/slcr.c
index b4c11c324c..d7c1882332 100644
--- a/arch/arm/cpu/armv7/zynq/slcr.c
+++ b/arch/arm/cpu/armv7/zynq/slcr.c
@@ -8,6 +8,7 @@
#include <asm/io.h>
#include <malloc.h>
#include <asm/arch/hardware.h>
+#include <asm/arch/clk.h>
#define SLCR_LOCK_MAGIC 0x767B
#define SLCR_UNLOCK_MAGIC 0xDF0D
@@ -50,8 +51,10 @@ void zynq_slcr_cpu_reset(void)
}
/* Setup clk for network */
-void zynq_slcr_gem_clk_setup(u32 gem_id, u32 rclk, u32 clk)
+void zynq_slcr_gem_clk_setup(u32 gem_id, unsigned long clk_rate)
{
+ int ret;
+
zynq_slcr_unlock();
if (gem_id > 1) {
@@ -59,16 +62,16 @@ void zynq_slcr_gem_clk_setup(u32 gem_id, u32 rclk, u32 clk)
goto out;
}
+ ret = zynq_clk_set_rate(gem0_clk + gem_id, clk_rate);
+ if (ret)
+ goto out;
+
if (gem_id) {
- /* Set divisors for appropriate frequency in GEM_CLK_CTRL */
- writel(clk, &slcr_base->gem1_clk_ctrl);
/* Configure GEM_RCLK_CTRL */
- writel(rclk, &slcr_base->gem1_rclk_ctrl);
+ writel(1, &slcr_base->gem1_rclk_ctrl);
} else {
- /* Set divisors for appropriate frequency in GEM_CLK_CTRL */
- writel(clk, &slcr_base->gem0_clk_ctrl);
/* Configure GEM_RCLK_CTRL */
- writel(rclk, &slcr_base->gem0_rclk_ctrl);
+ writel(1, &slcr_base->gem0_rclk_ctrl);
}
udelay(100000);
out:
diff --git a/arch/arm/cpu/armv7/zynq/spl.c b/arch/arm/cpu/armv7/zynq/spl.c
new file mode 100644
index 0000000000..fcad762c03
--- /dev/null
+++ b/arch/arm/cpu/armv7/zynq/spl.c
@@ -0,0 +1,69 @@
+/*
+ * (C) Copyright 2014 Xilinx, Inc. Michal Simek
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <spl.h>
+
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/spl.h>
+#include <asm/arch/sys_proto.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void board_init_f(ulong dummy)
+{
+ ps7_init();
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ /* Set global data pointer. */
+ gd = &gdata;
+
+ preloader_console_init();
+ arch_cpu_init();
+ board_init_r(NULL, 0);
+}
+
+u32 spl_boot_device(void)
+{
+ u32 mode;
+
+ switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
+#ifdef CONFIG_SPL_SPI_SUPPORT
+ case ZYNQ_BM_QSPI:
+ puts("qspi boot\n");
+ mode = BOOT_DEVICE_SPI;
+ break;
+#endif
+#ifdef CONFIG_SPL_MMC_SUPPORT
+ case ZYNQ_BM_SD:
+ puts("mmc boot\n");
+ mode = BOOT_DEVICE_MMC1;
+ break;
+#endif
+ default:
+ puts("Unsupported boot mode selected\n");
+ hang();
+ }
+
+ return mode;
+}
+
+#ifdef CONFIG_SPL_MMC_SUPPORT
+u32 spl_boot_mode(void)
+{
+ return MMCSD_MODE_FAT;
+}
+#endif
+
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+ /* boot linux */
+ return 0;
+}
+#endif
diff --git a/arch/arm/cpu/armv7/zynq/timer.c b/arch/arm/cpu/armv7/zynq/timer.c
index 2be253c2c3..303dbcfcea 100644
--- a/arch/arm/cpu/armv7/zynq/timer.c
+++ b/arch/arm/cpu/armv7/zynq/timer.c
@@ -29,6 +29,7 @@
#include <div64.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
+#include <asm/arch/clk.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -48,7 +49,6 @@ static struct scu_timer *timer_base =
#define TIMER_LOAD_VAL 0xFFFFFFFF
#define TIMER_PRESCALE 255
-#define TIMER_TICK_HZ (CONFIG_CPU_FREQ_HZ / 2 / TIMER_PRESCALE)
int timer_init(void)
{
@@ -56,6 +56,8 @@ int timer_init(void)
(TIMER_PRESCALE << SCUTIMER_CONTROL_PRESCALER_SHIFT) |
SCUTIMER_CONTROL_ENABLE_MASK;
+ gd->arch.timer_rate_hz = (gd->cpu_clk / 2) / (TIMER_PRESCALE + 1);
+
/* Load the timer counter register */
writel(0xFFFFFFFF, &timer_base->load);
@@ -69,7 +71,7 @@ int timer_init(void)
/* Reset time */
gd->arch.lastinc = readl(&timer_base->counter) /
- (TIMER_TICK_HZ / CONFIG_SYS_HZ);
+ (gd->arch.timer_rate_hz / CONFIG_SYS_HZ);
gd->arch.tbl = 0;
return 0;
@@ -83,14 +85,15 @@ ulong get_timer_masked(void)
{
ulong now;
- now = readl(&timer_base->counter) / (TIMER_TICK_HZ / CONFIG_SYS_HZ);
+ now = readl(&timer_base->counter) /
+ (gd->arch.timer_rate_hz / CONFIG_SYS_HZ);
if (gd->arch.lastinc >= now) {
/* Normal mode */
gd->arch.tbl += gd->arch.lastinc - now;
} else {
/* We have an overflow ... */
- gd->arch.tbl += gd->arch.lastinc + TIMER_LOAD_VAL - now;
+ gd->arch.tbl += gd->arch.lastinc + TIMER_LOAD_VAL - now + 1;
}
gd->arch.lastinc = now;
@@ -107,7 +110,8 @@ void __udelay(unsigned long usec)
if (usec == 0)
return;
- countticks = lldiv(TIMER_TICK_HZ * usec, 1000000);
+ countticks = lldiv(((unsigned long long)gd->arch.timer_rate_hz * usec),
+ 1000000);
/* decrementing timer */
timeend = readl(&timer_base->counter) - countticks;
diff --git a/arch/arm/cpu/armv7/zynq/u-boot-spl.lds b/arch/arm/cpu/armv7/zynq/u-boot-spl.lds
new file mode 100644
index 0000000000..0c4501e5c7
--- /dev/null
+++ b/arch/arm/cpu/armv7/zynq/u-boot-spl.lds
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2014 Xilinx, Inc. Michal Simek
+ * Copyright (c) 2004-2008 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
+ LENGTH = CONFIG_SPL_MAX_SIZE }
+MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
+ LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = ALIGN(4);
+ .text :
+ {
+ __image_copy_start = .;
+ CPUDIR/start.o (.text*)
+ *(.text*)
+ } > .sram
+
+ . = ALIGN(4);
+ .rodata : {
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ } > .sram
+
+ . = ALIGN(4);
+ .data : {
+ *(.data*)
+ } > .sram
+
+ . = ALIGN(4);
+
+ . = .;
+
+ __image_copy_end = .;
+
+ _end = .;
+
+ /* Move BSS section to RAM because of FAT */
+ .bss (NOLOAD) : {
+ __bss_start = .;
+ *(.bss*)
+ . = ALIGN(4);
+ __bss_end = .;
+ } > .sdram
+
+ /DISCARD/ : { *(.dynsym) }
+ /DISCARD/ : { *(.dynstr*) }
+ /DISCARD/ : { *(.dynamic*) }
+ /DISCARD/ : { *(.plt*) }
+ /DISCARD/ : { *(.interp*) }
+ /DISCARD/ : { *(.gnu*) }
+}
diff --git a/arch/arm/cpu/armv7/zynq/u-boot.lds b/arch/arm/cpu/armv7/zynq/u-boot.lds
new file mode 100644
index 0000000000..a68b050f2b
--- /dev/null
+++ b/arch/arm/cpu/armv7/zynq/u-boot.lds
@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2004-2008 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ *(.__image_copy_start)
+ CPUDIR/start.o (.text*)
+ *(.text*)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+ . = ALIGN(4);
+ .data : {
+ *(.data*)
+ }
+
+ . = ALIGN(4);
+
+ . = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ }
+
+ . = ALIGN(4);
+
+ .image_copy_end :
+ {
+ *(.__image_copy_end)
+ }
+
+ .rel_dyn_start :
+ {
+ *(.__rel_dyn_start)
+ }
+
+ .rel.dyn : {
+ *(.rel*)
+ }
+
+ .rel_dyn_end :
+ {
+ *(.__rel_dyn_end)
+ }
+
+ _end = .;
+
+/*
+ * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
+ * __bss_base and __bss_limit are for linker only (overlay ordering)
+ */
+
+ .bss_start __rel_dyn_start (OVERLAY) : {
+ KEEP(*(.__bss_start));
+ __bss_base = .;
+ }
+
+ .bss __bss_base (OVERLAY) : {
+ *(.bss*)
+ . = ALIGN(4);
+ __bss_limit = .;
+ }
+
+ .bss_end __bss_limit (OVERLAY) : {
+ KEEP(*(.__bss_end));
+ }
+
+ /*
+ * Zynq needs to discard more sections because the user
+ * is expected to pass this image on to tools for boot.bin
+ * generation that require them to be dropped.
+ */
+ /DISCARD/ : { *(.dynsym) }
+ /DISCARD/ : { *(.dynbss*) }
+ /DISCARD/ : { *(.dynstr*) }
+ /DISCARD/ : { *(.dynamic*) }
+ /DISCARD/ : { *(.plt*) }
+ /DISCARD/ : { *(.interp*) }
+ /DISCARD/ : { *(.gnu*) }
+ /DISCARD/ : { *(.ARM.exidx*) }
+ /DISCARD/ : { *(.gnu.linkonce.armexidx.*) }
+}
generated by cgit (git 2.34.1) at 2024-12-25 13:38:10 +0000