diff options
Diffstat (limited to 'arch/arm/cpu/armv8/fsl-layerscape')
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/Makefile | 4 | ||||
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 14 | ||||
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 113 | ||||
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 4 | ||||
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c | 6 | ||||
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 8 | ||||
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c | 14 | ||||
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/soc.c | 46 | ||||
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/spl.c | 4 |
9 files changed, 80 insertions, 133 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile index cce74052f7..5f86ef90d2 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile @@ -25,10 +25,6 @@ ifneq ($(CONFIG_LS2080A),) obj-$(CONFIG_SYS_HAS_SERDES) += ls2080a_serdes.o endif -ifneq ($(CONFIG_LS2085A),) -obj-$(CONFIG_SYS_HAS_SERDES) += ls2080a_serdes.o -endif - ifneq ($(CONFIG_LS1043A),) obj-$(CONFIG_SYS_HAS_SERDES) += ls1043a_serdes.o endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 7404bd932a..d93990036b 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -410,6 +410,11 @@ static inline void final_mmu_setup(void) */ } +u64 get_page_table_size(void) +{ + return 0x10000; +} + int arch_cpu_init(void) { icache_enable(); @@ -533,12 +538,12 @@ int print_cpuinfo(void) struct sys_info sysinfo; char buf[32]; unsigned int i, core; - u32 type, rcw; + u32 type, rcw, svr = gur_in32(&gur->svr); puts("SoC: "); cpu_name(buf); - printf(" %s (0x%x)\n", buf, gur_in32(&gur->svr)); + printf(" %s (0x%x)\n", buf, svr); memset((u8 *)buf, 0x00, ARRAY_SIZE(buf)); get_sys_info(&sysinfo); puts("Clock Configuration:"); @@ -559,7 +564,10 @@ int print_cpuinfo(void) printf(" FMAN: %-4s MHz", strmhz(buf, sysinfo.freq_fman[0])); #endif #ifdef CONFIG_SYS_FSL_HAS_DP_DDR - printf(" DP-DDR: %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus2)); + if (soc_has_dp_ddr()) { + printf(" DP-DDR: %-4s MT/s", + strmhz(buf, sysinfo.freq_ddrbus2)); + } #endif puts("\n"); diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index 9c18fd7a16..1e875c4b08 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -73,115 +73,6 @@ void ft_fixup_cpu(void *blob) } #endif -/* - * the burden is on the the caller to not request a count - * exceeding the bounds of the stream_ids[] array - */ -void alloc_stream_ids(int start_id, int count, u32 *stream_ids, int max_cnt) -{ - int i; - - if (count > max_cnt) { - printf("\n%s: ERROR: max per-device stream ID count exceed\n", - __func__); - return; - } - - for (i = 0; i < count; i++) - stream_ids[i] = start_id++; -} - -/* - * This function updates the mmu-masters property on the SMMU - * node as per the SMMU binding-- phandle and list of stream IDs - * for each MMU master. - */ -void append_mmu_masters(void *blob, const char *smmu_path, - const char *master_name, u32 *stream_ids, int count) -{ - u32 phandle; - int smmu_nodeoffset; - int master_nodeoffset; - int i; - - /* get phandle of mmu master device */ - master_nodeoffset = fdt_path_offset(blob, master_name); - if (master_nodeoffset < 0) { - printf("\n%s: ERROR: master not found\n", __func__); - return; - } - phandle = fdt_get_phandle(blob, master_nodeoffset); - if (!phandle) { /* if master has no phandle, create one */ - phandle = fdt_create_phandle(blob, master_nodeoffset); - if (!phandle) { - printf("\n%s: ERROR: unable to create phandle\n", - __func__); - return; - } - } - - /* append it to mmu-masters */ - smmu_nodeoffset = fdt_path_offset(blob, smmu_path); - if (fdt_appendprop_u32(blob, smmu_nodeoffset, "mmu-masters", - phandle) < 0) { - printf("\n%s: ERROR: unable to update SMMU node\n", __func__); - return; - } - - /* for each stream ID, append to mmu-masters */ - for (i = 0; i < count; i++) { - fdt_appendprop_u32(blob, smmu_nodeoffset, "mmu-masters", - stream_ids[i]); - } - - /* fix up #stream-id-cells with stream ID count */ - if (fdt_setprop_u32(blob, master_nodeoffset, "#stream-id-cells", - count) < 0) - printf("\n%s: ERROR: unable to update #stream-id-cells\n", - __func__); -} - - -/* - * The info below summarizes how streamID partitioning works - * for ls2080a and how it is conveyed to the OS via the device tree. - * - * -non-PCI legacy, platform devices (USB, SD/MMC, SATA, DMA) - * -all legacy devices get a unique ICID assigned and programmed in - * their AMQR registers by u-boot - * -u-boot updates the hardware device tree with streamID properties - * for each platform/legacy device (smmu-masters property) - * - * -PCIe - * -for each PCI controller that is active (as per RCW settings), - * u-boot will allocate a range of ICID and convey that to Linux via - * the device tree (smmu-masters property) - * - * -DPAA2 - * -u-boot will allocate a range of ICIDs to be used by the Management - * Complex for containers and will set these values in the MC DPC image. - * -the MC is responsible for allocating and setting up ICIDs - * for all DPAA2 devices. - * - */ -#ifdef CONFIG_FSL_LSCH3 -static void fdt_fixup_smmu(void *blob) -{ - int nodeoffset; - - nodeoffset = fdt_path_offset(blob, "/iommu@5000000"); - if (nodeoffset < 0) { - printf("\n%s: WARNING: no SMMU node found\n", __func__); - return; - } - - /* fixup for all PCI controllers */ -#ifdef CONFIG_PCI - fdt_fixup_smmu_pcie(blob); -#endif -} -#endif - void ft_cpu_setup(void *blob, bd_t *bd) { #ifdef CONFIG_MP @@ -204,10 +95,6 @@ void ft_cpu_setup(void *blob, bd_t *bd) fdt_fixup_esdhc(blob, bd); #endif -#ifdef CONFIG_FSL_LSCH3 - fdt_fixup_smmu(blob); -#endif - #ifdef CONFIG_SYS_DPAA_FMAN fdt_fixup_fman_firmware(blob); #endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c index 6f6a588292..453a93d94c 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c @@ -106,9 +106,13 @@ void get_sys_info(struct sys_info *sys_info) #define HWA_CGA_M2_CLK_SEL 0x00000007 #define HWA_CGA_M2_CLK_SHIFT 0 #ifdef CONFIG_FSL_ESDHC +#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK rcw_tmp = in_be32(&gur->rcwsr[15]); rcw_tmp = (rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT; sys_info->freq_sdhc = freq_c_pll[1] / rcw_tmp; +#else + sys_info->freq_sdhc = sys_info->freq_systembus; +#endif #endif #if defined(CONFIG_FSL_IFC) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c index 81cf47049f..d580a43b41 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c @@ -97,9 +97,13 @@ void get_sys_info(struct sys_info *sys_info) FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) & FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK; #ifdef CONFIG_SYS_FSL_HAS_DP_DDR - sys_info->freq_ddrbus2 *= (gur_in32(&gur->rcwsr[0]) >> + if (soc_has_dp_ddr()) { + sys_info->freq_ddrbus2 *= (gur_in32(&gur->rcwsr[0]) >> FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT) & FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK; + } else { + sys_info->freq_ddrbus2 = 0; + } #endif for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) { diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index 41e1704986..04831ca5bb 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -18,6 +18,14 @@ ENTRY(lowlevel_init) mov x29, lr /* Save LR */ #ifdef CONFIG_FSL_LSCH3 + + /* Set Wuo bit for RN-I 20 */ +#ifdef CONFIG_LS2080A + ldr x0, =CCI_AUX_CONTROL_BASE(20) + ldr x1, =0x00000010 + bl ccn504_set_aux +#endif + /* Add fully-coherent masters to DVM domain */ ldr x0, =CCI_MN_BASE ldr x1, =CCI_MN_RNF_NODEID_LIST diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c index ea3114cca4..eaa44a74c5 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c @@ -14,7 +14,7 @@ struct serdes_config { static struct serdes_config serdes1_cfg_tbl[] = { /* SerDes 1 */ - {0x03, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2 } }, + {0x03, {PCIE2, PCIE2, PCIE2, PCIE2, PCIE1, PCIE1, PCIE1, PCIE1 } }, {0x05, {PCIE2, PCIE2, PCIE2, PCIE2, SGMII4, SGMII3, SGMII2, SGMII1 } }, {0x07, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2, SGMII1 } }, @@ -31,9 +31,9 @@ static struct serdes_config serdes1_cfg_tbl[] = { {0x2A, {XFI8, XFI7, XFI6, XFI5, XFI4, XFI3, XFI2, XFI1 } }, {0x2B, {SGMII8, SGMII7, SGMII6, SGMII5, XAUI1, XAUI1, XAUI1, XAUI1 } }, {0x32, {XAUI2, XAUI2, XAUI2, XAUI2, XAUI1, XAUI1, XAUI1, XAUI1 } }, - {0x33, {PCIE2, PCIE2, PCIE2, PCIE2, QSGMII_C, QSGMII_D, QSGMII_A, - QSGMII_B} }, - {0x35, {QSGMII_C, QSGMII_D, QSGMII_A, PCIE2, XFI4, XFI3, XFI2, XFI1 } }, + {0x33, {PCIE2, PCIE2, PCIE2, PCIE2, QSGMII_D, QSGMII_C, QSGMII_B, + QSGMII_A} }, + {0x35, {QSGMII_D, QSGMII_C, QSGMII_B, PCIE2, XFI4, XFI3, XFI2, XFI1 } }, {} }; static struct serdes_config serdes2_cfg_tbl[] = { @@ -56,10 +56,10 @@ static struct serdes_config serdes2_cfg_tbl[] = { {0x42, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2 } }, {0x43, {PCIE3, PCIE3, PCIE3, PCIE3, NONE, NONE, SATA1, SATA2 } }, {0x44, {PCIE3, PCIE3, PCIE3, PCIE3, NONE, NONE, SATA1, SATA2 } }, - {0x45, {PCIE3, SGMII10, SGMII11, SGMII12, PCIE4, SGMII14, SGMII15, - SGMII16 } }, - {0x47, {SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, PCIE4, + {0x45, {SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, PCIE4, PCIE4 } }, + {0x47, {PCIE3, SGMII10, SGMII11, SGMII12, PCIE4, SGMII14, SGMII15, + SGMII16 } }, {0x49, {SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, SATA1, SATA2 } }, {0x4A, {SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, SATA1, diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 213ce3a824..0cb010012e 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -18,7 +18,31 @@ DECLARE_GLOBAL_DATA_PTR; -#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) +bool soc_has_dp_ddr(void) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + u32 svr = gur_in32(&gur->svr); + + /* LS2085A has DP_DDR */ + if (SVR_SOC_VER(svr) == SVR_LS2085) + return true; + + return false; +} + +bool soc_has_aiop(void) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + u32 svr = gur_in32(&gur->svr); + + /* LS2085A has AIOP */ + if (SVR_SOC_VER(svr) == SVR_LS2085) + return true; + + return false; +} + +#ifdef CONFIG_LS2080A /* * This erratum requires setting a value to eddrtqcr1 to * optimal the DDR performance. @@ -151,7 +175,14 @@ static void erratum_a009203(void) #endif #endif } - +void bypass_smmu(void) +{ + u32 val; + val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); + out_le32(SMMU_SCR0, val); + val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); + out_le32(SMMU_NSCR0, val); +} void fsl_lsch3_early_init_f(void) { erratum_a008751(); @@ -160,6 +191,15 @@ void fsl_lsch3_early_init_f(void) erratum_a009203(); erratum_a008514(); erratum_a008336(); +#ifdef CONFIG_CHAIN_OF_TRUST + /* In case of Secure Boot, the IBR configures the SMMU + * to allow only Secure transactions. + * SMMU must be reset in bypass mode. + * Set the ClientPD bit and Clear the USFCFG Bit + */ + if (fsl_check_boot_mode_secure() == 1) + bypass_smmu(); +#endif } #ifdef CONFIG_SCSI_AHCI_PLAT @@ -240,7 +280,7 @@ void fsl_lsch2_early_init_f(void) init_early_memctl_regs(); /* tighten IFC timing */ #endif -#ifdef CONFIG_FSL_QSPI +#if defined(CONFIG_FSL_QSPI) && !defined(CONFIG_QSPI_BOOT) out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); #endif /* Make SEC reads and writes snoopable */ diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c index f434c443ed..c1229c88af 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c @@ -46,7 +46,7 @@ void board_init_f(ulong dummy) { /* Clear global data */ memset((void *)gd, 0, sizeof(gd_t)); -#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) +#ifdef CONFIG_LS2080A arch_cpu_init(); #endif #ifdef CONFIG_FSL_IFC @@ -54,7 +54,7 @@ void board_init_f(ulong dummy) #endif board_early_init_f(); timer_init(); -#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) +#ifdef CONFIG_LS2080A env_init(); #endif get_clocks(); |