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-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/Kconfig25
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/cpu.c22
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c20
3 files changed, 61 insertions, 6 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 01c5068ab6..f48481f465 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -2,6 +2,7 @@ config ARCH_LS1012A
bool
select ARMV8_SET_SMPEN
select ARM_ERRATA_855873 if !TFABOOT
+ select FSL_LAYERSCAPE
select FSL_LSCH2
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
@@ -23,6 +24,7 @@ config ARCH_LS1043A
bool
select ARMV8_SET_SMPEN
select ARM_ERRATA_855873 if !TFABOOT
+ select FSL_LAYERSCAPE
select FSL_LSCH2
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
@@ -49,13 +51,12 @@ config ARCH_LS1043A
select SYS_I2C_MXC_I2C2
select SYS_I2C_MXC_I2C3
select SYS_I2C_MXC_I2C4
- imply SCSI
- imply SCSI_AHCI
imply CMD_PCI
config ARCH_LS1046A
bool
select ARMV8_SET_SMPEN
+ select FSL_LAYERSCAPE
select FSL_LSCH2
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
@@ -90,6 +91,7 @@ config ARCH_LS1088A
bool
select ARMV8_SET_SMPEN
select ARM_ERRATA_855873 if !TFABOOT
+ select FSL_LAYERSCAPE
select FSL_LSCH3
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
@@ -113,6 +115,8 @@ config ARCH_LS1088A
select SYS_FSL_SRDS_1
select SYS_FSL_SRDS_2
select FSL_TZASC_1
+ select FSL_TZASC_400
+ select FSL_TZPC_BP147
select ARCH_EARLY_INIT_R
select BOARD_EARLY_INIT_F
select SYS_I2C_MXC
@@ -130,6 +134,7 @@ config ARCH_LS2080A
select ARM_ERRATA_828024
select ARM_ERRATA_829520
select ARM_ERRATA_833471
+ select FSL_LAYERSCAPE
select FSL_LSCH3
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
@@ -145,6 +150,8 @@ config ARCH_LS2080A
select SYS_FSL_SRDS_2
select FSL_TZASC_1
select FSL_TZASC_2
+ select FSL_TZASC_400
+ select FSL_TZPC_BP147
select SYS_FSL_ERRATUM_A008336 if !TFABOOT
select SYS_FSL_ERRATUM_A008511 if !TFABOOT
select SYS_FSL_ERRATUM_A008514 if !TFABOOT
@@ -230,6 +237,9 @@ config FSL_MC_ENET
menu "Layerscape architecture"
depends on FSL_LSCH2 || FSL_LSCH3
+config FSL_LAYERSCAPE
+ bool
+
config FSL_PCIE_COMPAT
string "PCIe compatible of Kernel DT"
depends on PCIE_LAYERSCAPE
@@ -346,6 +356,12 @@ config MAX_CPUS
cores, count the reserved ports. This will allocate enough memory
in spin table to properly handle all cores.
+config EMC2305
+ bool "Fan controller"
+ help
+ Enable the EMC2305 fan controller for configuration of fan
+ speed.
+
config SECURE_BOOT
bool "Secure Boot"
help
@@ -404,6 +420,11 @@ config FSL_TZASC_1
config FSL_TZASC_2
bool
+config FSL_TZASC_400
+ bool
+
+config FSL_TZPC_BP147
+ bool
endmenu
menu "Layerscape clock tree configuration"
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index be21685eaa..978d46b32f 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -1099,15 +1099,29 @@ int arch_early_init_r(void)
printf("Did not wake secondary cores\n");
}
-#ifdef CONFIG_SYS_FSL_HAS_RGMII
- fsl_rgmii_init();
-#endif
-
config_core_prefetch();
#ifdef CONFIG_SYS_HAS_SERDES
fsl_serdes_init();
#endif
+#ifdef CONFIG_SYS_FSL_HAS_RGMII
+ /* some dpmacs in armv8a based freescale layerscape SOCs can be
+ * configured via both serdes(sgmii, xfi, xlaui etc) bits and via
+ * EC*_PMUX(rgmii) bits in RCW.
+ * e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from
+ * serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits
+ * Now if a dpmac is enabled by serdes bits then it takes precedence
+ * over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol
+ * that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII,
+ * then the dpmac is SGMII and not RGMII.
+ *
+ * Therefore, move the fsl_rgmii_init after fsl_serdes_init. in
+ * fsl_rgmii_init function of SOC, we will check if the dpmac is enabled
+ * or not? if it is (fsl_serdes_init has already enabled the dpmac),
+ * then don't enable it.
+ */
+ fsl_rgmii_init();
+#endif
#ifdef CONFIG_FMAN_ENET
fman_enet_init();
#endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
index ab1be3fa54..1a747a9e3d 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
@@ -548,12 +548,32 @@ void fsl_serdes_init(void)
#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
int i , j;
+#ifdef CONFIG_ARCH_LX2160A
+ for (i = XFI1, j = 1; i <= XFI14; i++, j++)
+ xfi_dpmac[i] = j;
+
+ for (i = SGMII1, j = 1; i <= SGMII18; i++, j++)
+ sgmii_dpmac[i] = j;
+
+ for (i = _25GE1, j = 1; i <= _25GE10; i++, j++)
+ a25gaui_dpmac[i] = j;
+
+ for (i = _40GE1, j = 1; i <= _40GE2; i++, j++)
+ xlaui_dpmac[i] = j;
+
+ for (i = _50GE1, j = 1; i <= _50GE2; i++, j++)
+ caui2_dpmac[i] = j;
+
+ for (i = _100GE1, j = 1; i <= _100GE2; i++, j++)
+ caui4_dpmac[i] = j;
+#else
for (i = XFI1, j = 1; i <= XFI8; i++, j++)
xfi_dpmac[i] = j;
for (i = SGMII1, j = 1; i <= SGMII16; i++, j++)
sgmii_dpmac[i] = j;
#endif
+#endif
#ifdef CONFIG_SYS_FSL_SRDS_1
serdes_init(FSL_SRDS_1,