diff options
Diffstat (limited to 'arch/arm/cpu/armv8/zynqmp')
| -rw-r--r-- | arch/arm/cpu/armv8/zynqmp/Kconfig | 20 | ||||
| -rw-r--r-- | arch/arm/cpu/armv8/zynqmp/Makefile | 1 | ||||
| -rw-r--r-- | arch/arm/cpu/armv8/zynqmp/cpu.c | 16 | ||||
| -rw-r--r-- | arch/arm/cpu/armv8/zynqmp/mp.c | 14 | ||||
| -rw-r--r-- | arch/arm/cpu/armv8/zynqmp/slcr.c | 63 | ||||
| -rw-r--r-- | arch/arm/cpu/armv8/zynqmp/spl.c | 5 |
6 files changed, 53 insertions, 66 deletions
diff --git a/arch/arm/cpu/armv8/zynqmp/Kconfig b/arch/arm/cpu/armv8/zynqmp/Kconfig index 5ffc9f6c86..3f922b4097 100644 --- a/arch/arm/cpu/armv8/zynqmp/Kconfig +++ b/arch/arm/cpu/armv8/zynqmp/Kconfig @@ -42,6 +42,13 @@ config SYS_CONFIG_NAME Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header will be used for board configuration. +config SYS_MEM_RSVD_FOR_MMU + bool "Reserve memory for MMU Table" + help + If defined this option is used to setup different space for + MMU table than the one which will be allocated during + relocation. + config BOOT_INIT_FILE string "boot.bin init register filename" depends on SPL @@ -50,6 +57,14 @@ config BOOT_INIT_FILE Add register writes to boot.bin format (max 256 pairs). Expect a table of register-value pairs, e.g. "0x12345678 0x4321" +config PMUFW_INIT_FILE + string "PMU firmware" + depends on SPL + default "" + help + Include external PMUFW (Platform Management Unit FirmWare) to + a Xilinx bootable image (boot.bin). + config ZYNQMP_USB bool "Configure ZynqMP USB" @@ -58,6 +73,7 @@ config SYS_MALLOC_F_LEN config DEFINE_TCM_OCM_MMAP bool "Define TCM and OCM memory in MMU Table" + default y if MP help This option if enabled defines the TCM and OCM memory and its memory attributes in MMU table entry. @@ -86,6 +102,7 @@ config SPL_ZYNQMP_ALT_BOOTMODE default 0x7 if USB_MODE default 0xa if SW_USBHOST_MODE default 0xb if SW_SATA_MODE + default 0xe if SD1_LSHFT_MODE choice prompt "Boot mode" @@ -122,6 +139,9 @@ config SW_USBHOST_MODE config SW_SATA_MODE bool "SW SATA_MODE" +config SD1_LSHFT_MODE + bool "SD1_LSHFT_MODE" + endchoice endif diff --git a/arch/arm/cpu/armv8/zynqmp/Makefile b/arch/arm/cpu/armv8/zynqmp/Makefile index 013f136707..72dee3ded4 100644 --- a/arch/arm/cpu/armv8/zynqmp/Makefile +++ b/arch/arm/cpu/armv8/zynqmp/Makefile @@ -8,5 +8,4 @@ obj-y += clk.o obj-y += cpu.o obj-$(CONFIG_MP) += mp.o -obj-y += slcr.o obj-$(CONFIG_SPL_BUILD) += spl.o handoff.o diff --git a/arch/arm/cpu/armv8/zynqmp/cpu.c b/arch/arm/cpu/armv8/zynqmp/cpu.c index 1b5066a826..f026cb4511 100644 --- a/arch/arm/cpu/armv8/zynqmp/cpu.c +++ b/arch/arm/cpu/armv8/zynqmp/cpu.c @@ -77,6 +77,18 @@ u64 get_page_table_size(void) return 0x14000; } +#ifdef CONFIG_SYS_MEM_RSVD_FOR_MMU +int reserve_mmu(void) +{ + initialize_tcm(TCM_LOCK); + memset((void *)ZYNQMP_TCM_BASE_ADDR, 0, ZYNQMP_TCM_SIZE); + gd->arch.tlb_size = PGTABLE_SIZE; + gd->arch.tlb_addr = ZYNQMP_TCM_BASE_ADDR; + + return 0; +} +#endif + static unsigned int zynqmp_get_silicon_version_secure(void) { u32 ver; @@ -198,7 +210,7 @@ int zynqmp_mmio_write(const u32 address, { if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) return zynqmp_mmio_rawwrite(address, mask, value); - else if (!IS_ENABLED(CONFIG_SPL_BUILD)) + else return invoke_smc(ZYNQMP_MMIO_WRITE, address, mask, value, 0, NULL); @@ -215,7 +227,7 @@ int zynqmp_mmio_read(const u32 address, u32 *value) if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) { ret = zynqmp_mmio_rawread(address, value); - } else if (!IS_ENABLED(CONFIG_SPL_BUILD)) { + } else { ret = invoke_smc(ZYNQMP_MMIO_READ, address, 0, 0, 0, ret_payload); *value = ret_payload[1]; diff --git a/arch/arm/cpu/armv8/zynqmp/mp.c b/arch/arm/cpu/armv8/zynqmp/mp.c index 76f889ba7d..3ea24b4763 100644 --- a/arch/arm/cpu/armv8/zynqmp/mp.c +++ b/arch/arm/cpu/armv8/zynqmp/mp.c @@ -257,22 +257,36 @@ int cpu_release(int nr, int argc, char * const argv[]) boot_addr = ZYNQMP_R5_LOVEC_ADDR; } + /* + * Since we don't know where the user may have loaded the image + * for an R5 we have to flush all the data cache to ensure + * the R5 sees it. + */ + flush_dcache_all(); + if (!strncmp(argv[1], "lockstep", 8)) { printf("R5 lockstep mode\n"); + set_r5_reset(LOCK); set_r5_tcm_mode(LOCK); set_r5_halt_mode(HALT, LOCK); set_r5_start(boot_addr); enable_clock_r5(); release_r5_reset(LOCK); + dcache_disable(); write_tcm_boot_trampoline(boot_addr_uniq); + dcache_enable(); set_r5_halt_mode(RELEASE, LOCK); } else if (!strncmp(argv[1], "split", 5)) { printf("R5 split mode\n"); + set_r5_reset(SPLIT); set_r5_tcm_mode(SPLIT); set_r5_halt_mode(HALT, SPLIT); + set_r5_start(boot_addr); enable_clock_r5(); release_r5_reset(SPLIT); + dcache_disable(); write_tcm_boot_trampoline(boot_addr_uniq); + dcache_enable(); set_r5_halt_mode(RELEASE, SPLIT); } else { printf("Unsupported mode\n"); diff --git a/arch/arm/cpu/armv8/zynqmp/slcr.c b/arch/arm/cpu/armv8/zynqmp/slcr.c deleted file mode 100644 index 713e9a62c0..0000000000 --- a/arch/arm/cpu/armv8/zynqmp/slcr.c +++ /dev/null @@ -1,63 +0,0 @@ -/* - * (C) Copyright 2014 - 2015 Xilinx, Inc. - * Michal Simek <michal.simek@xilinx.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <malloc.h> -#include <asm/arch/hardware.h> -#include <asm/arch/sys_proto.h> -#include <asm/arch/clk.h> - -/* - * zynq_slcr_mio_get_status - Get the status of MIO peripheral. - * - * @peri_name: Name of the peripheral for checking MIO status - * @get_pins: Pointer to array of get pin for this peripheral - * @num_pins: Number of pins for this peripheral - * @mask: Mask value - * @check_val: Required check value to get the status of periph - */ -struct zynq_slcr_mio_get_status { - const char *peri_name; - const int *get_pins; - int num_pins; - u32 mask; - u32 check_val; -}; - -static const struct zynq_slcr_mio_get_status mio_periphs[] = { -}; - -/* - * zynq_slcr_get_mio_pin_status - Get the MIO pin status of peripheral. - * - * @periph: Name of the peripheral - * - * Returns count to indicate the number of pins configured for the - * given @periph. - */ -int zynq_slcr_get_mio_pin_status(const char *periph) -{ - const struct zynq_slcr_mio_get_status *mio_ptr; - int val, i, j; - int mio = 0; - - for (i = 0; i < ARRAY_SIZE(mio_periphs); i++) { - if (strcmp(periph, mio_periphs[i].peri_name) == 0) { - mio_ptr = &mio_periphs[i]; - for (j = 0; j < mio_ptr->num_pins; j++) { - val = readl(&slcr_base->mio_pin - [mio_ptr->get_pins[j]]); - if ((val & mio_ptr->mask) == mio_ptr->check_val) - mio++; - } - break; - } - } - - return mio; -} diff --git a/arch/arm/cpu/armv8/zynqmp/spl.c b/arch/arm/cpu/armv8/zynqmp/spl.c index 468dc1dc4d..41b0070a5e 100644 --- a/arch/arm/cpu/armv8/zynqmp/spl.c +++ b/arch/arm/cpu/armv8/zynqmp/spl.c @@ -102,6 +102,11 @@ u32 spl_boot_device(void) case SW_SATA_MODE: return BOOT_DEVICE_SATA; #endif +#ifdef CONFIG_SPL_SPI_SUPPORT + case QSPI_MODE_24BIT: + case QSPI_MODE_32BIT: + return BOOT_DEVICE_SPI; +#endif default: printf("Invalid Boot Mode:0x%x\n", bootmode); break; |