diff options
Diffstat (limited to 'arch/arm/cpu/armv8')
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 3 | ||||
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c | 5 | ||||
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/soc.c | 9 | ||||
| -rw-r--r-- | arch/arm/cpu/armv8/start.S | 19 | ||||
| -rw-r--r-- | arch/arm/cpu/armv8/zynqmp/Kconfig | 4 | ||||
| -rw-r--r-- | arch/arm/cpu/armv8/zynqmp/clk.c | 20 | ||||
| -rw-r--r-- | arch/arm/cpu/armv8/zynqmp/cpu.c | 18 |
7 files changed, 67 insertions, 11 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index eafdd71a84..4e4861d107 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -190,6 +190,9 @@ void ft_cpu_setup(void *blob, bd_t *bd) "clock-frequency", CONFIG_SYS_NS16550_CLK, 1); #endif + do_fixup_by_compat_u32(blob, "fixed-clock", + "clock-frequency", CONFIG_SYS_CLK_FREQ, 1); + #ifdef CONFIG_PCI ft_pci_setup(blob, bd); #endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c index 8ef4f1c38f..ea3114cca4 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c @@ -28,12 +28,7 @@ static struct serdes_config serdes1_cfg_tbl[] = { SGMII1 } }, {0x26, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, XFI2, XFI1 } }, {0x28, {SGMII8, SGMII7, SGMII6, SGMII5, XFI4, XFI3, XFI2, XFI1 } }, -#ifdef CONFIG_LS2080A - {0x2A, {NONE, NONE, NONE, XFI5, XFI4, XFI3, XFI2, XFI1 } }, -#endif -#ifdef CONFIG_LS2085A {0x2A, {XFI8, XFI7, XFI6, XFI5, XFI4, XFI3, XFI2, XFI1 } }, -#endif {0x2B, {SGMII8, SGMII7, SGMII6, SGMII5, XAUI1, XAUI1, XAUI1, XAUI1 } }, {0x32, {XAUI2, XAUI2, XAUI2, XAUI2, XAUI1, XAUI1, XAUI1, XAUI1 } }, {0x33, {PCIE2, PCIE2, PCIE2, PCIE2, QSGMII_C, QSGMII_D, QSGMII_A, diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 23d6b73e3d..7ff01481be 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -12,6 +12,9 @@ #include <asm/io.h> #include <asm/global_data.h> #include <asm/arch-fsl-layerscape/config.h> +#ifdef CONFIG_CHAIN_OF_TRUST +#include <fsl_validate.h> +#endif DECLARE_GLOBAL_DATA_PTR; @@ -219,6 +222,9 @@ void fsl_lsch2_early_init_f(void) init_early_memctl_regs(); /* tighten IFC timing */ #endif +#ifdef CONFIG_FSL_QSPI + out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); +#endif /* Make SEC reads and writes snoopable */ setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP | SCFG_SNPCNFGCR_SECWRSNP); @@ -241,6 +247,9 @@ int board_late_init(void) #ifdef CONFIG_SCSI_AHCI_PLAT sata_init(); #endif +#ifdef CONFIG_CHAIN_OF_TRUST + fsl_setenv_chain_of_trust(); +#endif return 0; } diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S index 2ee60d60f1..67b166c7fd 100644 --- a/arch/arm/cpu/armv8/start.S +++ b/arch/arm/cpu/armv8/start.S @@ -168,6 +168,25 @@ apply_a57_core_errata: msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */ #endif +#ifdef CONFIG_ARM_ERRATA_833471 + mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */ + /* FPSCR write flush. + * Note that in some cases where a flush is unnecessary this + could impact performance. */ + orr x0, x0, #1 << 38 + msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */ +#endif + +#ifdef CONFIG_ARM_ERRATA_829520 + mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */ + /* Disable Indirect Predictor bit will prevent this erratum + from occurring + * Note that in some cases where a flush is unnecessary this + could impact performance. */ + orr x0, x0, #1 << 4 + msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */ +#endif + #ifdef CONFIG_ARM_ERRATA_833069 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */ /* Disable Enable Invalidates of BTB bit */ diff --git a/arch/arm/cpu/armv8/zynqmp/Kconfig b/arch/arm/cpu/armv8/zynqmp/Kconfig index e5a4fdd0fd..9a19dfa77f 100644 --- a/arch/arm/cpu/armv8/zynqmp/Kconfig +++ b/arch/arm/cpu/armv8/zynqmp/Kconfig @@ -20,10 +20,6 @@ config SYS_SOC config SYS_CONFIG_NAME default "xilinx_zynqmp_ep" if TARGET_ZYNQMP_EP -config SECURE_IOU - bool "Configure ZynqMP secure IOU" - default n - config ZYNQMP_USB bool "Configure ZynqMP USB" diff --git a/arch/arm/cpu/armv8/zynqmp/clk.c b/arch/arm/cpu/armv8/zynqmp/clk.c index 9218586e94..690c72dd66 100644 --- a/arch/arm/cpu/armv8/zynqmp/clk.c +++ b/arch/arm/cpu/armv8/zynqmp/clk.c @@ -21,9 +21,27 @@ unsigned long get_uart_clk(int dev_id) return 48000; case ZYNQMP_CSU_VERSION_EP108: return 25000000; + case ZYNQMP_CSU_VERSION_QEMU: + return 133000000; } - return 133000000; + return 100000000; +} + +unsigned long zynqmp_get_system_timer_freq(void) +{ + u32 ver = zynqmp_get_silicon_version(); + + switch (ver) { + case ZYNQMP_CSU_VERSION_VELOCE: + return 10000; + case ZYNQMP_CSU_VERSION_EP108: + return 4000000; + case ZYNQMP_CSU_VERSION_QEMU: + return 50000000; + } + + return 100000000; } #ifdef CONFIG_CLOCKS diff --git a/arch/arm/cpu/armv8/zynqmp/cpu.c b/arch/arm/cpu/armv8/zynqmp/cpu.c index f90cca36aa..c71f29152d 100644 --- a/arch/arm/cpu/armv8/zynqmp/cpu.c +++ b/arch/arm/cpu/armv8/zynqmp/cpu.c @@ -15,8 +15,22 @@ DECLARE_GLOBAL_DATA_PTR; +static unsigned int zynqmp_get_silicon_version_secure(void) +{ + u32 ver; + + ver = readl(&csu_base->version); + ver &= ZYNQMP_SILICON_VER_MASK; + ver >>= ZYNQMP_SILICON_VER_SHIFT; + + return ver; +} + unsigned int zynqmp_get_silicon_version(void) { + if (current_el() == 3) + return zynqmp_get_silicon_version_secure(); + gd->cpu_clk = get_tbclk(); switch (gd->cpu_clk) { @@ -24,9 +38,11 @@ unsigned int zynqmp_get_silicon_version(void) return ZYNQMP_CSU_VERSION_VELOCE; case 50000000: return ZYNQMP_CSU_VERSION_QEMU; + case 4000000: + return ZYNQMP_CSU_VERSION_EP108; } - return ZYNQMP_CSU_VERSION_EP108; + return ZYNQMP_CSU_VERSION_SILICON; } #ifndef CONFIG_SYS_DCACHE_OFF |