diff options
Diffstat (limited to 'arch/arm/cpu/armv8')
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 13 | ||||
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 1 | ||||
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/soc.c | 10 |
3 files changed, 21 insertions, 3 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index cdeef26fe5..3e02132537 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -85,6 +85,7 @@ config ARCH_LS2080A config FSL_LSCH2 bool + select SYS_FSL_HAS_CCI400 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_COMPAT_5 select SYS_FSL_SEC_BE @@ -248,6 +249,15 @@ config QSPI_AHB_INIT But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB bus for those flashes to support the full QSPI flash size. +config SYS_CCI400_OFFSET + hex "Offset for CCI400 base" + depends on SYS_FSL_HAS_CCI400 + default 0x3090000 if ARCH_LS1088A + default 0x180000 if FSL_LSCH2 + help + Offset for CCI400 base + CCI400 base addr = CCSRBAR + CCI400_OFFSET + config SYS_FSL_IFC_BANK_COUNT int "Maximum banks of Integrated flash controller" depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A @@ -255,6 +265,9 @@ config SYS_FSL_IFC_BANK_COUNT default 4 if ARCH_LS1046A default 8 if ARCH_LS2080A +config SYS_FSL_HAS_CCI400 + bool + config SYS_FSL_HAS_DP_DDR bool diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index c6fede31ba..ec5806517a 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -16,6 +16,7 @@ #include <asm/arch/soc.h> #include <asm/arch/cpu.h> #include <asm/arch/speed.h> +#include <fsl_immap.h> #include <asm/arch/mp.h> #include <efi_loader.h> #include <fm_eth.h> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 639e9d2ddc..339ff0c4c7 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -5,6 +5,7 @@ */ #include <common.h> +#include <fsl_immap.h> #include <fsl_ifc.h> #include <ahci.h> #include <scsi.h> @@ -285,7 +286,8 @@ static void erratum_a008850_early(void) { #ifdef CONFIG_SYS_FSL_ERRATUM_A008850 /* part 1 of 2 */ - struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR; + struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR + + CONFIG_SYS_CCI400_OFFSET); struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; /* Skip if running at lower exception level */ @@ -304,7 +306,8 @@ void erratum_a008850_post(void) { #ifdef CONFIG_SYS_FSL_ERRATUM_A008850 /* part 2 of 2 */ - struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR; + struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR + + CONFIG_SYS_CCI400_OFFSET); struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; u32 tmp; @@ -439,7 +442,8 @@ int setup_chip_volt(void) void fsl_lsch2_early_init_f(void) { - struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; + struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR + + CONFIG_SYS_CCI400_OFFSET); struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; #ifdef CONFIG_LAYERSCAPE_NS_ACCESS |