diff options
Diffstat (limited to 'arch/arm/cpu/tegra-common')
| -rw-r--r-- | arch/arm/cpu/tegra-common/Makefile | 2 | ||||
| -rw-r--r-- | arch/arm/cpu/tegra-common/ap.c | 53 | ||||
| -rw-r--r-- | arch/arm/cpu/tegra-common/cache.c | 48 | ||||
| -rw-r--r-- | arch/arm/cpu/tegra-common/clock.c | 3 |
4 files changed, 87 insertions, 19 deletions
diff --git a/arch/arm/cpu/tegra-common/Makefile b/arch/arm/cpu/tegra-common/Makefile index 8e95c7ee1d..4e0301c66a 100644 --- a/arch/arm/cpu/tegra-common/Makefile +++ b/arch/arm/cpu/tegra-common/Makefile @@ -28,7 +28,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)libcputegra-common.o SOBJS += lowlevel_init.o -COBJS-y += ap.o board.o sys_info.o timer.o clock.o +COBJS-y += ap.o board.o sys_info.o timer.o clock.o cache.o SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y)) diff --git a/arch/arm/cpu/tegra-common/ap.c b/arch/arm/cpu/tegra-common/ap.c index 236cda8419..9b77b2b82e 100644 --- a/arch/arm/cpu/tegra-common/ap.c +++ b/arch/arm/cpu/tegra-common/ap.c @@ -34,25 +34,44 @@ #include <asm/arch-tegra/tegra.h> #include <asm/arch-tegra/warmboot.h> -int tegra_get_chip_type(void) +int tegra_get_chip(void) { - struct apb_misc_gp_ctlr *gp; - struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE; - uint tegra_sku_id, rev; + int rev; + struct apb_misc_gp_ctlr *gp = + (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE; /* * This is undocumented, Chip ID is bits 15:8 of the register * APB_MISC + 0x804, and has value 0x20 for Tegra20, 0x30 for * Tegra30, and 0x35 for T114. */ - gp = (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE; rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT; + debug("%s: CHIPID is 0x%02X\n", __func__, rev); + + return rev; +} + +int tegra_get_sku_info(void) +{ + int sku_id; + struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE; - tegra_sku_id = readl(&fuse->sku_info) & 0xff; + sku_id = readl(&fuse->sku_info) & 0xff; + debug("%s: SKU info byte is 0x%02X\n", __func__, sku_id); - switch (rev) { + return sku_id; +} + +int tegra_get_chip_sku(void) +{ + uint sku_id, chip_id; + + chip_id = tegra_get_chip(); + sku_id = tegra_get_sku_info(); + + switch (chip_id) { case CHIPID_TEGRA20: - switch (tegra_sku_id) { + switch (sku_id) { case SKU_ID_T20: return TEGRA_SOC_T20; case SKU_ID_T25SE: @@ -64,19 +83,22 @@ int tegra_get_chip_type(void) } break; case CHIPID_TEGRA30: - switch (tegra_sku_id) { + switch (sku_id) { + case SKU_ID_T33: case SKU_ID_T30: return TEGRA_SOC_T30; } break; case CHIPID_TEGRA114: - switch (tegra_sku_id) { + switch (sku_id) { case SKU_ID_T114_ENG: return TEGRA_SOC_T114; } break; } - /* unknown sku id */ + /* unknown chip/sku id */ + printf("%s: ERROR: UNKNOWN CHIP/SKU ID COMBO (0x%02X/0x%02X)\n", + __func__, chip_id, sku_id); return TEGRA_SOC_UNKNOWN; } @@ -138,11 +160,6 @@ void s_init(void) enable_scu(); - /* enable SMP mode and FW for CPU0, by writing to Auxiliary Ctl reg */ - asm volatile( - "mrc p15, 0, r0, c1, c0, 1\n" - "orr r0, r0, #0x41\n" - "mcr p15, 0, r0, c1, c0, 1\n"); - - /* FIXME: should have SoC's L2 disabled too? */ + /* init the cache */ + config_cache(); } diff --git a/arch/arm/cpu/tegra-common/cache.c b/arch/arm/cpu/tegra-common/cache.c new file mode 100644 index 0000000000..48e9319c75 --- /dev/null +++ b/arch/arm/cpu/tegra-common/cache.c @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +/* Tegra cache routines */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch-tegra/ap.h> +#include <asm/arch/gp_padctrl.h> + +void config_cache(void) +{ + struct apb_misc_gp_ctlr *gp = + (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE; + u32 reg = 0; + + /* enable SMP mode and FW for CPU0, by writing to Auxiliary Ctl reg */ + asm volatile( + "mrc p15, 0, r0, c1, c0, 1\n" + "orr r0, r0, #0x41\n" + "mcr p15, 0, r0, c1, c0, 1\n"); + + /* Currently, only T114 needs this L2 cache change to boot Linux */ + reg = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK); + if (reg != (CHIPID_TEGRA114 << HIDREV_CHIPID_SHIFT)) + return; + /* + * Systems with an architectural L2 cache must not use the PL310. + * Config L2CTLR here for a data RAM latency of 3 cycles. + */ + asm("mrc p15, 1, %0, c9, c0, 2" : : "r" (reg)); + reg &= ~7; + reg |= 2; + asm("mcr p15, 1, %0, c9, c0, 2" : : "r" (reg)); +} diff --git a/arch/arm/cpu/tegra-common/clock.c b/arch/arm/cpu/tegra-common/clock.c index 49a06334cb..9156d009b2 100644 --- a/arch/arm/cpu/tegra-common/clock.c +++ b/arch/arm/cpu/tegra-common/clock.c @@ -557,4 +557,7 @@ void clock_init(void) debug("PLLP = %d\n", pll_rate[CLOCK_ID_PERIPH]); debug("PLLC = %d\n", pll_rate[CLOCK_ID_CGENERAL]); debug("PLLX = %d\n", pll_rate[CLOCK_ID_XCPU]); + + /* Do any special system timer/TSC setup */ + arch_timer_init(); } |