diff options
Diffstat (limited to 'arch/arm/cpu')
| -rw-r--r-- | arch/arm/cpu/armv7/ls102xa/Kconfig | 61 | ||||
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 87 |
2 files changed, 57 insertions, 91 deletions
diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index f94568a2e4..9ffb90eff9 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -1,10 +1,19 @@ config ARCH_LS1021A bool + select SYS_FSL_ERRATUM_A008378 + select SYS_FSL_ERRATUM_A008407 + select SYS_FSL_ERRATUM_A009663 + select SYS_FSL_ERRATUM_A009942 select SYS_FSL_ERRATUM_A010315 select SYS_FSL_SRDS_1 select SYS_HAS_SERDES - select SYS_FSL_DDR_BE - select SYS_FSL_DDR_VER_50 + select SYS_FSL_DDR_BE if SYS_FSL_DDR + select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR + select SYS_FSL_HAS_DDR3 if SYS_FSL_DDR + select SYS_FSL_HAS_DDR4 if SYS_FSL_DDR + select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_COMPAT_5 + select SYS_FSL_SEC_LE menu "LS102xA architecture" depends on ARCH_LS1021A @@ -24,10 +33,6 @@ config MAX_CPUS cores, count the reserved ports. This will allocate enough memory in spin table to properly handle all cores. -config NUM_DDR_CONTROLLERS - int "Maximum DDR controllers" - default 1 - config SECURE_BOOT bool "Secure Boot" help @@ -46,50 +51,12 @@ config SYS_FSL_SRDS_2 config SYS_HAS_SERDES bool -config SYS_FSL_DDR - bool "Freescale DDR driver" - help - Select Freescale General DDR driver, shared between most Freescale - PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM- - based Layerscape SoCs (such as ls2080a). - -config SYS_FSL_DDR_BE - bool - default y - help - Access DDR registers in big-endian. - -config SYS_FSL_DDR_VER - int - default 50 if SYS_FSL_DDR_VER_50 - -config SYS_FSL_DDR_VER_50 - bool - -config SYS_FSL_DDRC_ARM_GEN3 - bool - -config SYS_FSL_DDRC_GEN4 - bool - -config SYS_FSL_DDR3 - bool "Freescale DDR3 controller" - depends on !SYS_FSL_DDR4 - select SYS_FSL_DDR - select SYS_FSL_DDRC_ARM_GEN3 - help - Enable Freescale DDR3 controller on ARM-based SoCs. - -config SYS_FSL_DDR4 - bool "Freescale DDR4 controller" - select SYS_FSL_DDR - select SYS_FSL_DDRC_GEN4 - help - Enable Freescale DDR4 controller. - config SYS_FSL_IFC_BANK_COUNT int "Maximum banks of Integrated flash controller" depends on ARCH_LS1021A default 8 +config SYS_FSL_ERRATUM_A008407 + bool + endmenu diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index cc0dc889ae..de0b580e96 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -8,31 +8,62 @@ config ARCH_LS1012A config ARCH_LS1043A bool select FSL_LSCH2 + select SYS_FSL_DDR select SYS_FSL_DDR_BE select SYS_FSL_DDR_VER_50 + select SYS_FSL_ERRATUM_A008850 + select SYS_FSL_ERRATUM_A009660 + select SYS_FSL_ERRATUM_A009663 + select SYS_FSL_ERRATUM_A009929 + select SYS_FSL_ERRATUM_A009942 select SYS_FSL_ERRATUM_A010315 select SYS_FSL_ERRATUM_A010539 + select SYS_FSL_HAS_DDR3 + select SYS_FSL_HAS_DDR4 config ARCH_LS1046A bool select FSL_LSCH2 + select SYS_FSL_DDR select SYS_FSL_DDR_BE - select SYS_FSL_DDR4 select SYS_FSL_DDR_VER_50 + select SYS_FSL_ERRATUM_A008511 + select SYS_FSL_ERRATUM_A009801 + select SYS_FSL_ERRATUM_A009803 + select SYS_FSL_ERRATUM_A009942 + select SYS_FSL_ERRATUM_A010165 select SYS_FSL_ERRATUM_A010539 + select SYS_FSL_HAS_DDR4 select SYS_FSL_SRDS_2 config ARCH_LS2080A bool select FSL_LSCH3 - select SYS_FSL_DDR4 + select SYS_FSL_DDR select SYS_FSL_DDR_LE select SYS_FSL_DDR_VER_50 select SYS_FSL_HAS_DP_DDR + select SYS_FSL_HAS_SEC + select SYS_FSL_HAS_DDR4 + select SYS_FSL_SEC_COMPAT_5 + select SYS_FSL_SEC_LE select SYS_FSL_SRDS_2 + select SYS_FSL_ERRATUM_A008336 + select SYS_FSL_ERRATUM_A008511 + select SYS_FSL_ERRATUM_A008514 + select SYS_FSL_ERRATUM_A008585 + select SYS_FSL_ERRATUM_A009635 + select SYS_FSL_ERRATUM_A009663 + select SYS_FSL_ERRATUM_A009801 + select SYS_FSL_ERRATUM_A009803 + select SYS_FSL_ERRATUM_A009942 + select SYS_FSL_ERRATUM_A010165 config FSL_LSCH2 bool + select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_COMPAT_5 + select SYS_FSL_SEC_BE select SYS_FSL_SRDS_1 select SYS_HAS_SERDES @@ -65,9 +96,6 @@ config FSL_PPA_ARMV8_PSCI implemented under the common ARMv8 PSCI framework. endmenu -config SYS_FSL_MMDC - bool - config SYS_FSL_ERRATUM_A010315 bool "Workaround for PCIe erratum A010315" @@ -87,11 +115,6 @@ config MAX_CPUS cores, count the reserved ports. This will allocate enough memory in spin table to properly handle all cores. -config NUM_DDR_CONTROLLERS - int "Maximum DDR controllers" - default 3 if ARCH_LS2080A - default 1 - config SECURE_BOOT bool help @@ -123,49 +146,25 @@ config SYS_FSL_SRDS_2 config SYS_HAS_SERDES bool -config SYS_FSL_DDR - bool "Freescale DDR driver" - help - Select Freescale General DDR driver, shared between most Freescale - PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM- - based Layerscape SoCs (such as ls2080a). +endmenu -config SYS_FSL_DDR_BE +config SYS_FSL_ERRATUM_A008336 bool - help - Access DDR registers in big-endian. -config SYS_FSL_DDR_LE +config SYS_FSL_ERRATUM_A008514 bool - help - Access DDR registers in little-endian. - -config SYS_FSL_DDR_VER - int - default 50 if SYS_FSL_DDR_VER_50 -config SYS_FSL_DDR_VER_50 +config SYS_FSL_ERRATUM_A008585 bool -config SYS_FSL_DDRC_ARM_GEN3 +config SYS_FSL_ERRATUM_A008850 bool -config SYS_FSL_DDRC_GEN4 +config SYS_FSL_ERRATUM_A009635 bool -config SYS_FSL_DDR3 - bool "Freescale DDR3 controller" - depends on !SYS_FSL_DDR4 - select SYS_FSL_DDR - select SYS_FSL_DDRC_ARM_GEN3 - help - Enable Freescale DDR3 controller on ARM-based SoCs. - -config SYS_FSL_DDR4 - bool "Freescale DDR4 controller" - select SYS_FSL_DDR - select SYS_FSL_DDRC_GEN4 - help - Enable Freescale DDR4 controller. +config SYS_FSL_ERRATUM_A009660 + bool -endmenu +config SYS_FSL_ERRATUM_A009929 + bool |