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-rw-r--r--arch/arm/cpu/armv8/Kconfig7
-rw-r--r--arch/arm/cpu/armv8/psci.S26
2 files changed, 33 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
index c8bebabdf6..ff42791fb4 100644
--- a/arch/arm/cpu/armv8/Kconfig
+++ b/arch/arm/cpu/armv8/Kconfig
@@ -144,6 +144,13 @@ config ARMV8_PSCI_CPUS_PER_CLUSTER
A value 0 or no definition of it works for single cluster system.
System with multi-cluster should difine their own exact value.
+config ARMV8_EA_EL3_FIRST
+ bool "External aborts and SError interrupt exception are taken in EL3"
+ default n
+ help
+ Exception handling at all exception levels for External Abort and
+ SError interrupt exception are taken in EL3.
+
if SYS_HAS_ARMV8_SECURE_BASE
config ARMV8_SECURE_BASE
diff --git a/arch/arm/cpu/armv8/psci.S b/arch/arm/cpu/armv8/psci.S
index 097f91bace..358df8fee9 100644
--- a/arch/arm/cpu/armv8/psci.S
+++ b/arch/arm/cpu/armv8/psci.S
@@ -236,6 +236,28 @@ handle_sync:
b unhandled_exception
+#ifdef CONFIG_ARMV8_EA_EL3_FIRST
+/*
+ * Override this function if custom error handling is
+ * needed for asynchronous aborts
+ */
+ENTRY(plat_error_handler)
+ ret
+ENDPROC(plat_error_handler)
+.weak plat_error_handler
+
+handle_error:
+ bl psci_get_cpu_id
+ bl psci_get_cpu_stack_top
+ mov x9, #1
+ msr spsel, x9
+ mov sp, x0
+
+ bl plat_error_handler /* Platform specific error handling */
+deadloop:
+ b deadloop /* Never return */
+#endif
+
.align 11
.globl el3_exception_vectors
el3_exception_vectors:
@@ -261,7 +283,11 @@ el3_exception_vectors:
.align 7
b unhandled_exception /* FIQ, Lower EL using AArch64 */
.align 7
+#ifdef CONFIG_ARMV8_EA_EL3_FIRST
+ b handle_error /* SError, Lower EL using AArch64 */
+#else
b unhandled_exception /* SError, Lower EL using AArch64 */
+#endif
.align 7
b unhandled_exception /* Sync, Lower EL using AArch32 */
.align 7