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-rw-r--r--arch/arm/cpu/armv7/Kconfig19
-rw-r--r--arch/arm/cpu/armv7/mx7/Kconfig1
-rw-r--r--arch/arm/cpu/u-boot.lds4
3 files changed, 22 insertions, 2 deletions
diff --git a/arch/arm/cpu/armv7/Kconfig b/arch/arm/cpu/armv7/Kconfig
index 41c6639c13..b9c4f4e79b 100644
--- a/arch/arm/cpu/armv7/Kconfig
+++ b/arch/arm/cpu/armv7/Kconfig
@@ -6,6 +6,9 @@ config CPU_V7_HAS_NONSEC
config CPU_V7_HAS_VIRT
bool
+config ARCH_SUPPORT_PSCI
+ bool
+
config ARMV7_NONSEC
bool "Enable support for booting in non-secure mode" if EXPERT
depends on CPU_V7_HAS_NONSEC
@@ -31,6 +34,22 @@ config ARMV7_VIRT
---help---
Say Y here to boot in hypervisor (HYP) mode when booting non-secure.
+config ARMV7_PSCI
+ bool "Enable PSCI support" if EXPERT
+ depends on ARMV7_NONSEC && ARCH_SUPPORT_PSCI
+ default y
+ help
+ Say Y here to enable PSCI support.
+
+config ARMV7_PSCI_NR_CPUS
+ int "Maximum supported CPUs for PSCI"
+ depends on ARMV7_NONSEC
+ default 4
+ help
+ The maximum number of CPUs supported in the PSCI firmware.
+ It is no problem to set a larger value than the number of
+ CPUs in the actual hardware implementation.
+
config ARMV7_LPAE
bool "Use LPAE page table format" if EXPERT
depends on CPU_V7
diff --git a/arch/arm/cpu/armv7/mx7/Kconfig b/arch/arm/cpu/armv7/mx7/Kconfig
index 5fdc8dd583..fb00b8c67c 100644
--- a/arch/arm/cpu/armv7/mx7/Kconfig
+++ b/arch/arm/cpu/armv7/mx7/Kconfig
@@ -5,6 +5,7 @@ config MX7
select ROM_UNIFIED_SECTIONS
select CPU_V7_HAS_VIRT
select CPU_V7_HAS_NONSEC
+ select ARCH_SUPPORT_PSCI
default y
config MX7D
diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds
index 36c9fd0bd0..0a5fae6efc 100644
--- a/arch/arm/cpu/u-boot.lds
+++ b/arch/arm/cpu/u-boot.lds
@@ -83,10 +83,10 @@ SECTIONS
#endif
{
KEEP(*(.__secure_stack_start))
-
+#ifdef CONFIG_ARMV7_PSCI
/* Skip addreses for stack */
. = . + CONFIG_ARMV7_PSCI_NR_CPUS * ARM_PSCI_STACK_SIZE;
-
+#endif
/* Align end of stack section to page boundary */
. = ALIGN(CONSTANT(COMMONPAGESIZE));