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-rw-r--r--arch/arm/cpu/armv7/start.S6
-rw-r--r--arch/arm/cpu/armv7/vf610/generic.c2
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/soc.c2
3 files changed, 8 insertions, 2 deletions
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index f06fd28940..7b84a7a0f1 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -187,6 +187,12 @@ ENTRY(cpu_init_cp15)
mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
#endif
+#ifdef CONFIG_ARM_ERRATA_845369
+ mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
+ orr r0, r0, #1 << 22 @ set bit #22
+ mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
+#endif
+
mov r5, lr @ Store my Caller
mrc p15, 0, r1, c0, c0, 0 @ r1 has Read Main ID Register (MIDR)
mov r3, r1, lsr #20 @ get variant field
diff --git a/arch/arm/cpu/armv7/vf610/generic.c b/arch/arm/cpu/armv7/vf610/generic.c
index ac2d8d1a3f..88f3f4dd16 100644
--- a/arch/arm/cpu/armv7/vf610/generic.c
+++ b/arch/arm/cpu/armv7/vf610/generic.c
@@ -329,7 +329,7 @@ int arch_misc_init(void)
strcpy(soc, "vf");
strcat(soc, soc_type);
- setenv("soc", soc);
+ env_set("soc", soc);
return 0;
}
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index aee1ffa7d4..639e9d2ddc 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -95,7 +95,7 @@ static void erratum_a008514(void)
static unsigned long get_internval_val_mhz(void)
{
- char *interval = getenv(PLATFORM_CYCLE_ENV_VAR);
+ char *interval = env_get(PLATFORM_CYCLE_ENV_VAR);
/*
* interval is the number of platform cycles(MHz) between
* wake up events generated by EPU.