diff options
Diffstat (limited to 'arch/arm/cpu')
| -rw-r--r-- | arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c | 14 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/start.S | 15 | ||||
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/mp.c | 8 | ||||
| -rw-r--r-- | arch/arm/cpu/armv8/zynqmp/mp.c | 8 |
4 files changed, 28 insertions, 17 deletions
diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c index 8fef4019af..7818d72908 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c @@ -15,7 +15,7 @@ #include "mxs_init.h" -static uint32_t dram_vals[] = { +__weak uint32_t mxs_dram_vals[] = { /* * i.MX28 DDR2 at 200MHz */ @@ -100,11 +100,11 @@ static void initialize_dram_values(void) int i; debug("SPL: Setting mx28 board specific SDRAM parameters\n"); - mxs_adjust_memory_params(dram_vals); + mxs_adjust_memory_params(mxs_dram_vals); debug("SPL: Applying SDRAM parameters\n"); - for (i = 0; i < ARRAY_SIZE(dram_vals); i++) - writel(dram_vals[i], MXS_DRAM_BASE + (4 * i)); + for (i = 0; i < ARRAY_SIZE(mxs_dram_vals); i++) + writel(mxs_dram_vals[i], MXS_DRAM_BASE + (4 * i)); } #else static void initialize_dram_values(void) @@ -112,7 +112,7 @@ static void initialize_dram_values(void) int i; debug("SPL: Setting mx23 board specific SDRAM parameters\n"); - mxs_adjust_memory_params(dram_vals); + mxs_adjust_memory_params(mxs_dram_vals); /* * HW_DRAM_CTL27, HW_DRAM_CTL28 and HW_DRAM_CTL35 are not initialized as @@ -124,10 +124,10 @@ static void initialize_dram_values(void) * So skip the initialization of these HW_DRAM_CTL registers. */ debug("SPL: Applying SDRAM parameters\n"); - for (i = 0; i < ARRAY_SIZE(dram_vals); i++) { + for (i = 0; i < ARRAY_SIZE(mxs_dram_vals); i++) { if (i == 8 || i == 27 || i == 28 || i == 35) continue; - writel(dram_vals[i], MXS_DRAM_BASE + (4 * i)); + writel(mxs_dram_vals[i], MXS_DRAM_BASE + (4 * i)); } /* diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index c996525f86..81edec01bf 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -241,6 +241,14 @@ skip_errata_798870: skip_errata_801819: #endif +#ifdef CONFIG_ARM_CORTEX_A15_CVE_2017_5715 + mrc p15, 0, r0, c1, c0, 1 @ read auxilary control register + orr r0, r0, #1 << 0 @ Enable invalidates of BTB + push {r1-r5} @ Save the cpu info registers + bl v7_arch_cp15_set_acr + pop {r1-r5} @ Restore the cpu info - fall through +#endif + #ifdef CONFIG_ARM_ERRATA_454179 mrc p15, 0, r0, c1, c0, 1 @ Read ACR @@ -252,12 +260,15 @@ skip_errata_801819: pop {r1-r5} @ Restore the cpu info - fall through #endif -#ifdef CONFIG_ARM_ERRATA_430973 +#if defined(CONFIG_ARM_ERRATA_430973) || defined (CONFIG_ARM_CORTEX_A8_CVE_2017_5715) mrc p15, 0, r0, c1, c0, 1 @ Read ACR +#ifdef CONFIG_ARM_CORTEX_A8_CVE_2017_5715 + orr r0, r0, #(0x1 << 6) @ Set IBE bit always to enable OS WA +#else cmp r2, #0x21 @ Only on < r2p1 orrlt r0, r0, #(0x1 << 6) @ Set IBE bit - +#endif push {r1-r5} @ Save the cpu info registers bl v7_arch_cp15_set_acr pop {r1-r5} @ Restore the cpu info - fall through diff --git a/arch/arm/cpu/armv8/fsl-layerscape/mp.c b/arch/arm/cpu/armv8/fsl-layerscape/mp.c index dd89d0a83f..7627fd13e7 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/mp.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/mp.c @@ -191,14 +191,14 @@ int is_core_online(u64 cpu_id) return table[SPIN_TABLE_ELEM_STATUS_IDX] == 1; } -int cpu_reset(int nr) +int cpu_reset(u32 nr) { puts("Feature is not implemented.\n"); return 0; } -int cpu_disable(int nr) +int cpu_disable(u32 nr) { puts("Feature is not implemented.\n"); @@ -231,7 +231,7 @@ static int core_to_pos(int nr) return i; } -int cpu_status(int nr) +int cpu_status(u32 nr) { u64 *table; int pos; @@ -257,7 +257,7 @@ int cpu_status(int nr) return 0; } -int cpu_release(int nr, int argc, char * const argv[]) +int cpu_release(u32 nr, int argc, char * const argv[]) { u64 boot_addr; u64 *table = (u64 *)get_spin_tbl_addr(); diff --git a/arch/arm/cpu/armv8/zynqmp/mp.c b/arch/arm/cpu/armv8/zynqmp/mp.c index 7e270a7dc2..2a71870ae7 100644 --- a/arch/arm/cpu/armv8/zynqmp/mp.c +++ b/arch/arm/cpu/armv8/zynqmp/mp.c @@ -45,7 +45,7 @@ int is_core_valid(unsigned int core) return 0; } -int cpu_reset(int nr) +int cpu_reset(u32 nr) { puts("Feature is not implemented.\n"); return 0; @@ -131,7 +131,7 @@ static void enable_clock_r5(void) udelay(0x500); } -int cpu_disable(int nr) +int cpu_disable(u32 nr) { if (nr >= ZYNQMP_CORE_APU0 && nr <= ZYNQMP_CORE_APU3) { u32 val = readl(&crfapb_base->rst_fpd_apu); @@ -144,7 +144,7 @@ int cpu_disable(int nr) return 0; } -int cpu_status(int nr) +int cpu_status(u32 nr) { if (nr >= ZYNQMP_CORE_APU0 && nr <= ZYNQMP_CORE_APU3) { u32 addr_low = readl(((u8 *)&apu_base->rvbar_addr0_l) + nr * 8); @@ -220,7 +220,7 @@ void initialize_tcm(bool mode) } } -int cpu_release(int nr, int argc, char * const argv[]) +int cpu_release(u32 nr, int argc, char * const argv[]) { if (nr >= ZYNQMP_CORE_APU0 && nr <= ZYNQMP_CORE_APU3) { u64 boot_addr = simple_strtoull(argv[0], NULL, 16); |