diff options
Diffstat (limited to 'arch/arm/cpu')
23 files changed, 354 insertions, 107 deletions
diff --git a/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg new file mode 100644 index 0000000000..811876736c --- /dev/null +++ b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg @@ -0,0 +1,6 @@ +SECTION 0x0 BOOTABLE + TAG LAST + LOAD 0x0 spl/u-boot-spl.bin + CALL 0x14 0x0 + LOAD 0x40000100 u-boot.bin + CALL 0x40000100 0x0 diff --git a/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg new file mode 100644 index 0000000000..ea772f0c86 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg @@ -0,0 +1,8 @@ +SECTION 0x0 BOOTABLE + TAG LAST + LOAD 0x0 spl/u-boot-spl.bin + LOAD IVT 0x8000 0x14 + CALL HAB 0x8000 0x0 + LOAD 0x40000100 u-boot.bin + LOAD IVT 0x8000 0x40000100 + CALL HAB 0x8000 0x0 diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c index e3b6cd95f9..f357959059 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c @@ -36,7 +36,7 @@ static void mxs_power_clock2pll(void) CLKCTRL_CLKSEQ_BYPASS_CPU); } -static void mxs_power_clear_auto_restart(void) +static void mxs_power_set_auto_restart(void) { struct mxs_rtc_regs *rtc_regs = (struct mxs_rtc_regs *)MXS_RTC_BASE; @@ -49,10 +49,7 @@ static void mxs_power_clear_auto_restart(void) while (readl(&rtc_regs->hw_rtc_ctrl) & RTC_CTRL_CLKGATE) ; - /* - * Due to the hardware design bug of mx28 EVK-A - * we need to set the AUTO_RESTART bit. - */ + /* Do nothing if flag already set */ if (readl(&rtc_regs->hw_rtc_persistent0) & RTC_PERSISTENT0_AUTO_RESTART) return; @@ -911,7 +908,7 @@ void mxs_power_init(void) mxs_ungate_power(); mxs_power_clock2xtal(); - mxs_power_clear_auto_restart(); + mxs_power_set_auto_restart(); mxs_power_set_linreg(); mxs_power_setup_5v_detect(); diff --git a/arch/arm/cpu/armv7/at91/sama5d3_devices.c b/arch/arm/cpu/armv7/at91/sama5d3_devices.c index 4a3fca56a1..e55e1c6602 100644 --- a/arch/arm/cpu/armv7/at91/sama5d3_devices.c +++ b/arch/arm/cpu/armv7/at91/sama5d3_devices.c @@ -144,6 +144,30 @@ void at91_macb_hw_init(void) /* Enable clock */ at91_periph_clk_enable(ATMEL_ID_EMAC); } + +void at91_gmac_hw_init(void) +{ + at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* GTX0 */ + at91_set_a_periph(AT91_PIO_PORTB, 1, 0); /* GTX1 */ + at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* GTX2 */ + at91_set_a_periph(AT91_PIO_PORTB, 3, 0); /* GTX3 */ + at91_set_a_periph(AT91_PIO_PORTB, 4, 0); /* GRX0 */ + at91_set_a_periph(AT91_PIO_PORTB, 5, 0); /* GRX1 */ + at91_set_a_periph(AT91_PIO_PORTB, 6, 0); /* GRX2 */ + at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* GRX3 */ + at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* GTXCK */ + at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* GTXEN */ + + at91_set_a_periph(AT91_PIO_PORTB, 11, 0); /* GRXCK */ + at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* GRXER */ + + at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* GMDC */ + at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* GMDIO */ + at91_set_a_periph(AT91_PIO_PORTB, 18, 0); /* G125CK */ + + /* Enable clock */ + at91_periph_clk_enable(ATMEL_ID_GMAC); +} #endif #ifdef CONFIG_LCD diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c index fbbb365cb6..6bef254456 100644 --- a/arch/arm/cpu/armv7/mx5/clock.c +++ b/arch/arm/cpu/armv7/mx5/clock.c @@ -85,7 +85,7 @@ void set_usboh3_clk(void) MXC_CCM_CSCDR1_USBOH3_CLK_PODF(1)); } -void enable_usboh3_clk(unsigned char enable) +void enable_usboh3_clk(bool enable) { unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF; @@ -122,7 +122,7 @@ void set_usb_phy_clk(void) } #if defined(CONFIG_MX51) -void enable_usb_phy1_clk(unsigned char enable) +void enable_usb_phy1_clk(bool enable) { unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF; @@ -131,12 +131,12 @@ void enable_usb_phy1_clk(unsigned char enable) MXC_CCM_CCGR2_USB_PHY(cg)); } -void enable_usb_phy2_clk(unsigned char enable) +void enable_usb_phy2_clk(bool enable) { /* i.MX51 has a single USB PHY clock, so do nothing here. */ } #elif defined(CONFIG_MX53) -void enable_usb_phy1_clk(unsigned char enable) +void enable_usb_phy1_clk(bool enable) { unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF; @@ -145,7 +145,7 @@ void enable_usb_phy1_clk(unsigned char enable) MXC_CCM_CCGR4_USB_PHY1(cg)); } -void enable_usb_phy2_clk(unsigned char enable) +void enable_usb_phy2_clk(bool enable) { unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF; diff --git a/arch/arm/cpu/armv7/mx6/Makefile b/arch/arm/cpu/armv7/mx6/Makefile index c5e98582d0..6d736174db 100644 --- a/arch/arm/cpu/armv7/mx6/Makefile +++ b/arch/arm/cpu/armv7/mx6/Makefile @@ -11,10 +11,11 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).o -COBJS = soc.o clock.o +COBJS-y = soc.o clock.o +COBJS-$(CONFIG_SECURE_BOOT) += hab.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y)) all: $(obj).depend $(LIB) diff --git a/arch/arm/cpu/armv7/mx6/hab.c b/arch/arm/cpu/armv7/mx6/hab.c new file mode 100644 index 0000000000..5187775365 --- /dev/null +++ b/arch/arm/cpu/armv7/mx6/hab.c @@ -0,0 +1,104 @@ +/* + * Copyright (C) 2010-2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/hab.h> + +/* -------- start of HAB API updates ------------*/ +#define hab_rvt_report_event ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT) +#define hab_rvt_report_status ((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS) +#define hab_rvt_authenticate_image \ + ((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE) +#define hab_rvt_entry ((hab_rvt_entry_t *)HAB_RVT_ENTRY) +#define hab_rvt_exit ((hab_rvt_exit_t *)HAB_RVT_EXIT) +#define hab_rvt_clock_init HAB_RVT_CLOCK_INIT + +bool is_hab_enabled(void) +{ + struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; + struct fuse_bank *bank = &ocotp->bank[0]; + struct fuse_bank0_regs *fuse = + (struct fuse_bank0_regs *)bank->fuse_regs; + uint32_t reg = readl(&fuse->cfg5); + + return (reg & 0x2) == 0x2; +} + +void display_event(uint8_t *event_data, size_t bytes) +{ + uint32_t i; + + if (!(event_data && bytes > 0)) + return; + + for (i = 0; i < bytes; i++) { + if (i == 0) + printf("\t0x%02x", event_data[i]); + else if ((i % 8) == 0) + printf("\n\t0x%02x", event_data[i]); + else + printf(" 0x%02x", event_data[i]); + } +} + +int get_hab_status(void) +{ + uint32_t index = 0; /* Loop index */ + uint8_t event_data[128]; /* Event data buffer */ + size_t bytes = sizeof(event_data); /* Event size in bytes */ + enum hab_config config = 0; + enum hab_state state = 0; + + if (is_hab_enabled()) + puts("\nSecure boot enabled\n"); + else + puts("\nSecure boot disabled\n"); + + /* Check HAB status */ + if (hab_rvt_report_status(&config, &state) != HAB_SUCCESS) { + printf("\nHAB Configuration: 0x%02x, HAB State: 0x%02x\n", + config, state); + + /* Display HAB Error events */ + while (hab_rvt_report_event(HAB_FAILURE, index, event_data, + &bytes) == HAB_SUCCESS) { + puts("\n"); + printf("--------- HAB Event %d -----------------\n", + index + 1); + puts("event data:\n"); + display_event(event_data, bytes); + puts("\n"); + bytes = sizeof(event_data); + index++; + } + } + /* Display message if no HAB events are found */ + else { + printf("\nHAB Configuration: 0x%02x, HAB State: 0x%02x\n", + config, state); + puts("No HAB Events Found!\n\n"); + } + return 0; +} + +int do_hab_status(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + if ((argc != 1)) { + cmd_usage(cmdtp); + return 1; + } + + get_hab_status(); + + return 0; +} + +U_BOOT_CMD( + hab_status, CONFIG_SYS_MAXARGS, 1, do_hab_status, + "display HAB status", + "" + ); diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 8150bffb8c..a3902962b5 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -213,6 +213,34 @@ const struct boot_mode soc_boot_modes[] = { void s_init(void) { + struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; + int is_6q = is_cpu_type(MXC_CPU_MX6Q); + u32 mask480; + u32 mask528; + + /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs + * to make sure PFD is working right, otherwise, PFDs may + * not output clock after reset, MX6DL and MX6SL have added 396M pfd + * workaround in ROM code, as bus clock need it + */ + + mask480 = ANATOP_PFD_CLKGATE_MASK(0) | + ANATOP_PFD_CLKGATE_MASK(1) | + ANATOP_PFD_CLKGATE_MASK(2) | + ANATOP_PFD_CLKGATE_MASK(3); + mask528 = ANATOP_PFD_CLKGATE_MASK(0) | + ANATOP_PFD_CLKGATE_MASK(1) | + ANATOP_PFD_CLKGATE_MASK(3); + + /* + * Don't reset PFD2 on DL/S + */ + if (is_6q) + mask528 |= ANATOP_PFD_CLKGATE_MASK(2); + writel(mask480, &anatop->pfd_480_set); + writel(mask528, &anatop->pfd_528_set); + writel(mask480, &anatop->pfd_480_clr); + writel(mask528, &anatop->pfd_528_clr); } #ifdef CONFIG_IMX_HDMI diff --git a/arch/arm/cpu/armv7/omap3/clock.c b/arch/arm/cpu/armv7/omap3/clock.c index e903ed9ac4..9f989ff860 100644 --- a/arch/arm/cpu/armv7/omap3/clock.c +++ b/arch/arm/cpu/armv7/omap3/clock.c @@ -183,8 +183,7 @@ static void dpll3_init_34xx(u32 sil_index, u32 clk_index) * if running from flash, jump to small relocated code * area in SRAM. */ - f_lock_pll = (void *) ((u32) &_end_vect - (u32) &_start + - SRAM_VECT_CODE); + f_lock_pll = (void *) (SRAM_CLK_CODE); p0 = readl(&prcm_base->clken_pll); sr32(&p0, 0, 3, PLL_FAST_RELOCK_BYPASS); @@ -401,8 +400,7 @@ static void dpll3_init_36xx(u32 sil_index, u32 clk_index) * if running from flash, jump to small relocated code * area in SRAM. */ - f_lock_pll = (void *) ((u32) &_end_vect - (u32) &_start + - SRAM_VECT_CODE); + f_lock_pll = (void *) (SRAM_CLK_CODE); p0 = readl(&prcm_base->clken_pll); sr32(&p0, 0, 3, PLL_FAST_RELOCK_BYPASS); diff --git a/arch/arm/cpu/armv7/omap3/lowlevel_init.S b/arch/arm/cpu/armv7/omap3/lowlevel_init.S index 98c3c03a0e..6f7261b7b8 100644 --- a/arch/arm/cpu/armv7/omap3/lowlevel_init.S +++ b/arch/arm/cpu/armv7/omap3/lowlevel_init.S @@ -69,15 +69,13 @@ ENDPROC(do_omap3_emu_romcode_call) *************************************************************************/ ENTRY(cpy_clk_code) /* Copy DPLL code into SRAM */ - adr r0, go_to_speed /* get addr of clock setting code */ - mov r2, #384 /* r2 size to copy (div by 32 bytes) */ - mov r1, r1 /* r1 <- dest address (passed in) */ - add r2, r2, r0 /* r2 <- source end address */ + adr r0, go_to_speed /* copy from start of go_to_speed... */ + adr r2, lowlevel_init /* ... up to start of low_level_init */ next2: ldmia r0!, {r3 - r10} /* copy from source address [r0] */ stmia r1!, {r3 - r10} /* copy to target address [r1] */ cmp r0, r2 /* until source end address [r2] */ - bne next2 + blo next2 mov pc, lr /* back to caller */ ENDPROC(cpy_clk_code) diff --git a/arch/arm/cpu/armv7/omap4/hw_data.c b/arch/arm/cpu/armv7/omap4/hw_data.c index 310df5a6e2..6a225c8cb2 100644 --- a/arch/arm/cpu/armv7/omap4/hw_data.c +++ b/arch/arm/cpu/armv7/omap4/hw_data.c @@ -50,6 +50,7 @@ static const struct dpll_params mpu_dpll_params_1400mhz[NUM_SYS_CLKS] = { /* * dpll locked at 1600 MHz - MPU clk at 800 MHz(OPP Turbo 4430) * OMAP4430 OPP_TURBO frequency + * OMAP4470 OPP_NOM frequency */ static const struct dpll_params mpu_dpll_params_1600mhz[NUM_SYS_CLKS] = { {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ @@ -76,6 +77,7 @@ static const struct dpll_params mpu_dpll_params_1200mhz[NUM_SYS_CLKS] = { }; /* OMAP4460 OPP_NOM frequency */ +/* OMAP4470 OPP_NOM (Low Power) frequency */ static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = { {200, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */ {800, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */ @@ -198,6 +200,20 @@ struct dplls omap4460_dplls = { .ddr = NULL }; +struct dplls omap4470_dplls = { + .mpu = mpu_dpll_params_1600mhz, + .core = core_dpll_params_1600mhz, + .per = per_dpll_params_1536mhz, + .iva = iva_dpll_params_1862mhz, +#ifdef CONFIG_SYS_OMAP_ABE_SYSCK + .abe = abe_dpll_params_sysclk_196608khz, +#else + .abe = &abe_dpll_params_32k_196608khz, +#endif + .usb = usb_dpll_params_1920mhz, + .ddr = NULL +}; + struct pmic_data twl6030_4430es1 = { .base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV, .step = 12660, /* 12.66 mV represented in uV */ @@ -208,6 +224,7 @@ struct pmic_data twl6030_4430es1 = { .pmic_write = omap_vc_bypass_send_value, }; +/* twl6030 struct is used for TWL6030 and TWL6032 PMIC */ struct pmic_data twl6030 = { .base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV, .step = 12660, /* 12.66 mV represented in uV */ @@ -271,6 +288,20 @@ struct vcores_data omap4460_volts = { .mm.pmic = &twl6030, }; +struct vcores_data omap4470_volts = { + .mpu.value = 1200, + .mpu.addr = SMPS_REG_ADDR_SMPS1, + .mpu.pmic = &twl6030, + + .core.value = 1126, + .core.addr = SMPS_REG_ADDR_SMPS1, + .core.pmic = &twl6030, + + .mm.value = 1137, + .mm.addr = SMPS_REG_ADDR_SMPS1, + .mm.pmic = &twl6030, +}; + /* * Enable essential clock domains, modules and * do some additional special settings needed @@ -476,6 +507,11 @@ void hw_data_init(void) *omap_vcores = &omap4460_volts; break; + case OMAP4470_ES1_0: + *dplls_data = &omap4470_dplls; + *omap_vcores = &omap4470_volts; + break; + default: printf("\n INVALID OMAP REVISION "); } diff --git a/arch/arm/cpu/armv7/omap4/hwinit.c b/arch/arm/cpu/armv7/omap4/hwinit.c index 4da0fc0ad5..b0598a0774 100644 --- a/arch/arm/cpu/armv7/omap4/hwinit.c +++ b/arch/arm/cpu/armv7/omap4/hwinit.c @@ -138,6 +138,9 @@ void init_omap_revision(void) break; case MIDR_CORTEX_A9_R2P10: switch (readl(CONTROL_ID_CODE)) { + case OMAP4470_CONTROL_ID_CODE_ES1_0: + *omap_si_rev = OMAP4470_ES1_0; + break; case OMAP4460_CONTROL_ID_CODE_ES1_1: *omap_si_rev = OMAP4460_ES1_1; break; diff --git a/arch/arm/cpu/armv7/omap4/sdram_elpida.c b/arch/arm/cpu/armv7/omap4/sdram_elpida.c index d76dde719a..67a79261f7 100644 --- a/arch/arm/cpu/armv7/omap4/sdram_elpida.c +++ b/arch/arm/cpu/armv7/omap4/sdram_elpida.c @@ -60,6 +60,20 @@ static const struct emif_regs emif_regs_elpida_380_mhz_1cs = { .emif_ddr_phy_ctlr_1 = 0x049ff418 }; +const struct emif_regs emif_regs_elpida_400_mhz_1cs = { + .sdram_config_init = 0x80800eb2, + .sdram_config = 0x80801ab2, + .ref_ctrl = 0x00000618, + .sdram_tim1 = 0x10eb0662, + .sdram_tim2 = 0x20370dd2, + .sdram_tim3 = 0x00b1c33f, + .read_idle_ctrl = 0x000501ff, + .zq_config = 0x500b3215, + .temp_alert_config = 0x58016893, + .emif_ddr_phy_ctlr_1_init = 0x049ffff5, + .emif_ddr_phy_ctlr_1 = 0x049ff418 +}; + const struct emif_regs emif_regs_elpida_400_mhz_2cs = { .sdram_config_init = 0x80000eb9, .sdram_config = 0x80001ab9, @@ -107,8 +121,10 @@ static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs) *regs = &emif_regs_elpida_380_mhz_1cs; else if (omap4_rev == OMAP4430_ES2_0) *regs = &emif_regs_elpida_200_mhz_2cs; - else + else if (omap4_rev < OMAP4470_ES1_0) *regs = &emif_regs_elpida_400_mhz_2cs; + else + *regs = &emif_regs_elpida_400_mhz_1cs; } void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) __attribute__((weak, alias("emif_get_reg_dump_sdp"))); @@ -138,20 +154,31 @@ static const struct lpddr2_device_details elpida_2G_S4_details = { .manufacturer = LPDDR2_MANUFACTURER_ELPIDA }; +static const struct lpddr2_device_details elpida_4G_S4_details = { + .type = LPDDR2_TYPE_S4, + .density = LPDDR2_DENSITY_4Gb, + .io_width = LPDDR2_IO_WIDTH_32, + .manufacturer = LPDDR2_MANUFACTURER_ELPIDA +}; + struct lpddr2_device_details *emif_get_device_details_sdp(u32 emif_nr, u8 cs, struct lpddr2_device_details *lpddr2_dev_details) { u32 omap_rev = omap_revision(); /* EMIF1 & EMIF2 have identical configuration */ - if ((omap_rev == OMAP4430_ES1_0) && (cs == CS1)) { - /* Nothing connected on CS1 for ES1.0 */ + if (((omap_rev == OMAP4430_ES1_0) || (omap_rev == OMAP4470_ES1_0)) + && (cs == CS1)) { + /* Nothing connected on CS1 for 4430/4470 ES1.0 */ return NULL; - } else { - /* In all other cases Elpida 2G device */ + } else if (omap_rev < OMAP4470_ES1_0) { + /* In all other 4430/4460 cases Elpida 2G device */ *lpddr2_dev_details = elpida_2G_S4_details; - return lpddr2_dev_details; + } else { + /* 4470: 4G device */ + *lpddr2_dev_details = elpida_4G_S4_details; } + return lpddr2_dev_details; } struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs, @@ -265,7 +292,7 @@ void emif_get_device_timings_sdp(u32 emif_nr, /* Identical devices on EMIF1 & EMIF2 */ *cs0_device_timings = &elpida_2G_S4_timings; - if (omap_rev == OMAP4430_ES1_0) + if ((omap_rev == OMAP4430_ES1_0) || (omap_rev == OMAP4470_ES1_0)) *cs1_device_timings = NULL; else *cs1_device_timings = &elpida_2G_S4_timings; diff --git a/arch/arm/cpu/armv7/socfpga/Makefile b/arch/arm/cpu/armv7/socfpga/Makefile index 3b48ac9b2b..5024fc55e2 100644 --- a/arch/arm/cpu/armv7/socfpga/Makefile +++ b/arch/arm/cpu/armv7/socfpga/Makefile @@ -13,7 +13,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).o SOBJS := lowlevel_init.o -COBJS-y := misc.o timer.o +COBJS-y := misc.o timer.o reset_manager.o COBJS-$(CONFIG_SPL_BUILD) += spl.o COBJS := $(COBJS-y) diff --git a/arch/arm/cpu/armv7/socfpga/misc.c b/arch/arm/cpu/armv7/socfpga/misc.c index 66edb3c20f..2f1c7160f1 100644 --- a/arch/arm/cpu/armv7/socfpga/misc.c +++ b/arch/arm/cpu/armv7/socfpga/misc.c @@ -6,36 +6,9 @@ #include <common.h> #include <asm/io.h> -#include <asm/arch/reset_manager.h> DECLARE_GLOBAL_DATA_PTR; -static const struct socfpga_reset_manager *reset_manager_base = - (void *)SOCFPGA_RSTMGR_ADDRESS; - -/* - * Write the reset manager register to cause reset - */ -void reset_cpu(ulong addr) -{ - /* request a warm reset */ - writel(RSTMGR_CTRL_SWWARMRSTREQ_LSB, &reset_manager_base->ctrl); - /* - * infinite loop here as watchdog will trigger and reset - * the processor - */ - while (1) - ; -} - -/* - * Release peripherals from reset based on handoff - */ -void reset_deassert_peripherals_handoff(void) -{ - writel(0, &reset_manager_base->per_mod_reset); -} - int dram_init(void) { gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); diff --git a/arch/arm/cpu/armv7/socfpga/reset_manager.c b/arch/arm/cpu/armv7/socfpga/reset_manager.c new file mode 100644 index 0000000000..e320c011ae --- /dev/null +++ b/arch/arm/cpu/armv7/socfpga/reset_manager.c @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2013 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/reset_manager.h> + +DECLARE_GLOBAL_DATA_PTR; + +static const struct socfpga_reset_manager *reset_manager_base = + (void *)SOCFPGA_RSTMGR_ADDRESS; + +/* + * Write the reset manager register to cause reset + */ +void reset_cpu(ulong addr) +{ + /* request a warm reset */ + writel((1 << RSTMGR_CTRL_SWWARMRSTREQ_LSB), + &reset_manager_base->ctrl); + /* + * infinite loop here as watchdog will trigger and reset + * the processor + */ + while (1) + ; +} + +/* + * Release peripherals from reset based on handoff + */ +void reset_deassert_peripherals_handoff(void) +{ + writel(0, &reset_manager_base->per_mod_reset); +} diff --git a/arch/arm/cpu/armv7/tegra114/config.mk b/arch/arm/cpu/armv7/tegra114/config.mk deleted file mode 100644 index cb1a19da82..0000000000 --- a/arch/arm/cpu/armv7/tegra114/config.mk +++ /dev/null @@ -1,19 +0,0 @@ -# -# Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. -# -# (C) Copyright 2002 -# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> -# -# This program is free software; you can redistribute it and/or modify it -# under the terms and conditions of the GNU General Public License, -# version 2, as published by the Free Software Foundation. -# -# This program is distributed in the hope it will be useful, but WITHOUT -# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -# more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see <http://www.gnu.org/licenses/>. -# -CONFIG_ARCH_DEVICE_TREE := tegra114 diff --git a/arch/arm/cpu/armv7/tegra20/config.mk b/arch/arm/cpu/armv7/tegra20/config.mk deleted file mode 100644 index 3cac79bc1b..0000000000 --- a/arch/arm/cpu/armv7/tegra20/config.mk +++ /dev/null @@ -1,10 +0,0 @@ -# -# (C) Copyright 2010,2011 -# NVIDIA Corporation <www.nvidia.com> -# -# (C) Copyright 2002 -# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> -# -# SPDX-License-Identifier: GPL-2.0+ -# -CONFIG_ARCH_DEVICE_TREE := tegra20 diff --git a/arch/arm/cpu/armv7/tegra30/config.mk b/arch/arm/cpu/armv7/tegra30/config.mk deleted file mode 100644 index 719ca8192e..0000000000 --- a/arch/arm/cpu/armv7/tegra30/config.mk +++ /dev/null @@ -1,19 +0,0 @@ -# -# Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. -# -# (C) Copyright 2002 -# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> -# -# This program is free software; you can redistribute it and/or modify it -# under the terms and conditions of the GNU General Public License, -# version 2, as published by the Free Software Foundation. -# -# This program is distributed in the hope it will be useful, but WITHOUT -# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -# more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see <http://www.gnu.org/licenses/>. -# -CONFIG_ARCH_DEVICE_TREE := tegra30 diff --git a/arch/arm/cpu/armv7/zynq/Makefile b/arch/arm/cpu/armv7/zynq/Makefile index e5494f7489..de6b08157e 100644 --- a/arch/arm/cpu/armv7/zynq/Makefile +++ b/arch/arm/cpu/armv7/zynq/Makefile @@ -14,6 +14,7 @@ LIB = $(obj)lib$(SOC).o COBJS-y := timer.o COBJS-y += cpu.o +COBJS-y += ddrc.o COBJS-y += slcr.o COBJS := $(COBJS-y) diff --git a/arch/arm/cpu/armv7/zynq/ddrc.c b/arch/arm/cpu/armv7/zynq/ddrc.c new file mode 100644 index 0000000000..ba6a6aee5c --- /dev/null +++ b/arch/arm/cpu/armv7/zynq/ddrc.c @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2012 - 2013 Michal Simek <monstr@monstr.eu> + * Copyright (C) 2012 - 2013 Xilinx, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/hardware.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* Control regsiter bitfield definitions */ +#define ZYNQ_DDRC_CTRLREG_BUSWIDTH_MASK 0xC +#define ZYNQ_DDRC_CTRLREG_BUSWIDTH_SHIFT 2 +#define ZYNQ_DDRC_CTRLREG_BUSWIDTH_16BIT 1 + +/* ECC scrub regsiter definitions */ +#define ZYNQ_DDRC_ECC_SCRUBREG_ECC_MODE_MASK 0x7 +#define ZYNQ_DDRC_ECC_SCRUBREG_ECCMODE_SECDED 0x4 + +void zynq_ddrc_init(void) +{ + u32 width, ecctype; + + width = readl(&ddrc_base->ddrc_ctrl); + width = (width & ZYNQ_DDRC_CTRLREG_BUSWIDTH_MASK) >> + ZYNQ_DDRC_CTRLREG_BUSWIDTH_SHIFT; + ecctype = (readl(&ddrc_base->ecc_scrub) & + ZYNQ_DDRC_ECC_SCRUBREG_ECC_MODE_MASK); + + /* ECC is enabled when memory is in 16bit mode and it is enabled */ + if ((ecctype == ZYNQ_DDRC_ECC_SCRUBREG_ECCMODE_SECDED) && + (width == ZYNQ_DDRC_CTRLREG_BUSWIDTH_16BIT)) { + puts("Memory: ECC enabled\n"); + /* + * Clear the first 1MB because it is not initialized from + * first stage bootloader. To get ECC to work all memory has + * been initialized by writing any value. + */ + memset(0, 0, 1 * 1024 * 1024); + } else { + puts("Memory: ECC disabled\n"); + } + + if (width == ZYNQ_DDRC_CTRLREG_BUSWIDTH_16BIT) + gd->ram_size /= 2; +} diff --git a/arch/arm/cpu/armv7/zynq/slcr.c b/arch/arm/cpu/armv7/zynq/slcr.c index e5fe992982..717ec65aee 100644 --- a/arch/arm/cpu/armv7/zynq/slcr.c +++ b/arch/arm/cpu/armv7/zynq/slcr.c @@ -70,7 +70,7 @@ void zynq_slcr_gem_clk_setup(u32 gem_id, u32 rclk, u32 clk) /* Configure GEM_RCLK_CTRL */ writel(rclk, &slcr_base->gem0_rclk_ctrl); } - + udelay(100000); out: zynq_slcr_lock(); } diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds index 490aed2e0d..23bf030655 100644 --- a/arch/arm/cpu/u-boot.lds +++ b/arch/arm/cpu/u-boot.lds @@ -97,4 +97,6 @@ SECTIONS /DISCARD/ : { *(.plt*) } /DISCARD/ : { *(.interp*) } /DISCARD/ : { *(.gnu*) } + /DISCARD/ : { *(.ARM.exidx*) } + /DISCARD/ : { *(.gnu.linkonce.armexidx.*) } } |