12 files changed, 653 insertions, 10 deletions

diff --git a/arch/arm/cpu/arm1136/mx31/devices.c b/arch/arm/cpu/arm1136/mx31/devices.c
index 1e7d48f8fb..b42dac3fbe 100644
--- a/arch/arm/cpu/arm1136/mx31/devices.c
+++ b/arch/arm/cpu/arm1136/mx31/devices.c
@@ -38,7 +38,22 @@ void mx31_uart1_hw_init(void)
 }
 #endif
 
+#ifdef CONFIG_SYS_MX31_UART2
+void mx31_uart2_hw_init(void)
+{
+	/* setup pins for UART2 */
+	mx31_gpio_mux(MUX_RXD2__UART2_RXD_MUX);
+	mx31_gpio_mux(MUX_TXD2__UART2_TXD_MUX);
+	mx31_gpio_mux(MUX_RTS2__UART2_RTS_B);
+	mx31_gpio_mux(MUX_CTS2__UART2_CTS_B);
+}
+#endif
+
 #ifdef CONFIG_MXC_SPI
+/*
+ * Note: putting several spi setups here makes no sense as they may differ
+ * at board level (physical pin SS0 of CSPI2 may aswell be used as SS0 of CSPI3)
+ */
 void mx31_spi2_hw_init(void)
 {
 	/* SPI2 */
diff --git a/arch/arm/cpu/arm1136/mx31/generic.c b/arch/arm/cpu/arm1136/mx31/generic.c
index 78df7b9261..4f27e250bd 100644
--- a/arch/arm/cpu/arm1136/mx31/generic.c
+++ b/arch/arm/cpu/arm1136/mx31/generic.c
@@ -27,6 +27,8 @@
 #include <asm/io.h>
 #include <asm/arch/sys_proto.h>
 
+#define IOMUXGPR	(IOMUXC_BASE + 0x008)
+
 static u32 mx31_decode_pll(u32 reg, u32 infreq)
 {
 	u32 mfi = GET_PLL_MFI(reg);
@@ -141,6 +143,19 @@ void mx31_set_pad(enum iomux_pins pin, u32 config)
 
 }
 
+void mx31_set_gpr(enum iomux_gp_func gp, char en)
+{
+	u32 l;
+
+	l = readl(IOMUXGPR);
+	if (en)
+		l |= gp;
+	else
+		l &= ~gp;
+
+	writel(l, IOMUXGPR);
+}
+
 void mxc_setup_weimcs(int cs, const struct mxc_weimcs *weimcs)
 {
 	struct mx31_weim *weim = (struct mx31_weim *) WEIM_BASE;
diff --git a/arch/arm/cpu/arm1136/mx35/generic.c b/arch/arm/cpu/arm1136/mx35/generic.c
index 1b9809b2f8..ac4838f034 100644
--- a/arch/arm/cpu/arm1136/mx35/generic.c
+++ b/arch/arm/cpu/arm1136/mx35/generic.c
@@ -422,12 +422,39 @@ U_BOOT_CMD(
 	""
 );
 
+static char *get_reset_cause(void)
+{
+	/* read RCSR register from CCM module */
+	struct ccm_regs *ccm =
+		(struct ccm_regs *)IMX_CCM_BASE;
+
+	u32 cause = readl(&ccm->rcsr) & 0x0F;
+
+	switch (cause) {
+	case 0x0000:
+		return "POR";
+	case 0x0002:
+		return "JTAG";
+	case 0x0004:
+		return "RST";
+	case 0x0008:
+		return "WDOG";
+	default:
+		return "unknown reset";
+	}
+}
+
 #if defined(CONFIG_DISPLAY_CPUINFO)
 int print_cpuinfo(void)
 {
-	printf("CPU:   Freescale i.MX35 at %d MHz\n",
+	u32 srev = get_cpu_rev();
+
+	printf("CPU:   Freescale i.MX35 rev %d.%d at %d MHz.\n",
+		(srev & 0xF0) >> 4, (srev & 0x0F),
 		get_mcu_main_clk() / 1000000);
-	/* mxc_dump_clocks(); */
+
+	printf("Reset cause: %s\n", get_reset_cause());
+
 	return 0;
 }
 #endif
diff --git a/arch/arm/cpu/arm926ejs/davinci/Makefile b/arch/arm/cpu/arm926ejs/davinci/Makefile
index 0310957f89..98c7e55c40 100644
--- a/arch/arm/cpu/arm926ejs/davinci/Makefile
+++ b/arch/arm/cpu/arm926ejs/davinci/Makefile
@@ -35,6 +35,11 @@ COBJS-$(CONFIG_SOC_DM644X)	+= dm644x.o
 COBJS-$(CONFIG_SOC_DM646X)	+= dm646x.o
 COBJS-$(CONFIG_DRIVER_TI_EMAC)	+= lxt972.o dp83848.o et1011c.o ksz8873.o
 
+ifdef CONFIG_SPL_BUILD
+COBJS-y	+= spl.o
+COBJS-y	+= dm365_lowlevel.o
+endif
+
 SOBJS	= reset.o
 
 ifndef CONFIG_SKIP_LOWLEVEL_INIT
diff --git a/arch/arm/cpu/arm926ejs/davinci/cpu.c b/arch/arm/cpu/arm926ejs/davinci/cpu.c
index 02819f6f74..9ea97853c7 100644
--- a/arch/arm/cpu/arm926ejs/davinci/cpu.c
+++ b/arch/arm/cpu/arm926ejs/davinci/cpu.c
@@ -146,13 +146,15 @@ static inline unsigned pll_prediv(volatile void *pllbase)
 		return 8;
 	else
 		return pll_div(pllbase, PLLC_PREDIV);
+#elif defined(CONFIG_SOC_DM365)
+	return pll_div(pllbase, PLLC_PREDIV);
 #endif
 	return 1;
 }
 
 static inline unsigned pll_postdiv(volatile void *pllbase)
 {
-#ifdef CONFIG_SOC_DM355
+#if defined(CONFIG_SOC_DM355) || defined(CONFIG_SOC_DM365)
 	return pll_div(pllbase, PLLC_POSTDIV);
 #elif defined(CONFIG_SOC_DM6446)
 	if (pllbase == (volatile void *)DAVINCI_PLL_CNTRL0_BASE)
@@ -171,9 +173,13 @@ static unsigned pll_sysclk_mhz(unsigned pll_addr, unsigned div)
 #endif
 
 	/* the PLL might be bypassed */
-	if (REG(pllbase + PLLC_PLLCTL) & BIT(0)) {
+	if (readl(pllbase + PLLC_PLLCTL) & BIT(0)) {
 		base /= pll_prediv(pllbase);
+#if defined(CONFIG_SOC_DM365)
+		base *=  2 * (readl(pllbase + PLLC_PLLM) & 0x0ff);
+#else
 		base *= 1 + (REG(pllbase + PLLC_PLLM) & 0x0ff);
+#endif
 		base /= pll_postdiv(pllbase);
 	}
 	return DIV_ROUND_UP(base, 1000 * pll_div(pllbase, div));
@@ -184,8 +190,13 @@ int print_cpuinfo(void)
 	/* REVISIT fetch and display CPU ID and revision information
 	 * too ... that will matter as more revisions appear.
 	 */
+#if defined(CONFIG_SOC_DM365)
+	printf("Cores: ARM %d MHz",
+			pll_sysclk_mhz(DAVINCI_PLL_CNTRL1_BASE, ARM_PLLDIV));
+#else
 	printf("Cores: ARM %d MHz",
 			pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV));
+#endif
 
 #ifdef DSP_PLLDIV
 	printf(", DSP %d MHz",
@@ -194,8 +205,13 @@ int print_cpuinfo(void)
 
 	printf("\nDDR:   %d MHz\n",
 			/* DDR PHY uses an x2 input clock */
+#if defined(CONFIG_SOC_DM365)
+			pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, DDR_PLLDIV)
+				/ 2);
+#else
 			pll_sysclk_mhz(DAVINCI_PLL_CNTRL1_BASE, DDR_PLLDIV)
 				/ 2);
+#endif
 	return 0;
 }
 
@@ -205,6 +221,13 @@ unsigned int davinci_arm_clk_get()
 	return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV) * 1000000;
 }
 #endif
+
+#if defined(CONFIG_SOC_DM365)
+unsigned int davinci_clk_get(unsigned int div)
+{
+	return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, div) * 1000000;
+}
+#endif
 #endif /* CONFIG_DISPLAY_CPUINFO */
 #endif /* !CONFIG_SOC_DA8XX */
 
diff --git a/arch/arm/cpu/arm926ejs/davinci/dm365_lowlevel.c b/arch/arm/cpu/arm926ejs/davinci/dm365_lowlevel.c
new file mode 100644
index 0000000000..3772e64cc4
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/davinci/dm365_lowlevel.c
@@ -0,0 +1,439 @@
+/*
+ * SoC-specific lowlevel code for tms320dm365 and similar chips
+ * Actually used for booting from NAND with nand_spl.
+ *
+ * Copyright (C) 2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <common.h>
+#include <nand.h>
+#include <ns16550.h>
+#include <post.h>
+#include <asm/arch/dm365_lowlevel.h>
+#include <asm/arch/hardware.h>
+
+void dm365_waitloop(unsigned long loopcnt)
+{
+	unsigned long	i;
+
+	for (i = 0; i < loopcnt; i++)
+		asm("   NOP");
+}
+
+int dm365_pll1_init(unsigned long pllmult, unsigned long prediv)
+{
+	unsigned int clksrc = 0x0;
+
+	/* Power up the PLL */
+	clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLPWRDN);
+
+	clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_RES_9);
+	setbits_le32(&dv_pll0_regs->pllctl, clksrc << 8);
+
+	/*
+	 * Set PLLENSRC '0', PLL Enable(PLLEN) selection is controlled
+	 * through MMR
+	 */
+	clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLENSRC);
+
+	/* Set PLLEN=0 => PLL BYPASS MODE */
+	clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLEN);
+
+	dm365_waitloop(150);
+
+	 /* PLLRST=1(reset assert) */
+	setbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLRST);
+
+	dm365_waitloop(300);
+
+	/*Bring PLL out of Reset*/
+	clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLRST);
+
+	/* Program the Multiper and Pre-Divider for PLL1 */
+	writel(pllmult, &dv_pll0_regs->pllm);
+	writel(prediv, &dv_pll0_regs->prediv);
+
+	/* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 1 */
+	writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE |
+		PLLSECCTL_TINITZ, &dv_pll0_regs->secctl);
+	/* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 0 */
+	writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE,
+		&dv_pll0_regs->secctl);
+	/* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 0 */
+	writel(PLLSECCTL_STOPMODE, &dv_pll0_regs->secctl);
+	/* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 1 */
+	writel(PLLSECCTL_STOPMODE | PLLSECCTL_TINITZ, &dv_pll0_regs->secctl);
+
+	/* Program the PostDiv for PLL1 */
+	writel(0x8000, &dv_pll0_regs->postdiv);
+
+	/* Post divider setting for PLL1 */
+	writel(CONFIG_SYS_DM36x_PLL1_PLLDIV1, &dv_pll0_regs->plldiv1);
+	writel(CONFIG_SYS_DM36x_PLL1_PLLDIV2, &dv_pll0_regs->plldiv2);
+	writel(CONFIG_SYS_DM36x_PLL1_PLLDIV3, &dv_pll0_regs->plldiv3);
+	writel(CONFIG_SYS_DM36x_PLL1_PLLDIV4, &dv_pll0_regs->plldiv4);
+	writel(CONFIG_SYS_DM36x_PLL1_PLLDIV5, &dv_pll0_regs->plldiv5);
+	writel(CONFIG_SYS_DM36x_PLL1_PLLDIV6, &dv_pll0_regs->plldiv6);
+	writel(CONFIG_SYS_DM36x_PLL1_PLLDIV7, &dv_pll0_regs->plldiv7);
+	writel(CONFIG_SYS_DM36x_PLL1_PLLDIV8, &dv_pll0_regs->plldiv8);
+	writel(CONFIG_SYS_DM36x_PLL1_PLLDIV9, &dv_pll0_regs->plldiv9);
+
+	dm365_waitloop(300);
+
+	/* Set the GOSET bit */
+	writel(PLLCMD_GOSET, &dv_pll0_regs->pllcmd); /* Go */
+
+	dm365_waitloop(300);
+
+	/* Wait for PLL to LOCK */
+	while (!((readl(&dv_sys_module_regs->pll0_config) & PLL0_LOCK)
+		== PLL0_LOCK))
+		;
+
+	/* Enable the PLL Bit of PLLCTL*/
+	setbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLEN);
+
+	return 0;
+}
+
+int dm365_pll2_init(unsigned long pllm, unsigned long prediv)
+{
+	unsigned int clksrc = 0x0;
+
+	/* Power up the PLL*/
+	clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLPWRDN);
+
+	/*
+	 * Select the Clock Mode as Onchip Oscilator or External Clock on
+	 * MXI pin
+	 * VDB has input on MXI pin
+	 */
+	clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_RES_9);
+	setbits_le32(&dv_pll1_regs->pllctl, clksrc << 8);
+
+	/*
+	 * Set PLLENSRC '0', PLL Enable(PLLEN) selection is controlled
+	 * through MMR
+	 */
+	clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLENSRC);
+
+	/* Set PLLEN=0 => PLL BYPASS MODE */
+	clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLEN);
+
+	dm365_waitloop(50);
+
+	 /* PLLRST=1(reset assert) */
+	setbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLRST);
+
+	dm365_waitloop(300);
+
+	/* Bring PLL out of Reset */
+	clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLRST);
+
+	/* Program the Multiper and Pre-Divider for PLL2 */
+	writel(pllm, &dv_pll1_regs->pllm);
+	writel(prediv, &dv_pll1_regs->prediv);
+
+	writel(0x8000, &dv_pll1_regs->postdiv);
+
+	/* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 1 */
+	writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE |
+		PLLSECCTL_TINITZ, &dv_pll1_regs->secctl);
+	/* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 0 */
+	writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE,
+		&dv_pll1_regs->secctl);
+	/* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 0 */
+	writel(PLLSECCTL_STOPMODE, &dv_pll1_regs->secctl);
+	/* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 1 */
+	writel(PLLSECCTL_STOPMODE | PLLSECCTL_TINITZ, &dv_pll1_regs->secctl);
+
+	/* Post divider setting for PLL2 */
+	writel(CONFIG_SYS_DM36x_PLL2_PLLDIV1, &dv_pll1_regs->plldiv1);
+	writel(CONFIG_SYS_DM36x_PLL2_PLLDIV2, &dv_pll1_regs->plldiv2);
+	writel(CONFIG_SYS_DM36x_PLL2_PLLDIV3, &dv_pll1_regs->plldiv3);
+	writel(CONFIG_SYS_DM36x_PLL2_PLLDIV4, &dv_pll1_regs->plldiv4);
+	writel(CONFIG_SYS_DM36x_PLL2_PLLDIV5, &dv_pll1_regs->plldiv5);
+
+	/* GoCmd for PostDivider to take effect */
+	writel(PLLCMD_GOSET, &dv_pll1_regs->pllcmd);
+
+	dm365_waitloop(150);
+
+	/* Wait for PLL to LOCK */
+	while (!((readl(&dv_sys_module_regs->pll1_config) & PLL1_LOCK)
+		== PLL1_LOCK))
+		;
+
+	dm365_waitloop(4100);
+
+	/* Enable the PLL2 */
+	setbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLEN);
+
+	/* do this after PLL's have been set up */
+	writel(CONFIG_SYS_DM36x_PERI_CLK_CTRL,
+		&dv_sys_module_regs->peri_clkctl);
+
+	return 0;
+}
+
+int dm365_ddr_setup(void)
+{
+	lpsc_on(DAVINCI_LPSC_DDR_EMIF);
+	clrbits_le32(&dv_sys_module_regs->vtpiocr,
+		VPTIO_IOPWRDN | VPTIO_CLRZ | VPTIO_LOCK | VPTIO_PWRDN);
+
+	/* Set bit CLRZ (bit 13) */
+	setbits_le32(&dv_sys_module_regs->vtpiocr, VPTIO_CLRZ);
+
+	/* Check VTP READY Status */
+	while (!(readl(&dv_sys_module_regs->vtpiocr) & VPTIO_RDY))
+		;
+
+	/* Set bit VTP_IOPWRDWN bit 14 for DDR input buffers) */
+	setbits_le32(&dv_sys_module_regs->vtpiocr, VPTIO_IOPWRDN);
+
+	/* Set bit LOCK(bit7) */
+	setbits_le32(&dv_sys_module_regs->vtpiocr, VPTIO_LOCK);
+
+	/*
+	 * Powerdown VTP as it is locked (bit 6)
+	 * Set bit VTP_IOPWRDWN bit 14 for DDR input buffers)
+	 */
+	setbits_le32(&dv_sys_module_regs->vtpiocr,
+		VPTIO_IOPWRDN | VPTIO_PWRDN);
+
+	/* Wait for calibration to complete */
+	dm365_waitloop(150);
+
+	/* Set the DDR2 to synreset, then enable it again */
+	lpsc_syncreset(DAVINCI_LPSC_DDR_EMIF);
+	lpsc_on(DAVINCI_LPSC_DDR_EMIF);
+
+	writel(CONFIG_SYS_DM36x_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr);
+
+	/* Program SDRAM Bank Config Register */
+	writel((CONFIG_SYS_DM36x_DDR2_SDBCR | DV_DDR_BOOTUNLOCK),
+		&dv_ddr2_regs_ctrl->sdbcr);
+	writel((CONFIG_SYS_DM36x_DDR2_SDBCR | DV_DDR_TIMUNLOCK),
+		&dv_ddr2_regs_ctrl->sdbcr);
+
+	/* Program SDRAM Timing Control Register1 */
+	writel(CONFIG_SYS_DM36x_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr);
+	/* Program SDRAM Timing Control Register2 */
+	writel(CONFIG_SYS_DM36x_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2);
+
+	writel(CONFIG_SYS_DM36x_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr);
+
+	writel(CONFIG_SYS_DM36x_DDR2_SDBCR, &dv_ddr2_regs_ctrl->sdbcr);
+
+	/* Program SDRAM Refresh Control Register */
+	writel(CONFIG_SYS_DM36x_DDR2_SDRCR, &dv_ddr2_regs_ctrl->sdrcr);
+
+	lpsc_syncreset(DAVINCI_LPSC_DDR_EMIF);
+	lpsc_on(DAVINCI_LPSC_DDR_EMIF);
+
+	return 0;
+}
+
+void dm365_vpss_sync_reset(void)
+{
+	unsigned int PdNum = 0;
+
+	/* VPSS_CLKMD 1:1 */
+	setbits_le32(&dv_sys_module_regs->vpss_clkctl,
+		VPSS_CLK_CTL_VPSS_CLKMD);
+
+	/* LPSC SyncReset DDR Clock Enable */
+	writel(((readl(&dv_psc_regs->mdctl[47]) & ~PSC_MD_STATE_MSK) |
+		PSC_SYNCRESET), &dv_psc_regs->mdctl[47]);
+
+	writel((1 << PdNum), &dv_psc_regs->ptcmd);
+
+	while (!(((readl(&dv_psc_regs->ptstat) >> PdNum) & PSC_GOSTAT) == 0))
+		;
+	while (!((readl(&dv_psc_regs->mdstat[47]) &  PSC_MD_STATE_MSK) ==
+		PSC_SYNCRESET))
+		;
+}
+
+void dm365_por_reset(void)
+{
+	if (readl(&dv_pll0_regs->rstype) & 3)
+		dm365_vpss_sync_reset();
+}
+
+void dm365_psc_init(void)
+{
+	unsigned char i = 0;
+	unsigned char lpsc_start;
+	unsigned char lpsc_end, lpscgroup, lpscmin, lpscmax;
+	unsigned int  PdNum = 0;
+
+	lpscmin = 0;
+	lpscmax = 2;
+
+	for (lpscgroup = lpscmin; lpscgroup <= lpscmax; lpscgroup++) {
+		if (lpscgroup == 0) {
+			lpsc_start = 0; /* Enabling LPSC 3 to 28 SCR first */
+			lpsc_end   = 28;
+		} else if (lpscgroup == 1) { /* Skip locked LPSCs [29-37] */
+			lpsc_start = 38;
+			lpsc_end   = 47;
+		} else {
+			lpsc_start = 50;
+			lpsc_end   = 51;
+		}
+
+		/* NEXT=0x3, Enable LPSC's */
+		for (i = lpsc_start; i <= lpsc_end; i++)
+			setbits_le32(&dv_psc_regs->mdctl[i], 0x3);
+
+		/*
+		 * Program goctl to start transition sequence for LPSCs
+		 * CSL_PSC_0_REGS->PTCMD = (1<<PdNum); Kick off Power
+		 * Domain 0 Modules
+		 */
+		writel((1 << PdNum), &dv_psc_regs->ptcmd);
+
+		/*
+		 * Wait for GOSTAT = NO TRANSITION from PSC for Powerdomain 0
+		 */
+		while (!(((readl(&dv_psc_regs->ptstat) >> PdNum) & PSC_GOSTAT)
+			== 0))
+			;
+
+		/* Wait for MODSTAT = ENABLE from LPSC's */
+		for (i = lpsc_start; i <= lpsc_end; i++)
+			while (!((readl(&dv_psc_regs->mdstat[i]) &
+				PSC_MD_STATE_MSK) == 0x3))
+				;
+	}
+}
+
+static void dm365_emif_init(void)
+{
+	writel(CONFIG_SYS_DM36x_AWCCR, &davinci_emif_regs->awccr);
+	writel(CONFIG_SYS_DM36x_AB1CR, &davinci_emif_regs->ab1cr);
+
+	setbits_le32(&davinci_emif_regs->nandfcr, 1);
+
+	writel(CONFIG_SYS_DM36x_AB2CR, &davinci_emif_regs->ab2cr);
+
+	return;
+}
+
+void dm365_pinmux_ctl(unsigned long offset, unsigned long mask,
+	unsigned long value)
+{
+	clrbits_le32(&dv_sys_module_regs->pinmux[offset], mask);
+	setbits_le32(&dv_sys_module_regs->pinmux[offset], (mask & value));
+}
+
+__attribute__((weak))
+void board_gpio_init(void)
+{
+	return;
+}
+
+#if defined(CONFIG_POST)
+int post_log(char *format, ...)
+{
+	return 0;
+}
+#endif
+
+void dm36x_lowlevel_init(ulong bootflag)
+{
+	/*
+	 * copied from arch/arm/cpu/arm926ejs/start.S
+	 *
+	 * flush v4 I/D caches
+	 */
+	asm("mov	r0, #0");
+	asm("mcr	p15, 0, r0, c7, c7, 0");	/* flush v3/v4 cache */
+	asm("mcr	p15, 0, r0, c8, c7, 0");	/* flush v4 TLB */
+
+	/*
+	 * disable MMU stuff and caches
+	 */
+	asm("mrc	p15, 0, r0, c1, c0, 0");
+	/* clear bits 13, 9:8 (--V- --RS) */
+	asm("bic	r0, r0, #0x00002300");
+	/* clear bits 7, 2:0 (B--- -CAM) */
+	asm("bic	r0, r0, #0x00000087");
+	/* set bit 2 (A) Align */
+	asm("orr	r0, r0, #0x00000002");
+	/* set bit 12 (I) I-Cache */
+	asm("orr	r0, r0, #0x00001000");
+	asm("mcr	p15, 0, r0, c1, c0, 0");
+
+	/* Mask all interrupts */
+	writel(0x04, &dv_aintc_regs->intctl);
+	writel(0x0, &dv_aintc_regs->eabase);
+	writel(0x0, &dv_aintc_regs->eint0);
+	writel(0x0, &dv_aintc_regs->eint1);
+
+	/* Clear all interrupts */
+	writel(0xffffffff, &dv_aintc_regs->fiq0);
+	writel(0xffffffff, &dv_aintc_regs->fiq1);
+	writel(0xffffffff, &dv_aintc_regs->irq0);
+	writel(0xffffffff, &dv_aintc_regs->irq1);
+
+	/* System PSC setup - enable all */
+	dm365_psc_init();
+
+	/* Setup Pinmux */
+	dm365_pinmux_ctl(0, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX0);
+	dm365_pinmux_ctl(1, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX1);
+	dm365_pinmux_ctl(2, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX2);
+	dm365_pinmux_ctl(3, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX3);
+	dm365_pinmux_ctl(4, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX4);
+
+	/* PLL setup */
+	dm365_pll1_init(CONFIG_SYS_DM36x_PLL1_PLLM,
+		CONFIG_SYS_DM36x_PLL1_PREDIV);
+	dm365_pll2_init(CONFIG_SYS_DM36x_PLL2_PLLM,
+		CONFIG_SYS_DM36x_PLL2_PREDIV);
+
+	/* GPIO setup */
+	board_gpio_init();
+
+	NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM1),
+			CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
+
+	/*
+	 * Fix Power and Emulation Management Register
+	 * see sprufh2.pdf page 38 Table 22
+	 */
+	writel(0x0000e003, (CONFIG_SYS_NS16550_COM1 + 0x30));
+	puts("ddr init\n");
+	dm365_ddr_setup();
+
+	puts("emif init\n");
+	dm365_emif_init();
+
+#if defined(CONFIG_POST)
+	/*
+	 * Do memory tests, calls arch_memory_failure_handle()
+	 * if error detected.
+	 */
+	memory_post_test(0);
+#endif
+}
diff --git a/arch/arm/cpu/arm926ejs/davinci/psc.c b/arch/arm/cpu/arm926ejs/davinci/psc.c
index 707fa47e31..3e925181ea 100644
--- a/arch/arm/cpu/arm926ejs/davinci/psc.c
+++ b/arch/arm/cpu/arm926ejs/davinci/psc.c
@@ -46,7 +46,7 @@
  */
 
 /* Works on Always On power domain only (no PD argument) */
-void lpsc_on(unsigned int id)
+static void lpsc_transition(unsigned int id, unsigned int state)
 {
 	dv_reg_p mdstat, mdctl, ptstat, ptcmd;
 #ifdef CONFIG_SOC_DA8XX
@@ -83,10 +83,10 @@ void lpsc_on(unsigned int id)
 	while (readl(ptstat) & 0x01)
 		continue;
 
-	if ((readl(mdstat) & PSC_MDSTAT_STATE) == 0x03)
-		return; /* Already on and enabled */
+	if ((readl(mdstat) & PSC_MDSTAT_STATE) == state)
+		return; /* Already in that state */
 
-	writel(readl(mdctl) | 0x03, mdctl);
+	writel((readl(mdctl) & ~PSC_MDCTL_NEXT) | state, mdctl);
 
 	switch (id) {
 #ifdef CONFIG_SOC_DM644X
@@ -114,10 +114,20 @@ void lpsc_on(unsigned int id)
 
 	while (readl(ptstat) & 0x01)
 		continue;
-	while ((readl(mdstat) & PSC_MDSTAT_STATE) != 0x03)
+	while ((readl(mdstat) & PSC_MDSTAT_STATE) != state)
 		continue;
 }
 
+void lpsc_on(unsigned int id)
+{
+	lpsc_transition(id, 0x03);
+}
+
+void lpsc_syncreset(unsigned int id)
+{
+	lpsc_transition(id, 0x01);
+}
+
 /* Not all DaVinci chips have a DSP power domain. */
 #ifdef CONFIG_SOC_DM644X
 
diff --git a/arch/arm/cpu/arm926ejs/davinci/spl.c b/arch/arm/cpu/arm926ejs/davinci/spl.c
new file mode 100644
index 0000000000..d9b9398b7e
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/davinci/spl.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright (C) 2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/u-boot.h>
+#include <asm/utils.h>
+#include <nand.h>
+#include <asm/arch/dm365_lowlevel.h>
+#include <ns16550.h>
+
+void puts(const char *str)
+{
+	while (*str)
+		putc(*str++);
+}
+
+void putc(char c)
+{
+	if (c == '\n')
+		NS16550_putc((NS16550_t)(CONFIG_SYS_NS16550_COM1), '\r');
+
+	NS16550_putc((NS16550_t)(CONFIG_SYS_NS16550_COM1), c);
+}
+
+inline void hang(void)
+{
+	puts("### ERROR ### Please RESET the board ###\n");
+	for (;;)
+		;
+}
+
+void board_init_f(ulong dummy)
+{
+	dm36x_lowlevel_init(0);
+	relocate_code(CONFIG_SPL_STACK, NULL, CONFIG_SPL_TEXT_BASE);
+}
+
+void board_init_r(gd_t *id, ulong dummy)
+{
+
+	nand_init();
+	puts("Nand boot...\n");
+	nand_boot();
+}
diff --git a/arch/arm/cpu/arm926ejs/kirkwood/asm-offsets.s b/arch/arm/cpu/arm926ejs/kirkwood/asm-offsets.s
deleted file mode 100644
index e69de29bb2..0000000000
--- a/arch/arm/cpu/arm926ejs/kirkwood/asm-offsets.s
+++ /dev/null
diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S
index 5e30745057..339c5ed6bd 100644
--- a/arch/arm/cpu/arm926ejs/start.S
+++ b/arch/arm/cpu/arm926ejs/start.S
@@ -126,7 +126,15 @@ _fiq:
 
 .globl _TEXT_BASE
 _TEXT_BASE:
+#ifdef CONFIG_NAND_SPL /* deprecated, use instead CONFIG_SPL_BUILD */
 	.word	CONFIG_SYS_TEXT_BASE
+#else
+#ifdef CONFIG_SPL_BUILD
+	.word	CONFIG_SPL_TEXT_BASE
+#else
+	.word	CONFIG_SYS_TEXT_BASE
+#endif
+#endif
 
 /*
  * These are defined in the board-specific linker script.
@@ -146,6 +154,12 @@ _bss_end_ofs:
 _end_ofs:
 	.word _end - _start
 
+#ifdef CONFIG_NAND_U_BOOT
+.globl _end
+_end:
+	.word __bss_end__
+#endif
+
 #ifdef CONFIG_USE_IRQ
 /* IRQ stack memory (calculated at run-time) */
 .globl IRQ_STACK_START
@@ -186,7 +200,15 @@ reset:
 
 /* Set stackpointer in internal RAM to call board_init_f */
 call_board_init_f:
+#ifdef CONFIG_NAND_SPL /* deprecated, use instead CONFIG_SPL_BUILD */
+	ldr	sp, =(CONFIG_SYS_INIT_SP_ADDR)
+#else
+#ifdef CONFIG_SPL_BUILD
+	ldr	sp, =(CONFIG_SPL_STACK)
+#else
 	ldr	sp, =(CONFIG_SYS_INIT_SP_ADDR)
+#endif
+#endif
 	bic	sp, sp, #7 /* 8-byte alignment for ABI compliance */
 	ldr	r0,=0x00000000
 	bl	board_init_f
@@ -211,6 +233,7 @@ stack_setup:
 	mov	sp, r4
 
 	adr	r0, _start
+	sub	r9, r6, r0		/* r9 <- relocation offset */
 	cmp	r0, r6
 	beq	clear_bss		/* skip relocation */
 	mov	r1, r6			/* r1 <- scratch for copy loop */
@@ -265,12 +288,17 @@ fixnext:
 #endif
 
 clear_bss:
-#ifndef CONFIG_SPL_BUILD
+#ifdef CONFIG_SPL_BUILD
+	/* No relocation for SPL */
+	ldr	r0, =__bss_start
+	ldr	r1, =__bss_end__
+#else
 	ldr	r0, _bss_start_ofs
 	ldr	r1, _bss_end_ofs
 	mov	r4, r6			/* reloc addr */
 	add	r0, r0, r4
 	add	r1, r1, r4
+#endif
 	mov	r2, #0x00000000		/* clear			    */
 
 clbss_l:str	r2, [r0]		/* clear loop...		    */
@@ -278,6 +306,7 @@ clbss_l:str	r2, [r0]		/* clear loop...		    */
 	cmp	r0, r1
 	bne	clbss_l
 
+#ifndef CONFIG_SPL_BUILD
 	bl coloured_LED_init
 	bl red_led_on
 #endif
diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
index 7e37221e03..01f6d759b9 100644
--- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
@@ -180,6 +180,21 @@
 1:	ldr r1, [r0, #CLKCTL_CDHIPR]
 	cmp r1, #0x0
 	bne 1b
+#else
+	ldr r1, =0x3FFFFFFF
+	str r1, [r0, #CLKCTL_CCGR0]
+	ldr r1, =0x0
+	str r1, [r0, #CLKCTL_CCGR1]
+	str r1, [r0, #CLKCTL_CCGR2]
+	str r1, [r0, #CLKCTL_CCGR3]
+	str r1, [r0, #CLKCTL_CCGR7]
+
+	ldr r1, =0x00030000
+	str r1, [r0, #CLKCTL_CCGR4]
+	ldr r1, =0x00FFF030
+	str r1, [r0, #CLKCTL_CCGR5]
+	ldr r1, =0x0F00030F
+	str r1, [r0, #CLKCTL_CCGR6]
 #endif
 
 	/* Switch ARM to step clock */
diff --git a/arch/arm/cpu/armv7/omap-common/spl.c b/arch/arm/cpu/armv7/omap-common/spl.c
index d37ca0ff5a..2c59d2b36b 100644
--- a/arch/arm/cpu/armv7/omap-common/spl.c
+++ b/arch/arm/cpu/armv7/omap-common/spl.c
@@ -156,6 +156,8 @@ void preloader_console_init(void)
 
 	serial_init();		/* serial communications setup */
 
+	gd->have_console = 1;
+
 	/* Avoid a second "U-Boot" coming from this string */
 	u_boot_rev = &u_boot_rev[7];