diff options
Diffstat (limited to 'arch/arm/cpu')
| -rw-r--r-- | arch/arm/cpu/armv7/mx6/Kconfig | 16 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/mx7ulp/scg.c | 8 | ||||
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 3 |
3 files changed, 24 insertions, 3 deletions
diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig index 190e5c6ec7..af6dad3aa9 100644 --- a/arch/arm/cpu/armv7/mx6/Kconfig +++ b/arch/arm/cpu/armv7/mx6/Kconfig @@ -155,6 +155,19 @@ config TARGET_MX6CUBOXI select BOARD_LATE_INIT select SUPPORT_SPL +config TARGET_MX6LOGICPD + bool "Logic PD i.MX6 SOM" + select BOARD_EARLY_INIT_F + select BOARD_LATE_INIT + select DM + select DM_ETH + select DM_GPIO + select DM_I2C + select DM_MMC + select DM_PMIC + select DM_REGULATOR + select OF_CONTROL + config TARGET_MX6QARM2 bool "mx6qarm2" @@ -172,6 +185,7 @@ config TARGET_MX6Q_ICORE config TARGET_MX6Q_ICORE_RQS bool "Support Engicam i.Core RQS" + select BOARD_LATE_INIT select MX6QDL select OF_CONTROL select DM @@ -253,6 +267,7 @@ config TARGET_MX6UL_GEAM select SUPPORT_SPL config TARGET_MX6UL_ISIOT bool "Support Engicam Is.IoT MX6UL" + select BOARD_LATE_INIT select MX6UL select OF_CONTROL select DM @@ -404,6 +419,7 @@ source "board/gateworks/gw_ventana/Kconfig" source "board/kosagi/novena/Kconfig" source "board/samtec/vining_2000/Kconfig" source "board/liebherr/mccmon6/Kconfig" +source "board/logicpd/imx6/Kconfig" source "board/seco/Kconfig" source "board/solidrun/mx6cuboxi/Kconfig" source "board/technexion/pico-imx6ul/Kconfig" diff --git a/arch/arm/cpu/armv7/mx7ulp/scg.c b/arch/arm/cpu/armv7/mx7ulp/scg.c index ca8252d0d2..c117af0a0e 100644 --- a/arch/arm/cpu/armv7/mx7ulp/scg.c +++ b/arch/arm/cpu/armv7/mx7ulp/scg.c @@ -504,7 +504,9 @@ u32 decode_pll(enum pll_clocks pll) num = readl(&scg1_regs->spllnum); denom = readl(&scg1_regs->splldenom); - return (infreq / pre_div) * (mult + num / denom); + infreq = infreq / pre_div; + + return infreq * mult + infreq * num / denom; case PLL_A7_APLL: reg = readl(&scg1_regs->apllcsr); @@ -531,7 +533,9 @@ u32 decode_pll(enum pll_clocks pll) num = readl(&scg1_regs->apllnum); denom = readl(&scg1_regs->aplldenom); - return (infreq / pre_div) * (mult + num / denom); + infreq = infreq / pre_div; + + return infreq * mult + infreq * num / denom; case PLL_USB: reg = readl(&scg1_regs->upllcsr); diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index ea6c090e0b..d446527616 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -5,6 +5,7 @@ */ #include <common.h> +#include <fsl_ddr_sdram.h> #include <asm/io.h> #include <linux/errno.h> #include <asm/system.h> @@ -876,7 +877,7 @@ void update_early_mmu_table(void) __weak int dram_init(void) { - initdram(); + fsl_initdram(); #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) /* This will break-before-make MMU for DDR */ update_early_mmu_table(); |