diff options
Diffstat (limited to 'arch/arm/cpu')
30 files changed, 467 insertions, 2799 deletions
diff --git a/arch/arm/cpu/arm1136/start.S b/arch/arm/cpu/arm1136/start.S index 3e2358e132..1cfcca9fa6 100644 --- a/arch/arm/cpu/arm1136/start.S +++ b/arch/arm/cpu/arm1136/start.S @@ -15,48 +15,7 @@ #include <asm-offsets.h> #include <config.h> #include <version.h> -.globl _start -_start: b reset -#ifdef CONFIG_SPL_BUILD - ldr pc, _hang - ldr pc, _hang - ldr pc, _hang - ldr pc, _hang - ldr pc, _hang - ldr pc, _hang - ldr pc, _hang -_hang: - .word do_hang - .word 0x12345678 - .word 0x12345678 - .word 0x12345678 - .word 0x12345678 - .word 0x12345678 - .word 0x12345678 - .word 0x12345678 /* now 16*4=64 */ -#else - ldr pc, _undefined_instruction - ldr pc, _software_interrupt - ldr pc, _prefetch_abort - ldr pc, _data_abort - ldr pc, _not_used - ldr pc, _irq - ldr pc, _fiq - -_undefined_instruction: .word undefined_instruction -_software_interrupt: .word software_interrupt -_prefetch_abort: .word prefetch_abort -_data_abort: .word data_abort -_not_used: .word not_used -_irq: .word irq -_fiq: .word fiq -_pad: .word 0x12345678 /* now 16*4=64 */ -#endif /* CONFIG_SPL_BUILD */ -.global _end_vect -_end_vect: - - .balignl 16,0xdeadbeef /* ************************************************************************* * @@ -70,26 +29,7 @@ _end_vect: ************************************************************************* */ -#ifdef CONFIG_USE_IRQ -/* IRQ stack memory (calculated at run-time) */ -.globl IRQ_STACK_START -IRQ_STACK_START: - .word 0x0badc0de - -/* IRQ stack memory (calculated at run-time) */ -.globl FIQ_STACK_START -FIQ_STACK_START: - .word 0x0badc0de -#endif - -/* IRQ stack memory (calculated at run-time) + 8 bytes */ -.globl IRQ_STACK_START_IN -IRQ_STACK_START_IN: - .word 0x0badc0de - -/* - * the actual reset code - */ + .globl reset reset: /* @@ -152,195 +92,3 @@ cpu_init_crit: mov lr, ip /* restore link */ mov pc, lr /* back to my caller */ #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ - -#ifndef CONFIG_SPL_BUILD -/* - ************************************************************************* - * - * Interrupt handling - * - ************************************************************************* - */ -@ -@ IRQ stack frame. -@ -#define S_FRAME_SIZE 72 - -#define S_OLD_R0 68 -#define S_PSR 64 -#define S_PC 60 -#define S_LR 56 -#define S_SP 52 - -#define S_IP 48 -#define S_FP 44 -#define S_R10 40 -#define S_R9 36 -#define S_R8 32 -#define S_R7 28 -#define S_R6 24 -#define S_R5 20 -#define S_R4 16 -#define S_R3 12 -#define S_R2 8 -#define S_R1 4 -#define S_R0 0 - -#define MODE_SVC 0x13 -#define I_BIT 0x80 - -/* - * use bad_save_user_regs for abort/prefetch/undef/swi ... - * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling - */ - - .macro bad_save_user_regs - sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack - stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 - - ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort stack - ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs) - add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack - - add r5, sp, #S_SP - mov r1, lr - stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr - mov r0, sp @ save current stack into r0 (param register) - .endm - - .macro irq_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Calling r0-r12 - add r8, sp, #S_PC @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good. - stmdb r8, {sp, lr}^ @ Calling SP, LR - str lr, [r8, #0] @ Save calling PC - mrs r6, spsr - str r6, [r8, #4] @ Save CPSR - str r0, [r8, #8] @ Save OLD_R0 - mov r0, sp - .endm - - .macro irq_restore_user_regs - ldmia sp, {r0 - lr}^ @ Calling r0 - lr - mov r0, r0 - ldr lr, [sp, #S_PC] @ Get PC - add sp, sp, #S_FRAME_SIZE - subs pc, lr, #4 @ return & move spsr_svc into cpsr - .endm - - .macro get_bad_stack - ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter in banked mode) - - str lr, [r13] @ save caller lr in position 0 of saved stack - mrs lr, spsr @ get the spsr - str lr, [r13, #4] @ save spsr in position 1 of saved stack - - mov r13, #MODE_SVC @ prepare SVC-Mode - @ msr spsr_c, r13 - msr spsr, r13 @ switch modes, make sure moves will execute - mov lr, pc @ capture return pc - movs pc, lr @ jump to next instruction & switch modes. - .endm - - .macro get_bad_stack_swi - sub r13, r13, #4 @ space on current stack for scratch reg. - str r0, [r13] @ save R0's value. - ldr r0, IRQ_STACK_START_IN @ get data regions start - str lr, [r0] @ save caller lr in position 0 of saved stack - mrs lr, spsr @ get the spsr - str lr, [r0, #4] @ save spsr in position 1 of saved stack - ldr lr, [r0] @ restore lr - ldr r0, [r13] @ restore r0 - add r13, r13, #4 @ pop stack entry - .endm - - .macro get_irq_stack @ setup IRQ stack - ldr sp, IRQ_STACK_START - .endm - - .macro get_fiq_stack @ setup FIQ stack - ldr sp, FIQ_STACK_START - .endm -#endif /* CONFIG_SPL_BUILD */ - -/* - * exception handlers - */ -#ifdef CONFIG_SPL_BUILD - .align 5 -do_hang: - bl hang /* hang and never return */ -#else /* !CONFIG_SPL_BUILD */ - .align 5 -undefined_instruction: - get_bad_stack - bad_save_user_regs - bl do_undefined_instruction - - .align 5 -software_interrupt: - get_bad_stack_swi - bad_save_user_regs - bl do_software_interrupt - - .align 5 -prefetch_abort: - get_bad_stack - bad_save_user_regs - bl do_prefetch_abort - - .align 5 -data_abort: - get_bad_stack - bad_save_user_regs - bl do_data_abort - - .align 5 -not_used: - get_bad_stack - bad_save_user_regs - bl do_not_used - -#ifdef CONFIG_USE_IRQ - - .align 5 -irq: - get_irq_stack - irq_save_user_regs - bl do_irq - irq_restore_user_regs - - .align 5 -fiq: - get_fiq_stack - /* someone ought to write a more effiction fiq_save_user_regs */ - irq_save_user_regs - bl do_fiq - irq_restore_user_regs - -#else - - .align 5 -irq: - get_bad_stack - bad_save_user_regs - bl do_irq - - .align 5 -fiq: - get_bad_stack - bad_save_user_regs - bl do_fiq - -#endif - .align 5 -.global arm1136_cache_flush -arm1136_cache_flush: -#if !defined(CONFIG_SYS_ICACHE_OFF) - mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache -#endif -#if !defined(CONFIG_SYS_DCACHE_OFF) - mcr p15, 0, r1, c7, c14, 0 @ invalidate D cache -#endif - mov pc, lr @ back to caller -#endif /* CONFIG_SPL_BUILD */ diff --git a/arch/arm/cpu/arm1176/start.S b/arch/arm/cpu/arm1176/start.S index ce620115d4..0704bdde27 100644 --- a/arch/arm/cpu/arm1176/start.S +++ b/arch/arm/cpu/arm1176/start.S @@ -25,48 +25,6 @@ /* ************************************************************************* * - * Jump vector table as in table 3.1 in [1] - * - ************************************************************************* - */ - -.globl _start -_start: b reset -#ifndef CONFIG_SPL_BUILD - ldr pc, _undefined_instruction - ldr pc, _software_interrupt - ldr pc, _prefetch_abort - ldr pc, _data_abort - ldr pc, _not_used - ldr pc, _irq - ldr pc, _fiq - -_undefined_instruction: - .word undefined_instruction -_software_interrupt: - .word software_interrupt -_prefetch_abort: - .word prefetch_abort -_data_abort: - .word data_abort -_not_used: - .word not_used -_irq: - .word irq -_fiq: - .word fiq -_pad: - .word 0x12345678 /* now 16*4=64 */ -#else - . = _start + 64 -#endif - -.global _end_vect -_end_vect: - .balignl 16,0xdeadbeef -/* - ************************************************************************* - * * Startup Code (reset vector) * * do important init only if we don't start from memory! @@ -77,14 +35,7 @@ _end_vect: ************************************************************************* */ -/* IRQ stack memory (calculated at run-time) + 8 bytes */ -.globl IRQ_STACK_START_IN -IRQ_STACK_START_IN: - .word 0x0badc0de - -/* - * the actual reset code - */ + .globl reset reset: /* @@ -182,150 +133,3 @@ skip_tcmdisable: c_runtime_cpu_setup: mov pc, lr - -#ifndef CONFIG_SPL_BUILD -/* - ************************************************************************* - * - * Interrupt handling - * - ************************************************************************* - */ -@ -@ IRQ stack frame. -@ -#define S_FRAME_SIZE 72 - -#define S_OLD_R0 68 -#define S_PSR 64 -#define S_PC 60 -#define S_LR 56 -#define S_SP 52 - -#define S_IP 48 -#define S_FP 44 -#define S_R10 40 -#define S_R9 36 -#define S_R8 32 -#define S_R7 28 -#define S_R6 24 -#define S_R5 20 -#define S_R4 16 -#define S_R3 12 -#define S_R2 8 -#define S_R1 4 -#define S_R0 0 - -#define MODE_SVC 0x13 -#define I_BIT 0x80 - -/* - * use bad_save_user_regs for abort/prefetch/undef/swi ... - */ - - .macro bad_save_user_regs - /* carve out a frame on current user stack */ - sub sp, sp, #S_FRAME_SIZE - /* Save user registers (now in svc mode) r0-r12 */ - stmia sp, {r0 - r12} - - ldr r2, IRQ_STACK_START_IN - /* get values for "aborted" pc and cpsr (into parm regs) */ - ldmia r2, {r2 - r3} - /* grab pointer to old stack */ - add r0, sp, #S_FRAME_SIZE - - add r5, sp, #S_SP - mov r1, lr - /* save sp_SVC, lr_SVC, pc, cpsr */ - stmia r5, {r0 - r3} - /* save current stack into r0 (param register) */ - mov r0, sp - .endm - - .macro get_bad_stack - ldr r13, IRQ_STACK_START_IN @ setup our mode stack - - /* save caller lr in position 0 of saved stack */ - str lr, [r13] - /* get the spsr */ - mrs lr, spsr - /* save spsr in position 1 of saved stack */ - str lr, [r13, #4] - - /* prepare SVC-Mode */ - mov r13, #MODE_SVC - @ msr spsr_c, r13 - /* switch modes, make sure moves will execute */ - msr spsr, r13 - /* capture return pc */ - mov lr, pc - /* jump to next instruction & switch modes. */ - movs pc, lr - .endm - - .macro get_bad_stack_swi - /* space on current stack for scratch reg. */ - sub r13, r13, #4 - /* save R0's value. */ - str r0, [r13] - ldr r13, IRQ_STACK_START_IN @ setup our mode stack - /* save caller lr in position 0 of saved stack */ - str lr, [r0] - /* get the spsr */ - mrs lr, spsr - /* save spsr in position 1 of saved stack */ - str lr, [r0, #4] - /* restore lr */ - ldr lr, [r0] - /* restore r0 */ - ldr r0, [r13] - /* pop stack entry */ - add r13, r13, #4 - .endm - -/* - * exception handlers - */ - .align 5 -undefined_instruction: - get_bad_stack - bad_save_user_regs - bl do_undefined_instruction - - .align 5 -software_interrupt: - get_bad_stack_swi - bad_save_user_regs - bl do_software_interrupt - - .align 5 -prefetch_abort: - get_bad_stack - bad_save_user_regs - bl do_prefetch_abort - - .align 5 -data_abort: - get_bad_stack - bad_save_user_regs - bl do_data_abort - - .align 5 -not_used: - get_bad_stack - bad_save_user_regs - bl do_not_used - - .align 5 -irq: - get_bad_stack - bad_save_user_regs - bl do_irq - - .align 5 -fiq: - get_bad_stack - bad_save_user_regs - bl do_fiq -#endif /* CONFIG_SPL_BUILD */ diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S index 1a34842690..01c85be64b 100644 --- a/arch/arm/cpu/arm720t/start.S +++ b/arch/arm/cpu/arm720t/start.S @@ -15,48 +15,6 @@ /* ************************************************************************* * - * Jump vector table as in table 3.1 in [1] - * - ************************************************************************* - */ - - -.globl _start -_start: b reset - ldr pc, _undefined_instruction - ldr pc, _software_interrupt - ldr pc, _prefetch_abort - ldr pc, _data_abort - ldr pc, _not_used - ldr pc, _irq - ldr pc, _fiq - -#ifdef CONFIG_SPL_BUILD -_undefined_instruction: .word _undefined_instruction -_software_interrupt: .word _software_interrupt -_prefetch_abort: .word _prefetch_abort -_data_abort: .word _data_abort -_not_used: .word _not_used -_irq: .word _irq -_fiq: .word _fiq -_pad: .word 0x12345678 /* now 16*4=64 */ -#else -_undefined_instruction: .word undefined_instruction -_software_interrupt: .word software_interrupt -_prefetch_abort: .word prefetch_abort -_data_abort: .word data_abort -_not_used: .word not_used -_irq: .word irq -_fiq: .word fiq -_pad: .word 0x12345678 /* now 16*4=64 */ -#endif /* CONFIG_SPL_BUILD */ - - .balignl 16,0xdeadbeef - - -/* - ************************************************************************* - * * Startup Code (reset vector) * * do important init only if we don't start from RAM! @@ -67,26 +25,7 @@ _pad: .word 0x12345678 /* now 16*4=64 */ ************************************************************************* */ -#ifdef CONFIG_USE_IRQ -/* IRQ stack memory (calculated at run-time) */ -.globl IRQ_STACK_START -IRQ_STACK_START: - .word 0x0badc0de - -/* IRQ stack memory (calculated at run-time) */ -.globl FIQ_STACK_START -FIQ_STACK_START: - .word 0x0badc0de -#endif - -/* IRQ stack memory (calculated at run-time) + 8 bytes */ -.globl IRQ_STACK_START_IN -IRQ_STACK_START_IN: - .word 0x0badc0de - -/* - * the actual reset code - */ + .globl reset reset: /* @@ -139,169 +78,3 @@ cpu_init_crit: mov pc, lr #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ - - -#ifndef CONFIG_SPL_BUILD -/* - ************************************************************************* - * - * Interrupt handling - * - ************************************************************************* - */ - -@ -@ IRQ stack frame. -@ -#define S_FRAME_SIZE 72 - -#define S_OLD_R0 68 -#define S_PSR 64 -#define S_PC 60 -#define S_LR 56 -#define S_SP 52 - -#define S_IP 48 -#define S_FP 44 -#define S_R10 40 -#define S_R9 36 -#define S_R8 32 -#define S_R7 28 -#define S_R6 24 -#define S_R5 20 -#define S_R4 16 -#define S_R3 12 -#define S_R2 8 -#define S_R1 4 -#define S_R0 0 - -#define MODE_SVC 0x13 -#define I_BIT 0x80 - -/* - * use bad_save_user_regs for abort/prefetch/undef/swi ... - * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling - */ - - .macro bad_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Calling r0-r12 - add r8, sp, #S_PC - - ldr r2, IRQ_STACK_START_IN - ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0 - add r0, sp, #S_FRAME_SIZE @ restore sp_SVC - - add r5, sp, #S_SP - mov r1, lr - stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC, pc, cpsr, old_r - mov r0, sp - .endm - - .macro irq_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Calling r0-r12 - add r8, sp, #S_PC - stmdb r8, {sp, lr}^ @ Calling SP, LR - str lr, [r8, #0] @ Save calling PC - mrs r6, spsr - str r6, [r8, #4] @ Save CPSR - str r0, [r8, #8] @ Save OLD_R0 - mov r0, sp - .endm - - .macro irq_restore_user_regs - ldmia sp, {r0 - lr}^ @ Calling r0 - lr - mov r0, r0 - ldr lr, [sp, #S_PC] @ Get PC - add sp, sp, #S_FRAME_SIZE - subs pc, lr, #4 @ return & move spsr_svc into cpsr - .endm - - .macro get_bad_stack - ldr r13, IRQ_STACK_START_IN @ setup our mode stack - - str lr, [r13] @ save caller lr / spsr - mrs lr, spsr - str lr, [r13, #4] - - mov r13, #MODE_SVC @ prepare SVC-Mode - msr spsr_c, r13 - mov lr, pc - movs pc, lr - .endm - - .macro get_irq_stack @ setup IRQ stack - ldr sp, IRQ_STACK_START - .endm - - .macro get_fiq_stack @ setup FIQ stack - ldr sp, FIQ_STACK_START - .endm - -/* - * exception handlers - */ - .align 5 -undefined_instruction: - get_bad_stack - bad_save_user_regs - bl do_undefined_instruction - - .align 5 -software_interrupt: - get_bad_stack - bad_save_user_regs - bl do_software_interrupt - - .align 5 -prefetch_abort: - get_bad_stack - bad_save_user_regs - bl do_prefetch_abort - - .align 5 -data_abort: - get_bad_stack - bad_save_user_regs - bl do_data_abort - - .align 5 -not_used: - get_bad_stack - bad_save_user_regs - bl do_not_used - -#ifdef CONFIG_USE_IRQ - - .align 5 -irq: - get_irq_stack - irq_save_user_regs - bl do_irq - irq_restore_user_regs - - .align 5 -fiq: - get_fiq_stack - /* someone ought to write a more effiction fiq_save_user_regs */ - irq_save_user_regs - bl do_fiq - irq_restore_user_regs - -#else - - .align 5 -irq: - get_bad_stack - bad_save_user_regs - bl do_irq - - .align 5 -fiq: - get_bad_stack - bad_save_user_regs - bl do_fiq - -#endif -#endif /* CONFIG_SPL_BUILD */ diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.c b/arch/arm/cpu/arm720t/tegra-common/cpu.c index 168f525ec7..c6f3b029a1 100644 --- a/arch/arm/cpu/arm720t/tegra-common/cpu.c +++ b/arch/arm/cpu/arm720t/tegra-common/cpu.c @@ -82,7 +82,7 @@ struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = { { .n = 600, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */ }, /* - * T30: 1.4 GHz + * T30: 600 MHz * * Register Field Bits Width * ------------------------------ @@ -92,10 +92,10 @@ struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = { * PLLX_MISC cpcon 11: 8 4 */ { - { .n = 862, .m = 8, .p = 0, .cpcon = 8 }, /* OSC: 13.0 MHz */ - { .n = 583, .m = 8, .p = 0, .cpcon = 4 }, /* OSC: 19.2 MHz */ - { .n = 700, .m = 6, .p = 0, .cpcon = 8 }, /* OSC: 12.0 MHz */ - { .n = 700, .m = 13, .p = 0, .cpcon = 8 }, /* OSC: 26.0 MHz */ + { .n = 600, .m = 13, .p = 0, .cpcon = 8 }, /* OSC: 13.0 MHz */ + { .n = 500, .m = 16, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */ + { .n = 600, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 12.0 MHz */ + { .n = 600, .m = 26, .p = 0, .cpcon = 8 }, /* OSC: 26.0 MHz */ }, /* * T114: 700 MHz diff --git a/arch/arm/cpu/arm720t/tegra30/cpu.c b/arch/arm/cpu/arm720t/tegra30/cpu.c index a80648389c..9003902e3f 100644 --- a/arch/arm/cpu/arm720t/tegra30/cpu.c +++ b/arch/arm/cpu/arm720t/tegra30/cpu.c @@ -41,10 +41,18 @@ void tegra_i2c_ll_write_data(uint data, uint config) writel(config, ®->cnfg); } +#define TPS62366A_I2C_ADDR 0xC0 +#define TPS62366A_SET1_REG 0x01 +#define TPS62366A_SET1_DATA (0x4600 | TPS62366A_SET1_REG) + +#define TPS62361B_I2C_ADDR 0xC0 +#define TPS62361B_SET3_REG 0x03 +#define TPS62361B_SET3_DATA (0x4600 | TPS62361B_SET3_REG) + #define TPS65911_I2C_ADDR 0x5A #define TPS65911_VDDCTRL_OP_REG 0x28 #define TPS65911_VDDCTRL_SR_REG 0x27 -#define TPS65911_VDDCTRL_OP_DATA (0x2300 | TPS65911_VDDCTRL_OP_REG) +#define TPS65911_VDDCTRL_OP_DATA (0x2400 | TPS65911_VDDCTRL_OP_REG) #define TPS65911_VDDCTRL_SR_DATA (0x0100 | TPS65911_VDDCTRL_SR_REG) #define I2C_SEND_2_BYTES 0x0A02 @@ -58,9 +66,20 @@ static void enable_cpu_power_rail(void) reg |= CPUPWRREQ_OE; writel(reg, &pmc->pmc_cntrl); + /* Set VDD_CORE to 1.200V. */ +#ifdef CONFIG_TEGRA_VDD_CORE_TPS62366A_SET1 + tegra_i2c_ll_write_addr(TPS62366A_I2C_ADDR, 2); + tegra_i2c_ll_write_data(TPS62366A_SET1_DATA, I2C_SEND_2_BYTES); +#endif +#ifdef CONFIG_TEGRA_VDD_CORE_TPS62361B_SET3 + tegra_i2c_ll_write_addr(TPS62361B_I2C_ADDR, 2); + tegra_i2c_ll_write_data(TPS62361B_SET3_DATA, I2C_SEND_2_BYTES); +#endif + udelay(1000); + /* * Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus. - * First set VDD to 1.4V, then enable the VDD regulator. + * First set VDD to 1.0125V, then enable the VDD regulator. */ tegra_i2c_ll_write_addr(TPS65911_I2C_ADDR, 2); tegra_i2c_ll_write_data(TPS65911_VDDCTRL_OP_DATA, I2C_SEND_2_BYTES); diff --git a/arch/arm/cpu/arm920t/ep93xx/u-boot.lds b/arch/arm/cpu/arm920t/ep93xx/u-boot.lds index 96994043e4..623a635208 100644 --- a/arch/arm/cpu/arm920t/ep93xx/u-boot.lds +++ b/arch/arm/cpu/arm920t/ep93xx/u-boot.lds @@ -16,7 +16,8 @@ SECTIONS .text : { *(.__image_copy_start) - arch/arm/cpu/arm920t/start.o (.text*) + *(.vectors) + arch/arm/cpu/arm920t/start.o (.text*) /* the EP93xx expects to find the pattern 'CRUS' at 0x1000 */ . = 0x1000; LONG(0x53555243) diff --git a/arch/arm/cpu/arm920t/start.S b/arch/arm/cpu/arm920t/start.S index 7bf094aec1..07404502c8 100644 --- a/arch/arm/cpu/arm920t/start.S +++ b/arch/arm/cpu/arm920t/start.S @@ -15,36 +15,6 @@ /* ************************************************************************* * - * Jump vector table as in table 3.1 in [1] - * - ************************************************************************* - */ - - -.globl _start -_start: b start_code - ldr pc, _undefined_instruction - ldr pc, _software_interrupt - ldr pc, _prefetch_abort - ldr pc, _data_abort - ldr pc, _not_used - ldr pc, _irq - ldr pc, _fiq - -_undefined_instruction: .word undefined_instruction -_software_interrupt: .word software_interrupt -_prefetch_abort: .word prefetch_abort -_data_abort: .word data_abort -_not_used: .word not_used -_irq: .word irq -_fiq: .word fiq - - .balignl 16,0xdeadbeef - - -/* - ************************************************************************* - * * Startup Code (called from the ARM reset exception vector) * * do important init only if we don't start from memory! @@ -55,28 +25,9 @@ _fiq: .word fiq ************************************************************************* */ -#ifdef CONFIG_USE_IRQ -/* IRQ stack memory (calculated at run-time) */ -.globl IRQ_STACK_START -IRQ_STACK_START: - .word 0x0badc0de - -/* IRQ stack memory (calculated at run-time) */ -.globl FIQ_STACK_START -FIQ_STACK_START: - .word 0x0badc0de -#endif - -/* IRQ stack memory (calculated at run-time) + 8 bytes */ -.globl IRQ_STACK_START_IN -IRQ_STACK_START_IN: - .word 0x0badc0de + .globl reset -/* - * the actual start code - */ - -start_code: +reset: /* * set the cpu to SVC32 mode */ @@ -196,166 +147,3 @@ cpu_init_crit: mov lr, ip mov pc, lr #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ - -/* - ************************************************************************* - * - * Interrupt handling - * - ************************************************************************* - */ - -@ -@ IRQ stack frame. -@ -#define S_FRAME_SIZE 72 - -#define S_OLD_R0 68 -#define S_PSR 64 -#define S_PC 60 -#define S_LR 56 -#define S_SP 52 - -#define S_IP 48 -#define S_FP 44 -#define S_R10 40 -#define S_R9 36 -#define S_R8 32 -#define S_R7 28 -#define S_R6 24 -#define S_R5 20 -#define S_R4 16 -#define S_R3 12 -#define S_R2 8 -#define S_R1 4 -#define S_R0 0 - -#define MODE_SVC 0x13 -#define I_BIT 0x80 - -/* - * use bad_save_user_regs for abort/prefetch/undef/swi ... - * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling - */ - - .macro bad_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Calling r0-r12 - ldr r2, IRQ_STACK_START_IN - ldmia r2, {r2 - r3} @ get pc, cpsr - add r0, sp, #S_FRAME_SIZE @ restore sp_SVC - - add r5, sp, #S_SP - mov r1, lr - stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr - mov r0, sp - .endm - - .macro irq_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Calling r0-r12 - add r7, sp, #S_PC - stmdb r7, {sp, lr}^ @ Calling SP, LR - str lr, [r7, #0] @ Save calling PC - mrs r6, spsr - str r6, [r7, #4] @ Save CPSR - str r0, [r7, #8] @ Save OLD_R0 - mov r0, sp - .endm - - .macro irq_restore_user_regs - ldmia sp, {r0 - lr}^ @ Calling r0 - lr - mov r0, r0 - ldr lr, [sp, #S_PC] @ Get PC - add sp, sp, #S_FRAME_SIZE - /* return & move spsr_svc into cpsr */ - subs pc, lr, #4 - .endm - - .macro get_bad_stack - ldr r13, IRQ_STACK_START_IN @ setup our mode stack - - str lr, [r13] @ save caller lr / spsr - mrs lr, spsr - str lr, [r13, #4] - - mov r13, #MODE_SVC @ prepare SVC-Mode - @ msr spsr_c, r13 - msr spsr, r13 - mov lr, pc - movs pc, lr - .endm - - .macro get_irq_stack @ setup IRQ stack - ldr sp, IRQ_STACK_START - .endm - - .macro get_fiq_stack @ setup FIQ stack - ldr sp, FIQ_STACK_START - .endm - -/* - * exception handlers - */ - .align 5 -undefined_instruction: - get_bad_stack - bad_save_user_regs - bl do_undefined_instruction - - .align 5 -software_interrupt: - get_bad_stack - bad_save_user_regs - bl do_software_interrupt - - .align 5 -prefetch_abort: - get_bad_stack - bad_save_user_regs - bl do_prefetch_abort - - .align 5 -data_abort: - get_bad_stack - bad_save_user_regs - bl do_data_abort - - .align 5 -not_used: - get_bad_stack - bad_save_user_regs - bl do_not_used - -#ifdef CONFIG_USE_IRQ - - .align 5 -irq: - get_irq_stack - irq_save_user_regs - bl do_irq - irq_restore_user_regs - - .align 5 -fiq: - get_fiq_stack - /* someone ought to write a more effiction fiq_save_user_regs */ - irq_save_user_regs - bl do_fiq - irq_restore_user_regs - -#else - - .align 5 -irq: - get_bad_stack - bad_save_user_regs - bl do_irq - - .align 5 -fiq: - get_bad_stack - bad_save_user_regs - bl do_fiq - -#endif diff --git a/arch/arm/cpu/arm926ejs/mxs/start.S b/arch/arm/cpu/arm926ejs/mxs/start.S index 34a0fcb462..9b60436539 100644 --- a/arch/arm/cpu/arm926ejs/mxs/start.S +++ b/arch/arm/cpu/arm926ejs/mxs/start.S @@ -27,70 +27,6 @@ /* ************************************************************************* * - * Jump vector table as in table 3.1 in [1] - * - ************************************************************************* - */ - - -.globl _start -_start: - b reset - b undefined_instruction - b software_interrupt - b prefetch_abort - b data_abort - b not_used - b irq - b fiq - -/* - * Vector table, located at address 0x20. - * This table allows the code running AFTER SPL, the U-Boot, to install it's - * interrupt handlers here. The problem is that the U-Boot is loaded into RAM, - * including it's interrupt vectoring table and the table at 0x0 is still the - * SPLs. So if interrupt happens in U-Boot, the SPLs interrupt vectoring table - * is still used. - */ -_vt_reset: - .word _reset -_vt_undefined_instruction: - .word _hang -_vt_software_interrupt: - .word _hang -_vt_prefetch_abort: - .word _hang -_vt_data_abort: - .word _hang -_vt_not_used: - .word _reset -_vt_irq: - .word _hang -_vt_fiq: - .word _hang - -reset: - ldr pc, _vt_reset -undefined_instruction: - ldr pc, _vt_undefined_instruction -software_interrupt: - ldr pc, _vt_software_interrupt -prefetch_abort: - ldr pc, _vt_prefetch_abort -data_abort: - ldr pc, _vt_data_abort -not_used: - ldr pc, _vt_not_used -irq: - ldr pc, _vt_irq -fiq: - ldr pc, _vt_fiq - - .balignl 16,0xdeadbeef - -/* - ************************************************************************* - * * Startup Code (reset vector) * * do important init only if we don't start from memory! @@ -101,28 +37,8 @@ fiq: ************************************************************************* */ -#ifdef CONFIG_USE_IRQ -/* IRQ stack memory (calculated at run-time) */ -.globl IRQ_STACK_START -IRQ_STACK_START: - .word 0x0badc0de - -/* IRQ stack memory (calculated at run-time) */ -.globl FIQ_STACK_START -FIQ_STACK_START: - .word 0x0badc0de -#endif - -/* IRQ stack memory (calculated at run-time) + 8 bytes */ -.globl IRQ_STACK_START_IN -IRQ_STACK_START_IN: - .word 0x0badc0de - -/* - * the actual reset code - */ - -_reset: + .globl reset +reset: /* * If the CPU is configured in "Wait JTAG connection mode", the stack * pointer is not configured and is zero. This will cause crash when @@ -179,7 +95,3 @@ _reset: mov r0, #0 bx lr - -_hang: -1: - bl 1b /* hang and never return */ diff --git a/arch/arm/cpu/arm926ejs/spear/start.S b/arch/arm/cpu/arm926ejs/spear/start.S index 7dbd5dbf99..290ac2e561 100644 --- a/arch/arm/cpu/arm926ejs/spear/start.S +++ b/arch/arm/cpu/arm926ejs/spear/start.S @@ -17,29 +17,6 @@ #include <config.h> -.globl _start -_start: - b reset - ldr pc, _undefined_instruction - ldr pc, _software_interrupt - ldr pc, _prefetch_abort - ldr pc, _data_abort - ldr pc, _not_used - ldr pc, _irq - ldr pc, _fiq - -_undefined_instruction: -_software_interrupt: -_prefetch_abort: -_data_abort: -_not_used: -_irq: -_fiq: - .word infinite_loop - -infinite_loop: - b infinite_loop - /* ************************************************************************* * @@ -53,9 +30,7 @@ infinite_loop: ************************************************************************* */ -/* - * the actual reset code - */ + .globl reset reset: /* diff --git a/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds b/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds index b6d0f65b66..c7ee19912f 100644 --- a/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds +++ b/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds @@ -21,6 +21,7 @@ SECTIONS . = ALIGN(4); .text : { + *(.vectors) arch/arm/cpu/arm926ejs/spear/start.o (.text*) *(.text*) } diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S index 0717327050..8eb249475e 100644 --- a/arch/arm/cpu/arm926ejs/start.S +++ b/arch/arm/cpu/arm926ejs/start.S @@ -23,75 +23,6 @@ /* ************************************************************************* * - * Jump vector table as in table 3.1 in [1] - * - ************************************************************************* - */ - - -#ifdef CONFIG_SYS_DV_NOR_BOOT_CFG -.globl _start -_start: -.globl _NOR_BOOT_CFG -_NOR_BOOT_CFG: - .word CONFIG_SYS_DV_NOR_BOOT_CFG - b reset -#else -.globl _start -_start: - b reset -#endif -#ifdef CONFIG_SPL_BUILD -/* No exception handlers in preloader */ - ldr pc, _hang - ldr pc, _hang - ldr pc, _hang - ldr pc, _hang - ldr pc, _hang - ldr pc, _hang - ldr pc, _hang - -_hang: - .word do_hang -/* pad to 64 byte boundary */ - .word 0x12345678 - .word 0x12345678 - .word 0x12345678 - .word 0x12345678 - .word 0x12345678 - .word 0x12345678 - .word 0x12345678 -#else - ldr pc, _undefined_instruction - ldr pc, _software_interrupt - ldr pc, _prefetch_abort - ldr pc, _data_abort - ldr pc, _not_used - ldr pc, _irq - ldr pc, _fiq - -_undefined_instruction: - .word undefined_instruction -_software_interrupt: - .word software_interrupt -_prefetch_abort: - .word prefetch_abort -_data_abort: - .word data_abort -_not_used: - .word not_used -_irq: - .word irq -_fiq: - .word fiq - -#endif /* CONFIG_SPL_BUILD */ - .balignl 16,0xdeadbeef - - -/* - ************************************************************************* - * * Startup Code (reset vector) * * do important init only if we don't start from memory! @@ -102,26 +33,7 @@ _fiq: ************************************************************************* */ -#ifdef CONFIG_USE_IRQ -/* IRQ stack memory (calculated at run-time) */ -.globl IRQ_STACK_START -IRQ_STACK_START: - .word 0x0badc0de - -/* IRQ stack memory (calculated at run-time) */ -.globl FIQ_STACK_START -FIQ_STACK_START: - .word 0x0badc0de -#endif - -/* IRQ stack memory (calculated at run-time) + 8 bytes */ -.globl IRQ_STACK_START_IN -IRQ_STACK_START_IN: - .word 0x0badc0de - -/* - * the actual reset code - */ + .globl reset reset: /* @@ -198,175 +110,3 @@ flush_dcache: mov lr, ip /* restore link */ mov pc, lr /* back to my caller */ #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ - -#ifndef CONFIG_SPL_BUILD -/* - ************************************************************************* - * - * Interrupt handling - * - ************************************************************************* - */ - -@ -@ IRQ stack frame. -@ -#define S_FRAME_SIZE 72 - -#define S_OLD_R0 68 -#define S_PSR 64 -#define S_PC 60 -#define S_LR 56 -#define S_SP 52 - -#define S_IP 48 -#define S_FP 44 -#define S_R10 40 -#define S_R9 36 -#define S_R8 32 -#define S_R7 28 -#define S_R6 24 -#define S_R5 20 -#define S_R4 16 -#define S_R3 12 -#define S_R2 8 -#define S_R1 4 -#define S_R0 0 - -#define MODE_SVC 0x13 -#define I_BIT 0x80 - -/* - * use bad_save_user_regs for abort/prefetch/undef/swi ... - * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling - */ - - .macro bad_save_user_regs - @ carve out a frame on current user stack - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 - ldr r2, IRQ_STACK_START_IN - @ get values for "aborted" pc and cpsr (into parm regs) - ldmia r2, {r2 - r3} - add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack - add r5, sp, #S_SP - mov r1, lr - stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr - mov r0, sp @ save current stack into r0 (param register) - .endm - - .macro irq_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Calling r0-r12 - @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good. - add r8, sp, #S_PC - stmdb r8, {sp, lr}^ @ Calling SP, LR - str lr, [r8, #0] @ Save calling PC - mrs r6, spsr - str r6, [r8, #4] @ Save CPSR - str r0, [r8, #8] @ Save OLD_R0 - mov r0, sp - .endm - - .macro irq_restore_user_regs - ldmia sp, {r0 - lr}^ @ Calling r0 - lr - mov r0, r0 - ldr lr, [sp, #S_PC] @ Get PC - add sp, sp, #S_FRAME_SIZE - subs pc, lr, #4 @ return & move spsr_svc into cpsr - .endm - - .macro get_bad_stack - ldr r13, IRQ_STACK_START_IN @ setup our mode stack - - str lr, [r13] @ save caller lr in position 0 of saved stack - mrs lr, spsr @ get the spsr - str lr, [r13, #4] @ save spsr in position 1 of saved stack - mov r13, #MODE_SVC @ prepare SVC-Mode - @ msr spsr_c, r13 - msr spsr, r13 @ switch modes, make sure moves will execute - mov lr, pc @ capture return pc - movs pc, lr @ jump to next instruction & switch modes. - .endm - - .macro get_irq_stack @ setup IRQ stack - ldr sp, IRQ_STACK_START - .endm - - .macro get_fiq_stack @ setup FIQ stack - ldr sp, FIQ_STACK_START - .endm -#endif /* CONFIG_SPL_BUILD */ - -/* - * exception handlers - */ -#ifdef CONFIG_SPL_BUILD - .align 5 -do_hang: -1: - bl 1b /* hang and never return */ -#else /* !CONFIG_SPL_BUILD */ - .align 5 -undefined_instruction: - get_bad_stack - bad_save_user_regs - bl do_undefined_instruction - - .align 5 -software_interrupt: - get_bad_stack - bad_save_user_regs - bl do_software_interrupt - - .align 5 -prefetch_abort: - get_bad_stack - bad_save_user_regs - bl do_prefetch_abort - - .align 5 -data_abort: - get_bad_stack - bad_save_user_regs - bl do_data_abort - - .align 5 -not_used: - get_bad_stack - bad_save_user_regs - bl do_not_used - -#ifdef CONFIG_USE_IRQ - - .align 5 -irq: - get_irq_stack - irq_save_user_regs - bl do_irq - irq_restore_user_regs - - .align 5 -fiq: - get_fiq_stack - /* someone ought to write a more effiction fiq_save_user_regs */ - irq_save_user_regs - bl do_fiq - irq_restore_user_regs - -#else - - .align 5 -irq: - get_bad_stack - bad_save_user_regs - bl do_irq - - .align 5 -fiq: - get_bad_stack - bad_save_user_regs - bl do_fiq - -#endif -#endif /* CONFIG_SPL_BUILD */ diff --git a/arch/arm/cpu/arm946es/cpu.c b/arch/arm/cpu/arm946es/cpu.c index 0c8d92d737..e20e5a89aa 100644 --- a/arch/arm/cpu/arm946es/cpu.c +++ b/arch/arm/cpu/arm946es/cpu.c @@ -16,6 +16,7 @@ #include <common.h> #include <command.h> #include <asm/system.h> +#include <asm/io.h> static void cache_flush(void); @@ -51,3 +52,15 @@ static void cache_flush (void) asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); asm ("mcr p15, 0, %0, c7, c6, 0": :"r" (i)); } + +#ifndef CONFIG_INTEGRATOR + +__attribute__((noreturn)) void reset_cpu(ulong addr __attribute__((unused))) +{ + writew(0x0, 0xfffece10); + writew(0x8, 0xfffece10); + for (;;) + ; +} + +#endif /* #ifdef CONFIG_INTEGRATOR */ diff --git a/arch/arm/cpu/arm946es/start.S b/arch/arm/cpu/arm946es/start.S index 7d50145836..41123716a7 100644 --- a/arch/arm/cpu/arm946es/start.S +++ b/arch/arm/cpu/arm946es/start.S @@ -22,45 +22,6 @@ /* ************************************************************************* * - * Jump vector table as in table 3.1 in [1] - * - ************************************************************************* - */ - - -.globl _start -_start: - b reset - ldr pc, _undefined_instruction - ldr pc, _software_interrupt - ldr pc, _prefetch_abort - ldr pc, _data_abort - ldr pc, _not_used - ldr pc, _irq - ldr pc, _fiq - -_undefined_instruction: - .word undefined_instruction -_software_interrupt: - .word software_interrupt -_prefetch_abort: - .word prefetch_abort -_data_abort: - .word data_abort -_not_used: - .word not_used -_irq: - .word irq -_fiq: - .word fiq - - .balignl 16,0xdeadbeef - -_vectors_end: - -/* - ************************************************************************* - * * Startup Code (reset vector) * * do important init only if we don't start from memory! @@ -71,26 +32,7 @@ _vectors_end: ************************************************************************* */ -#ifdef CONFIG_USE_IRQ -/* IRQ stack memory (calculated at run-time) */ -.globl IRQ_STACK_START -IRQ_STACK_START: - .word 0x0badc0de - -/* IRQ stack memory (calculated at run-time) */ -.globl FIQ_STACK_START -FIQ_STACK_START: - .word 0x0badc0de -#endif - -/* IRQ stack memory (calculated at run-time) + 8 bytes */ -.globl IRQ_STACK_START_IN -IRQ_STACK_START_IN: - .word 0x0badc0de - -/* - * the actual reset code - */ + .globl reset reset: /* @@ -157,189 +99,3 @@ cpu_init_crit: mov lr, ip /* restore link */ mov pc, lr /* back to my caller */ #endif -/* - ************************************************************************* - * - * Interrupt handling - * - ************************************************************************* - */ - -@ -@ IRQ stack frame. -@ -#define S_FRAME_SIZE 72 - -#define S_OLD_R0 68 -#define S_PSR 64 -#define S_PC 60 -#define S_LR 56 -#define S_SP 52 - -#define S_IP 48 -#define S_FP 44 -#define S_R10 40 -#define S_R9 36 -#define S_R8 32 -#define S_R7 28 -#define S_R6 24 -#define S_R5 20 -#define S_R4 16 -#define S_R3 12 -#define S_R2 8 -#define S_R1 4 -#define S_R0 0 - -#define MODE_SVC 0x13 -#define I_BIT 0x80 - -/* - * use bad_save_user_regs for abort/prefetch/undef/swi ... - * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling - */ - - .macro bad_save_user_regs - @ carve out a frame on current user stack - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 - - ldr r2, IRQ_STACK_START_IN - @ get values for "aborted" pc and cpsr (into parm regs) - ldmia r2, {r2 - r3} - add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack - add r5, sp, #S_SP - mov r1, lr - stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr - mov r0, sp @ save current stack into r0 (param register) - .endm - - .macro irq_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Calling r0-r12 - @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good. - add r8, sp, #S_PC - stmdb r8, {sp, lr}^ @ Calling SP, LR - str lr, [r8, #0] @ Save calling PC - mrs r6, spsr - str r6, [r8, #4] @ Save CPSR - str r0, [r8, #8] @ Save OLD_R0 - mov r0, sp - .endm - - .macro irq_restore_user_regs - ldmia sp, {r0 - lr}^ @ Calling r0 - lr - mov r0, r0 - ldr lr, [sp, #S_PC] @ Get PC - add sp, sp, #S_FRAME_SIZE - subs pc, lr, #4 @ return & move spsr_svc into cpsr - .endm - - .macro get_bad_stack - ldr r13, IRQ_STACK_START_IN @ setup our mode stack - - str lr, [r13] @ save caller lr in position 0 of saved stack - mrs lr, spsr @ get the spsr - str lr, [r13, #4] @ save spsr in position 1 of saved stack - mov r13, #MODE_SVC @ prepare SVC-Mode - @ msr spsr_c, r13 - msr spsr, r13 @ switch modes, make sure moves will execute - mov lr, pc @ capture return pc - movs pc, lr @ jump to next instruction & switch modes. - .endm - - .macro get_irq_stack @ setup IRQ stack - ldr sp, IRQ_STACK_START - .endm - - .macro get_fiq_stack @ setup FIQ stack - ldr sp, FIQ_STACK_START - .endm - -/* - * exception handlers - */ - .align 5 -undefined_instruction: - get_bad_stack - bad_save_user_regs - bl do_undefined_instruction - - .align 5 -software_interrupt: - get_bad_stack - bad_save_user_regs - bl do_software_interrupt - - .align 5 -prefetch_abort: - get_bad_stack - bad_save_user_regs - bl do_prefetch_abort - - .align 5 -data_abort: - get_bad_stack - bad_save_user_regs - bl do_data_abort - - .align 5 -not_used: - get_bad_stack - bad_save_user_regs - bl do_not_used - -#ifdef CONFIG_USE_IRQ - - .align 5 -irq: - get_irq_stack - irq_save_user_regs - bl do_irq - irq_restore_user_regs - - .align 5 -fiq: - get_fiq_stack - /* someone ought to write a more effiction fiq_save_user_regs */ - irq_save_user_regs - bl do_fiq - irq_restore_user_regs - -#else - - .align 5 -irq: - get_bad_stack - bad_save_user_regs - bl do_irq - - .align 5 -fiq: - get_bad_stack - bad_save_user_regs - bl do_fiq - -#endif - -# ifdef CONFIG_INTEGRATOR - - /* Satisfied by general board level routine */ - -#else - - .align 5 -.globl reset_cpu -reset_cpu: - - ldr r1, rstctl1 /* get clkm1 reset ctl */ - mov r3, #0x0 - strh r3, [r1] /* clear it */ - mov r3, #0x8 - strh r3, [r1] /* force dsp+arm reset */ -_loop_forever: - b _loop_forever - -rstctl1: - .word 0xfffece10 - -#endif /* #ifdef CONFIG_INTEGRATOR */ diff --git a/arch/arm/cpu/arm_intcm/start.S b/arch/arm/cpu/arm_intcm/start.S index 7404ea7348..c0c07b6a11 100644 --- a/arch/arm/cpu/arm_intcm/start.S +++ b/arch/arm/cpu/arm_intcm/start.S @@ -21,42 +21,6 @@ /* ************************************************************************* * - * Jump vector table - * - ************************************************************************* - */ - -.globl _start -_start: - b reset - ldr pc, _undefined_instruction - ldr pc, _software_interrupt - ldr pc, _prefetch_abort - ldr pc, _data_abort - ldr pc, _not_used - ldr pc, _irq - ldr pc, _fiq - -_undefined_instruction: - .word undefined_instruction -_software_interrupt: - .word software_interrupt -_prefetch_abort: - .word prefetch_abort -_data_abort: - .word data_abort -_not_used: - .word not_used -_irq: - .word irq -_fiq: - .word fiq - - .balignl 16,0xdeadbeef - -/* - ************************************************************************* - * * Startup Code (reset vector) * * do important init only if we don't start from memory! @@ -67,26 +31,7 @@ _fiq: ************************************************************************* */ -#ifdef CONFIG_USE_IRQ -/* IRQ stack memory (calculated at run-time) */ -.globl IRQ_STACK_START -IRQ_STACK_START: - .word 0x0badc0de - -/* IRQ stack memory (calculated at run-time) */ -.globl FIQ_STACK_START -FIQ_STACK_START: - .word 0x0badc0de -#endif - -/* IRQ stack memory (calculated at run-time) + 8 bytes */ -.globl IRQ_STACK_START_IN -IRQ_STACK_START_IN: - .word 0x0badc0de - -/* - * the actual reset code - */ + .globl reset reset: /* @@ -132,174 +77,3 @@ cpu_init_crit: */ mov pc, lr /* back to my caller */ #endif -/* - ************************************************************************* - * - * Interrupt handling - * - ************************************************************************* - */ - -@ -@ IRQ stack frame. -@ -#define S_FRAME_SIZE 72 - -#define S_OLD_R0 68 -#define S_PSR 64 -#define S_PC 60 -#define S_LR 56 -#define S_SP 52 - -#define S_IP 48 -#define S_FP 44 -#define S_R10 40 -#define S_R9 36 -#define S_R8 32 -#define S_R7 28 -#define S_R6 24 -#define S_R5 20 -#define S_R4 16 -#define S_R3 12 -#define S_R2 8 -#define S_R1 4 -#define S_R0 0 - -#define MODE_SVC 0x13 -#define I_BIT 0x80 - -/* - * use bad_save_user_regs for abort/prefetch/undef/swi ... - * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling - */ - - .macro bad_save_user_regs - @ carve out a frame on current user stack - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 - - ldr r2, IRQ_STACK_START_IN - @ get values for "aborted" pc and cpsr (into parm regs) - ldmia r2, {r2 - r3} - add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack - add r5, sp, #S_SP - mov r1, lr - stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr - mov r0, sp @ save current stack into r0 (param register) - .endm - - .macro irq_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Calling r0-r12 - @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good. - add r8, sp, #S_PC - stmdb r8, {sp, lr}^ @ Calling SP, LR - str lr, [r8, #0] @ Save calling PC - mrs r6, spsr - str r6, [r8, #4] @ Save CPSR - str r0, [r8, #8] @ Save OLD_R0 - mov r0, sp - .endm - - .macro irq_restore_user_regs - ldmia sp, {r0 - lr}^ @ Calling r0 - lr - mov r0, r0 - ldr lr, [sp, #S_PC] @ Get PC - add sp, sp, #S_FRAME_SIZE - subs pc, lr, #4 @ return & move spsr_svc into cpsr - .endm - - .macro get_bad_stack - ldr r13, IRQ_STACK_START_IN @ setup our mode stack - - str lr, [r13] @ save caller lr in position 0 of saved stack - mrs lr, spsr @ get the spsr - str lr, [r13, #4] @ save spsr in position 1 of saved stack - mov r13, #MODE_SVC @ prepare SVC-Mode - @ msr spsr_c, r13 - msr spsr, r13 @ switch modes, make sure moves will execute - mov lr, pc @ capture return pc - movs pc, lr @ jump to next instruction & switch modes. - .endm - - .macro get_irq_stack @ setup IRQ stack - ldr sp, IRQ_STACK_START - .endm - - .macro get_fiq_stack @ setup FIQ stack - ldr sp, FIQ_STACK_START - .endm - -/* - * exception handlers - */ - .align 5 -.globl undefined_instruction -undefined_instruction: - get_bad_stack - bad_save_user_regs - bl do_undefined_instruction - - .align 5 -.globl software_interrupt -software_interrupt: - get_bad_stack - bad_save_user_regs - bl do_software_interrupt - - .align 5 -.globl prefetch_abort -prefetch_abort: - get_bad_stack - bad_save_user_regs - bl do_prefetch_abort - - .align 5 -.globl data_abort -data_abort: - get_bad_stack - bad_save_user_regs - bl do_data_abort - - .align 5 -.globl not_used -not_used: - get_bad_stack - bad_save_user_regs - bl do_not_used - -#ifdef CONFIG_USE_IRQ - .align 5 -.globl irq -irq: - get_irq_stack - irq_save_user_regs - bl do_irq - irq_restore_user_regs - - .align 5 -.globl fiq -fiq: - get_fiq_stack - /* someone ought to write a more effiction fiq_save_user_regs */ - irq_save_user_regs - bl do_fiq - irq_restore_user_regs - -#else - - .align 5 -.globl irq -irq: - get_bad_stack - bad_save_user_regs - bl do_irq - - .align 5 -.globl fiq -fiq: - get_bad_stack - bad_save_user_regs - bl do_fiq - -#endif diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c index 9edb47502c..ee7c2e5a4b 100644 --- a/arch/arm/cpu/armv7/exynos/pinmux.c +++ b/arch/arm/cpu/armv7/exynos/pinmux.c @@ -13,30 +13,23 @@ static void exynos5_uart_config(int peripheral) { - struct exynos5_gpio_part1 *gpio1 = - (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); - struct s5p_gpio_bank *bank; int i, start, count; switch (peripheral) { case PERIPH_ID_UART0: - bank = &gpio1->a0; - start = 0; + start = EXYNOS5_GPIO_A00; count = 4; break; case PERIPH_ID_UART1: - bank = &gpio1->d0; - start = 0; + start = EXYNOS5_GPIO_D00; count = 4; break; case PERIPH_ID_UART2: - bank = &gpio1->a1; - start = 0; + start = EXYNOS5_GPIO_A10; count = 4; break; case PERIPH_ID_UART3: - bank = &gpio1->a1; - start = 4; + start = EXYNOS5_GPIO_A14; count = 2; break; default: @@ -44,37 +37,30 @@ static void exynos5_uart_config(int peripheral) return; } for (i = start; i < start + count; i++) { - s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE); - s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); + gpio_set_pull(i, S5P_GPIO_PULL_NONE); + gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2)); } } static void exynos5420_uart_config(int peripheral) { - struct exynos5420_gpio_part1 *gpio1 = - (struct exynos5420_gpio_part1 *)samsung_get_base_gpio_part1(); - struct s5p_gpio_bank *bank; int i, start, count; switch (peripheral) { case PERIPH_ID_UART0: - bank = &gpio1->a0; - start = 0; + start = EXYNOS5420_GPIO_A00; count = 4; break; case PERIPH_ID_UART1: - bank = &gpio1->a0; - start = 4; + start = EXYNOS5420_GPIO_A04; count = 4; break; case PERIPH_ID_UART2: - bank = &gpio1->a1; - start = 0; + start = EXYNOS5420_GPIO_A10; count = 4; break; case PERIPH_ID_UART3: - bank = &gpio1->a1; - start = 4; + start = EXYNOS5420_GPIO_A14; count = 2; break; default: @@ -83,64 +69,59 @@ static void exynos5420_uart_config(int peripheral) } for (i = start; i < start + count; i++) { - s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE); - s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); + gpio_set_pull(i, S5P_GPIO_PULL_NONE); + gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2)); } } static int exynos5_mmc_config(int peripheral, int flags) { - struct exynos5_gpio_part1 *gpio1 = - (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); - struct s5p_gpio_bank *bank, *bank_ext; - int i, start = 0, gpio_func = 0; + int i, start, start_ext, gpio_func = 0; switch (peripheral) { case PERIPH_ID_SDMMC0: - bank = &gpio1->c0; - bank_ext = &gpio1->c1; - start = 0; - gpio_func = GPIO_FUNC(0x2); + start = EXYNOS5_GPIO_C00; + start_ext = EXYNOS5_GPIO_C10; + gpio_func = S5P_GPIO_FUNC(0x2); break; case PERIPH_ID_SDMMC1: - bank = &gpio1->c2; - bank_ext = NULL; + start = EXYNOS5_GPIO_C20; + start_ext = 0; break; case PERIPH_ID_SDMMC2: - bank = &gpio1->c3; - bank_ext = &gpio1->c4; - start = 3; - gpio_func = GPIO_FUNC(0x3); + start = EXYNOS5_GPIO_C30; + start_ext = EXYNOS5_GPIO_C43; + gpio_func = S5P_GPIO_FUNC(0x3); break; case PERIPH_ID_SDMMC3: - bank = &gpio1->c4; - bank_ext = NULL; + start = EXYNOS5_GPIO_C40; + start_ext = 0; break; default: debug("%s: invalid peripheral %d", __func__, peripheral); return -1; } - if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) { + if ((flags & PINMUX_FLAG_8BIT_MODE) && !start_ext) { debug("SDMMC device %d does not support 8bit mode", peripheral); return -1; } if (flags & PINMUX_FLAG_8BIT_MODE) { - for (i = start; i <= (start + 3); i++) { - s5p_gpio_cfg_pin(bank_ext, i, gpio_func); - s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP); - s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X); + for (i = start_ext; i <= (start_ext + 3); i++) { + gpio_cfg_pin(i, gpio_func); + gpio_set_pull(i, S5P_GPIO_PULL_UP); + gpio_set_drv(i, S5P_GPIO_DRV_4X); } } - for (i = 0; i < 2; i++) { - s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); - s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE); - s5p_gpio_set_drv(bank, i, GPIO_DRV_4X); + for (i = start; i < (start + 2); i++) { + gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2)); + gpio_set_pull(i, S5P_GPIO_PULL_NONE); + gpio_set_drv(i, S5P_GPIO_DRV_4X); } - for (i = 3; i <= 6; i++) { - s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); - s5p_gpio_set_pull(bank, i, GPIO_PULL_UP); - s5p_gpio_set_drv(bank, i, GPIO_DRV_4X); + for (i = (start + 3); i <= (start + 6); i++) { + gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2)); + gpio_set_pull(i, S5P_GPIO_PULL_UP); + gpio_set_drv(i, S5P_GPIO_DRV_4X); } return 0; @@ -148,26 +129,20 @@ static int exynos5_mmc_config(int peripheral, int flags) static int exynos5420_mmc_config(int peripheral, int flags) { - struct exynos5420_gpio_part3 *gpio3 = - (struct exynos5420_gpio_part3 *)samsung_get_base_gpio_part3(); - struct s5p_gpio_bank *bank = NULL, *bank_ext = NULL; - int i, start; + int i, start = 0, start_ext = 0; switch (peripheral) { case PERIPH_ID_SDMMC0: - bank = &gpio3->c0; - bank_ext = &gpio3->c3; - start = 0; + start = EXYNOS5420_GPIO_C00; + start_ext = EXYNOS5420_GPIO_C30; break; case PERIPH_ID_SDMMC1: - bank = &gpio3->c1; - bank_ext = &gpio3->d1; - start = 4; + start = EXYNOS5420_GPIO_C10; + start_ext = EXYNOS5420_GPIO_D14; break; case PERIPH_ID_SDMMC2: - bank = &gpio3->c2; - bank_ext = NULL; - start = 0; + start = EXYNOS5420_GPIO_C20; + start_ext = 0; break; default: start = 0; @@ -175,41 +150,41 @@ static int exynos5420_mmc_config(int peripheral, int flags) return -1; } - if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) { + if ((flags & PINMUX_FLAG_8BIT_MODE) && !start_ext) { debug("SDMMC device %d does not support 8bit mode", peripheral); return -1; } if (flags & PINMUX_FLAG_8BIT_MODE) { - for (i = start; i <= (start + 3); i++) { - s5p_gpio_cfg_pin(bank_ext, i, GPIO_FUNC(0x2)); - s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP); - s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X); + for (i = start_ext; i <= (start_ext + 3); i++) { + gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2)); + gpio_set_pull(i, S5P_GPIO_PULL_UP); + gpio_set_drv(i, S5P_GPIO_DRV_4X); } } - for (i = 0; i < 3; i++) { + for (i = start; i < (start + 3); i++) { /* * MMC0 is intended to be used for eMMC. The * card detect pin is used as a VDDEN signal to * power on the eMMC. The 5420 iROM makes * this same assumption. */ - if ((peripheral == PERIPH_ID_SDMMC0) && (i == 2)) { - s5p_gpio_set_value(bank, i, 1); - s5p_gpio_cfg_pin(bank, i, GPIO_OUTPUT); + if ((peripheral == PERIPH_ID_SDMMC0) && (i == (start + 2))) { + gpio_set_value(i, 1); + gpio_cfg_pin(i, S5P_GPIO_OUTPUT); } else { - s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); + gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2)); } - s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE); - s5p_gpio_set_drv(bank, i, GPIO_DRV_4X); + gpio_set_pull(i, S5P_GPIO_PULL_NONE); + gpio_set_drv(i, S5P_GPIO_DRV_4X); } - for (i = 3; i <= 6; i++) { - s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); - s5p_gpio_set_pull(bank, i, GPIO_PULL_UP); - s5p_gpio_set_drv(bank, i, GPIO_DRV_4X); + for (i = (start + 3); i <= (start + 6); i++) { + gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2)); + gpio_set_pull(i, S5P_GPIO_PULL_UP); + gpio_set_drv(i, S5P_GPIO_DRV_4X); } return 0; @@ -217,8 +192,6 @@ static int exynos5420_mmc_config(int peripheral, int flags) static void exynos5_sromc_config(int flags) { - struct exynos5_gpio_part1 *gpio1 = - (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); int i; /* @@ -236,13 +209,13 @@ static void exynos5_sromc_config(int flags) * GPY1[2] SROM_WAIT(2) * GPY1[3] EBI_DATA_RDn(2) */ - s5p_gpio_cfg_pin(&gpio1->y0, (flags & PINMUX_FLAG_BANK), - GPIO_FUNC(2)); - s5p_gpio_cfg_pin(&gpio1->y0, 4, GPIO_FUNC(2)); - s5p_gpio_cfg_pin(&gpio1->y0, 5, GPIO_FUNC(2)); + gpio_cfg_pin(EXYNOS5_GPIO_Y00 + (flags & PINMUX_FLAG_BANK), + S5P_GPIO_FUNC(2)); + gpio_cfg_pin(EXYNOS5_GPIO_Y04, S5P_GPIO_FUNC(2)); + gpio_cfg_pin(EXYNOS5_GPIO_Y05, S5P_GPIO_FUNC(2)); for (i = 0; i < 4; i++) - s5p_gpio_cfg_pin(&gpio1->y1, i, GPIO_FUNC(2)); + gpio_cfg_pin(EXYNOS5_GPIO_Y10 + i, S5P_GPIO_FUNC(2)); /* * EBI: 8 Addrss Lines @@ -277,108 +250,101 @@ static void exynos5_sromc_config(int flags) * GPY6[7] EBI_DATA[15](2) */ for (i = 0; i < 8; i++) { - s5p_gpio_cfg_pin(&gpio1->y3, i, GPIO_FUNC(2)); - s5p_gpio_set_pull(&gpio1->y3, i, GPIO_PULL_UP); + gpio_cfg_pin(EXYNOS5_GPIO_Y30 + i, S5P_GPIO_FUNC(2)); + gpio_set_pull(EXYNOS5_GPIO_Y30 + i, S5P_GPIO_PULL_UP); - s5p_gpio_cfg_pin(&gpio1->y5, i, GPIO_FUNC(2)); - s5p_gpio_set_pull(&gpio1->y5, i, GPIO_PULL_UP); + gpio_cfg_pin(EXYNOS5_GPIO_Y50 + i, S5P_GPIO_FUNC(2)); + gpio_set_pull(EXYNOS5_GPIO_Y50 + i, S5P_GPIO_PULL_UP); - s5p_gpio_cfg_pin(&gpio1->y6, i, GPIO_FUNC(2)); - s5p_gpio_set_pull(&gpio1->y6, i, GPIO_PULL_UP); + gpio_cfg_pin(EXYNOS5_GPIO_Y60 + i, S5P_GPIO_FUNC(2)); + gpio_set_pull(EXYNOS5_GPIO_Y60 + i, S5P_GPIO_PULL_UP); } } static void exynos5_i2c_config(int peripheral, int flags) { - - struct exynos5_gpio_part1 *gpio1 = - (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); - switch (peripheral) { case PERIPH_ID_I2C0: - s5p_gpio_cfg_pin(&gpio1->b3, 0, GPIO_FUNC(0x2)); - s5p_gpio_cfg_pin(&gpio1->b3, 1, GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS5_GPIO_B30, S5P_GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS5_GPIO_B31, S5P_GPIO_FUNC(0x2)); break; case PERIPH_ID_I2C1: - s5p_gpio_cfg_pin(&gpio1->b3, 2, GPIO_FUNC(0x2)); - s5p_gpio_cfg_pin(&gpio1->b3, 3, GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS5_GPIO_B32, S5P_GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS5_GPIO_B33, S5P_GPIO_FUNC(0x2)); break; case PERIPH_ID_I2C2: - s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5_GPIO_A06, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5_GPIO_A07, S5P_GPIO_FUNC(0x3)); break; case PERIPH_ID_I2C3: - s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5_GPIO_A12, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5_GPIO_A13, S5P_GPIO_FUNC(0x3)); break; case PERIPH_ID_I2C4: - s5p_gpio_cfg_pin(&gpio1->a2, 0, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->a2, 1, GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5_GPIO_A20, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5_GPIO_A21, S5P_GPIO_FUNC(0x3)); break; case PERIPH_ID_I2C5: - s5p_gpio_cfg_pin(&gpio1->a2, 2, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->a2, 3, GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5_GPIO_A22, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5_GPIO_A23, S5P_GPIO_FUNC(0x3)); break; case PERIPH_ID_I2C6: - s5p_gpio_cfg_pin(&gpio1->b1, 3, GPIO_FUNC(0x4)); - s5p_gpio_cfg_pin(&gpio1->b1, 4, GPIO_FUNC(0x4)); + gpio_cfg_pin(EXYNOS5_GPIO_B13, S5P_GPIO_FUNC(0x4)); + gpio_cfg_pin(EXYNOS5_GPIO_B14, S5P_GPIO_FUNC(0x4)); break; case PERIPH_ID_I2C7: - s5p_gpio_cfg_pin(&gpio1->b2, 2, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->b2, 3, GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5_GPIO_B22, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5_GPIO_B23, S5P_GPIO_FUNC(0x3)); break; } } static void exynos5420_i2c_config(int peripheral) { - struct exynos5420_gpio_part1 *gpio1 = - (struct exynos5420_gpio_part1 *)samsung_get_base_gpio_part1(); - switch (peripheral) { case PERIPH_ID_I2C0: - s5p_gpio_cfg_pin(&gpio1->b3, 0, GPIO_FUNC(0x2)); - s5p_gpio_cfg_pin(&gpio1->b3, 1, GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS5420_GPIO_B30, S5P_GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS5420_GPIO_B31, S5P_GPIO_FUNC(0x2)); break; case PERIPH_ID_I2C1: - s5p_gpio_cfg_pin(&gpio1->b3, 2, GPIO_FUNC(0x2)); - s5p_gpio_cfg_pin(&gpio1->b3, 3, GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS5420_GPIO_B32, S5P_GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS5420_GPIO_B33, S5P_GPIO_FUNC(0x2)); break; case PERIPH_ID_I2C2: - s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5420_GPIO_A06, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5420_GPIO_A07, S5P_GPIO_FUNC(0x3)); break; case PERIPH_ID_I2C3: - s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5420_GPIO_A12, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5420_GPIO_A13, S5P_GPIO_FUNC(0x3)); break; case PERIPH_ID_I2C4: - s5p_gpio_cfg_pin(&gpio1->a2, 0, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->a2, 1, GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5420_GPIO_A20, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5420_GPIO_A21, S5P_GPIO_FUNC(0x3)); break; case PERIPH_ID_I2C5: - s5p_gpio_cfg_pin(&gpio1->a2, 2, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->a2, 3, GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5420_GPIO_A22, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5420_GPIO_A23, S5P_GPIO_FUNC(0x3)); break; case PERIPH_ID_I2C6: - s5p_gpio_cfg_pin(&gpio1->b1, 3, GPIO_FUNC(0x4)); - s5p_gpio_cfg_pin(&gpio1->b1, 4, GPIO_FUNC(0x4)); + gpio_cfg_pin(EXYNOS5420_GPIO_B13, S5P_GPIO_FUNC(0x4)); + gpio_cfg_pin(EXYNOS5420_GPIO_B14, S5P_GPIO_FUNC(0x4)); break; case PERIPH_ID_I2C7: - s5p_gpio_cfg_pin(&gpio1->b2, 2, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->b2, 3, GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5420_GPIO_B22, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5420_GPIO_B23, S5P_GPIO_FUNC(0x3)); break; case PERIPH_ID_I2C8: - s5p_gpio_cfg_pin(&gpio1->b3, 4, GPIO_FUNC(0x2)); - s5p_gpio_cfg_pin(&gpio1->b3, 5, GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS5420_GPIO_B34, S5P_GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS5420_GPIO_B35, S5P_GPIO_FUNC(0x2)); break; case PERIPH_ID_I2C9: - s5p_gpio_cfg_pin(&gpio1->b3, 6, GPIO_FUNC(0x2)); - s5p_gpio_cfg_pin(&gpio1->b3, 7, GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS5420_GPIO_B36, S5P_GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS5420_GPIO_B37, S5P_GPIO_FUNC(0x2)); break; case PERIPH_ID_I2C10: - s5p_gpio_cfg_pin(&gpio1->b4, 0, GPIO_FUNC(0x2)); - s5p_gpio_cfg_pin(&gpio1->b4, 1, GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS5420_GPIO_B40, S5P_GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS5420_GPIO_B41, S5P_GPIO_FUNC(0x2)); break; } } @@ -386,19 +352,15 @@ static void exynos5420_i2c_config(int peripheral) static void exynos5_i2s_config(int peripheral) { int i; - struct exynos5_gpio_part1 *gpio1 = - (struct exynos5_gpio_part1 *)samsung_get_base_gpio_part1(); - struct exynos5_gpio_part4 *gpio4 = - (struct exynos5_gpio_part4 *)samsung_get_base_gpio_part4(); switch (peripheral) { case PERIPH_ID_I2S0: for (i = 0; i < 5; i++) - s5p_gpio_cfg_pin(&gpio4->z, i, GPIO_FUNC(0x02)); + gpio_cfg_pin(EXYNOS5_GPIO_Z0 + i, S5P_GPIO_FUNC(0x02)); break; case PERIPH_ID_I2S1: for (i = 0; i < 5; i++) - s5p_gpio_cfg_pin(&gpio1->b0, i, GPIO_FUNC(0x02)); + gpio_cfg_pin(EXYNOS5_GPIO_B00 + i, S5P_GPIO_FUNC(0x02)); break; } } @@ -406,75 +368,57 @@ static void exynos5_i2s_config(int peripheral) void exynos5_spi_config(int peripheral) { int cfg = 0, pin = 0, i; - struct s5p_gpio_bank *bank = NULL; - struct exynos5_gpio_part1 *gpio1 = - (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); - struct exynos5_gpio_part2 *gpio2 = - (struct exynos5_gpio_part2 *) samsung_get_base_gpio_part2(); switch (peripheral) { case PERIPH_ID_SPI0: - bank = &gpio1->a2; - cfg = GPIO_FUNC(0x2); - pin = 0; + cfg = S5P_GPIO_FUNC(0x2); + pin = EXYNOS5_GPIO_A20; break; case PERIPH_ID_SPI1: - bank = &gpio1->a2; - cfg = GPIO_FUNC(0x2); - pin = 4; + cfg = S5P_GPIO_FUNC(0x2); + pin = EXYNOS5_GPIO_A24; break; case PERIPH_ID_SPI2: - bank = &gpio1->b1; - cfg = GPIO_FUNC(0x5); - pin = 1; + cfg = S5P_GPIO_FUNC(0x5); + pin = EXYNOS5_GPIO_B11; break; case PERIPH_ID_SPI3: - bank = &gpio2->f1; - cfg = GPIO_FUNC(0x2); - pin = 0; + cfg = S5P_GPIO_FUNC(0x2); + pin = EXYNOS5_GPIO_F10; break; case PERIPH_ID_SPI4: for (i = 0; i < 2; i++) { - s5p_gpio_cfg_pin(&gpio2->f0, i + 2, GPIO_FUNC(0x4)); - s5p_gpio_cfg_pin(&gpio2->e0, i + 4, GPIO_FUNC(0x4)); + gpio_cfg_pin(EXYNOS5_GPIO_F02 + i, S5P_GPIO_FUNC(0x4)); + gpio_cfg_pin(EXYNOS5_GPIO_E04 + i, S5P_GPIO_FUNC(0x4)); } break; } if (peripheral != PERIPH_ID_SPI4) { for (i = pin; i < pin + 4; i++) - s5p_gpio_cfg_pin(bank, i, cfg); + gpio_cfg_pin(i, cfg); } } void exynos5420_spi_config(int peripheral) { int cfg, pin, i; - struct s5p_gpio_bank *bank = NULL; - struct exynos5420_gpio_part1 *gpio1 = - (struct exynos5420_gpio_part1 *)samsung_get_base_gpio_part1(); - struct exynos5420_gpio_part4 *gpio4 = - (struct exynos5420_gpio_part4 *)samsung_get_base_gpio_part4(); switch (peripheral) { case PERIPH_ID_SPI0: - bank = &gpio1->a2; - cfg = GPIO_FUNC(0x2); - pin = 0; + pin = EXYNOS5420_GPIO_A20; + cfg = S5P_GPIO_FUNC(0x2); break; case PERIPH_ID_SPI1: - bank = &gpio1->a2; - cfg = GPIO_FUNC(0x2); - pin = 4; + pin = EXYNOS5420_GPIO_A24; + cfg = S5P_GPIO_FUNC(0x2); break; case PERIPH_ID_SPI2: - bank = &gpio1->b1; - cfg = GPIO_FUNC(0x5); - pin = 1; + pin = EXYNOS5420_GPIO_B11; + cfg = S5P_GPIO_FUNC(0x5); break; case PERIPH_ID_SPI3: - bank = &gpio4->f1; - cfg = GPIO_FUNC(0x2); - pin = 0; + pin = EXYNOS5420_GPIO_F10; + cfg = S5P_GPIO_FUNC(0x2); break; case PERIPH_ID_SPI4: cfg = 0; @@ -489,11 +433,13 @@ void exynos5420_spi_config(int peripheral) if (peripheral != PERIPH_ID_SPI4) { for (i = pin; i < pin + 4; i++) - s5p_gpio_cfg_pin(bank, i, cfg); + gpio_cfg_pin(i, cfg); } else { for (i = 0; i < 2; i++) { - s5p_gpio_cfg_pin(&gpio4->f0, i + 2, GPIO_FUNC(0x4)); - s5p_gpio_cfg_pin(&gpio4->e0, i + 4, GPIO_FUNC(0x4)); + gpio_cfg_pin(EXYNOS5420_GPIO_F02 + i, + S5P_GPIO_FUNC(0x4)); + gpio_cfg_pin(EXYNOS5420_GPIO_E04 + i, + S5P_GPIO_FUNC(0x4)); } } } @@ -588,76 +534,70 @@ static int exynos5420_pinmux_config(int peripheral, int flags) static void exynos4_i2c_config(int peripheral, int flags) { - struct exynos4_gpio_part1 *gpio1 = - (struct exynos4_gpio_part1 *) samsung_get_base_gpio_part1(); - switch (peripheral) { case PERIPH_ID_I2C0: - s5p_gpio_cfg_pin(&gpio1->d1, 0, GPIO_FUNC(0x2)); - s5p_gpio_cfg_pin(&gpio1->d1, 1, GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS4_GPIO_D10, S5P_GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS4_GPIO_D11, S5P_GPIO_FUNC(0x2)); break; case PERIPH_ID_I2C1: - s5p_gpio_cfg_pin(&gpio1->d1, 2, GPIO_FUNC(0x2)); - s5p_gpio_cfg_pin(&gpio1->d1, 3, GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS4_GPIO_D12, S5P_GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS4_GPIO_D13, S5P_GPIO_FUNC(0x2)); break; case PERIPH_ID_I2C2: - s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS4_GPIO_A06, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS4_GPIO_A07, S5P_GPIO_FUNC(0x3)); break; case PERIPH_ID_I2C3: - s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS4_GPIO_A12, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS4_GPIO_A13, S5P_GPIO_FUNC(0x3)); break; case PERIPH_ID_I2C4: - s5p_gpio_cfg_pin(&gpio1->b, 2, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->b, 3, GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS4_GPIO_B2, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS4_GPIO_B3, S5P_GPIO_FUNC(0x3)); break; case PERIPH_ID_I2C5: - s5p_gpio_cfg_pin(&gpio1->b, 6, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->b, 7, GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS4_GPIO_B6, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS4_GPIO_B7, S5P_GPIO_FUNC(0x3)); break; case PERIPH_ID_I2C6: - s5p_gpio_cfg_pin(&gpio1->c1, 3, GPIO_FUNC(0x4)); - s5p_gpio_cfg_pin(&gpio1->c1, 4, GPIO_FUNC(0x4)); + gpio_cfg_pin(EXYNOS4_GPIO_C13, S5P_GPIO_FUNC(0x4)); + gpio_cfg_pin(EXYNOS4_GPIO_C14, S5P_GPIO_FUNC(0x4)); break; case PERIPH_ID_I2C7: - s5p_gpio_cfg_pin(&gpio1->d0, 2, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->d0, 3, GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS4_GPIO_D02, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS4_GPIO_D03, S5P_GPIO_FUNC(0x3)); break; } } static int exynos4_mmc_config(int peripheral, int flags) { - struct exynos4_gpio_part2 *gpio2 = - (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); - struct s5p_gpio_bank *bank, *bank_ext; - int i; + int i, start = 0, start_ext = 0; switch (peripheral) { case PERIPH_ID_SDMMC0: - bank = &gpio2->k0; - bank_ext = &gpio2->k1; + start = EXYNOS4_GPIO_K00; + start_ext = EXYNOS4_GPIO_K13; break; case PERIPH_ID_SDMMC2: - bank = &gpio2->k2; - bank_ext = &gpio2->k3; + start = EXYNOS4_GPIO_K20; + start_ext = EXYNOS4_GPIO_K33; break; default: return -1; } - for (i = 0; i < 7; i++) { - if (i == 2) + for (i = start; i < (start + 7); i++) { + if (i == (start + 2)) continue; - s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); - s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE); - s5p_gpio_set_drv(bank, i, GPIO_DRV_4X); + gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2)); + gpio_set_pull(i, S5P_GPIO_PULL_NONE); + gpio_set_drv(i, S5P_GPIO_DRV_4X); } if (flags & PINMUX_FLAG_8BIT_MODE) { - for (i = 3; i < 7; i++) { - s5p_gpio_cfg_pin(bank_ext, i, GPIO_FUNC(0x3)); - s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_NONE); - s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X); + for (i = start_ext; i < (start_ext + 4); i++) { + gpio_cfg_pin(i, S5P_GPIO_FUNC(0x3)); + gpio_set_pull(i, S5P_GPIO_PULL_NONE); + gpio_set_drv(i, S5P_GPIO_DRV_4X); } } @@ -666,41 +606,138 @@ static int exynos4_mmc_config(int peripheral, int flags) static void exynos4_uart_config(int peripheral) { - struct exynos4_gpio_part1 *gpio1 = - (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1(); - struct s5p_gpio_bank *bank; int i, start, count; switch (peripheral) { case PERIPH_ID_UART0: - bank = &gpio1->a0; - start = 0; + start = EXYNOS4_GPIO_A00; count = 4; break; case PERIPH_ID_UART1: - bank = &gpio1->a0; - start = 4; + start = EXYNOS4_GPIO_A04; count = 4; break; case PERIPH_ID_UART2: - bank = &gpio1->a1; - start = 0; + start = EXYNOS4_GPIO_A10; count = 4; break; case PERIPH_ID_UART3: - bank = &gpio1->a1; - start = 4; + start = EXYNOS4_GPIO_A14; count = 2; break; default: debug("%s: invalid peripheral %d", __func__, peripheral); return; } - for (i = start; i < start + count; i++) { - s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE); - s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); + for (i = start; i < (start + count); i++) { + gpio_set_pull(i, S5P_GPIO_PULL_NONE); + gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2)); + } +} + +static void exynos4x12_i2c_config(int peripheral, int flags) +{ + switch (peripheral) { + case PERIPH_ID_I2C0: + gpio_cfg_pin(EXYNOS4X12_GPIO_D10, S5P_GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS4X12_GPIO_D11, S5P_GPIO_FUNC(0x2)); + break; + case PERIPH_ID_I2C1: + gpio_cfg_pin(EXYNOS4X12_GPIO_D12, S5P_GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS4X12_GPIO_D13, S5P_GPIO_FUNC(0x2)); + break; + case PERIPH_ID_I2C2: + gpio_cfg_pin(EXYNOS4X12_GPIO_A06, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS4X12_GPIO_A07, S5P_GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C3: + gpio_cfg_pin(EXYNOS4X12_GPIO_A12, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS4X12_GPIO_A13, S5P_GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C4: + gpio_cfg_pin(EXYNOS4X12_GPIO_B2, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS4X12_GPIO_B3, S5P_GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C5: + gpio_cfg_pin(EXYNOS4X12_GPIO_B6, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS4X12_GPIO_B7, S5P_GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C6: + gpio_cfg_pin(EXYNOS4X12_GPIO_C13, S5P_GPIO_FUNC(0x4)); + gpio_cfg_pin(EXYNOS4X12_GPIO_C14, S5P_GPIO_FUNC(0x4)); + break; + case PERIPH_ID_I2C7: + gpio_cfg_pin(EXYNOS4X12_GPIO_D02, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS4X12_GPIO_D03, S5P_GPIO_FUNC(0x3)); + break; + } +} + +static int exynos4x12_mmc_config(int peripheral, int flags) +{ + int i, start = 0, start_ext = 0; + + switch (peripheral) { + case PERIPH_ID_SDMMC0: + start = EXYNOS4X12_GPIO_K00; + start_ext = EXYNOS4X12_GPIO_K13; + break; + case PERIPH_ID_SDMMC2: + start = EXYNOS4X12_GPIO_K20; + start_ext = EXYNOS4X12_GPIO_K33; + break; + default: + return -1; } + for (i = start; i < (start + 7); i++) { + if (i == (start + 2)) + continue; + gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2)); + gpio_set_pull(i, S5P_GPIO_PULL_NONE); + gpio_set_drv(i, S5P_GPIO_DRV_4X); + } + if (flags & PINMUX_FLAG_8BIT_MODE) { + for (i = start_ext; i < (start_ext + 4); i++) { + gpio_cfg_pin(i, S5P_GPIO_FUNC(0x3)); + gpio_set_pull(i, S5P_GPIO_PULL_NONE); + gpio_set_drv(i, S5P_GPIO_DRV_4X); + } + } + + return 0; } + +static void exynos4x12_uart_config(int peripheral) +{ + int i, start, count; + + switch (peripheral) { + case PERIPH_ID_UART0: + start = EXYNOS4X12_GPIO_A00; + count = 4; + break; + case PERIPH_ID_UART1: + start = EXYNOS4X12_GPIO_A04; + count = 4; + break; + case PERIPH_ID_UART2: + start = EXYNOS4X12_GPIO_A10; + count = 4; + break; + case PERIPH_ID_UART3: + start = EXYNOS4X12_GPIO_A14; + count = 2; + break; + default: + debug("%s: invalid peripheral %d", __func__, peripheral); + return; + } + for (i = start; i < (start + count); i++) { + gpio_set_pull(i, S5P_GPIO_PULL_NONE); + gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2)); + } +} + static int exynos4_pinmux_config(int peripheral, int flags) { switch (peripheral) { @@ -736,6 +773,41 @@ static int exynos4_pinmux_config(int peripheral, int flags) return 0; } +static int exynos4x12_pinmux_config(int peripheral, int flags) +{ + switch (peripheral) { + case PERIPH_ID_UART0: + case PERIPH_ID_UART1: + case PERIPH_ID_UART2: + case PERIPH_ID_UART3: + exynos4x12_uart_config(peripheral); + break; + case PERIPH_ID_I2C0: + case PERIPH_ID_I2C1: + case PERIPH_ID_I2C2: + case PERIPH_ID_I2C3: + case PERIPH_ID_I2C4: + case PERIPH_ID_I2C5: + case PERIPH_ID_I2C6: + case PERIPH_ID_I2C7: + exynos4x12_i2c_config(peripheral, flags); + break; + case PERIPH_ID_SDMMC0: + case PERIPH_ID_SDMMC2: + return exynos4x12_mmc_config(peripheral, flags); + case PERIPH_ID_SDMMC1: + case PERIPH_ID_SDMMC3: + case PERIPH_ID_SDMMC4: + debug("SDMMC device %d not implemented\n", peripheral); + return -1; + default: + debug("%s: invalid peripheral %d", __func__, peripheral); + return -1; + } + + return 0; +} + int exynos_pinmux_config(int peripheral, int flags) { if (cpu_is_exynos5()) { @@ -744,11 +816,14 @@ int exynos_pinmux_config(int peripheral, int flags) else if (proid_is_exynos5250()) return exynos5_pinmux_config(peripheral, flags); } else if (cpu_is_exynos4()) { - return exynos4_pinmux_config(peripheral, flags); - } else { - debug("pinmux functionality not supported\n"); + if (proid_is_exynos4412()) + return exynos4x12_pinmux_config(peripheral, flags); + else + return exynos4_pinmux_config(peripheral, flags); } + debug("pinmux functionality not supported\n"); + return -1; } @@ -787,7 +862,7 @@ int pinmux_decode_periph_id(const void *blob, int node) return exynos5_pinmux_decode_periph_id(blob, node); else if (cpu_is_exynos4()) return exynos4_pinmux_decode_periph_id(blob, node); - else - return PERIPH_ID_NONE; + + return PERIPH_ID_NONE; } #endif diff --git a/arch/arm/cpu/armv7/rmobile/Makefile b/arch/arm/cpu/armv7/rmobile/Makefile index 22219990dd..fad004ca64 100644 --- a/arch/arm/cpu/armv7/rmobile/Makefile +++ b/arch/arm/cpu/armv7/rmobile/Makefile @@ -11,7 +11,7 @@ obj-y += emac.o obj-$(CONFIG_DISPLAY_BOARDINFO) += board.o obj-$(CONFIG_GLOBAL_TIMER) += timer.o obj-$(CONFIG_R8A7740) += lowlevel_init.o cpu_info-r8a7740.o pfc-r8a7740.o -obj-$(CONFIG_R8A7790) += lowlevel_init_ca15.o cpu_info-r8a7790.o pfc-r8a7790.o -obj-$(CONFIG_R8A7791) += lowlevel_init_ca15.o cpu_info-r8a7791.o pfc-r8a7791.o +obj-$(CONFIG_R8A7790) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7790.o +obj-$(CONFIG_R8A7791) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7791.o obj-$(CONFIG_SH73A0) += lowlevel_init.o cpu_info-sh73a0.o pfc-sh73a0.o obj-$(CONFIG_TMU_TIMER) += ../../../../sh/lib/time.o diff --git a/arch/arm/cpu/armv7/rmobile/cpu_info-r8a7791.c b/arch/arm/cpu/armv7/rmobile/cpu_info-r8a7791.c deleted file mode 100644 index 2de58ed273..0000000000 --- a/arch/arm/cpu/armv7/rmobile/cpu_info-r8a7791.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - * arch/arm/cpu/armv7/rmobile/cpu_info-r8a7791.c - * - * Copyright (C) 2013 Renesas Electronics Corporation - * - * SPDX-License-Identifier: GPL-2.0 - */ -#include <common.h> -#include <asm/io.h> - -#define PRR 0xFF000044 - -u32 rmobile_get_cpu_type(void) -{ - u32 product; - - product = readl(PRR); - - return (u32)((product & 0x00007F00) >> 8); -} - -u32 rmobile_get_cpu_rev_integer(void) -{ - u32 product; - - product = readl(PRR); - - return (u32)((product & 0x000000F0) >> 4); -} diff --git a/arch/arm/cpu/armv7/rmobile/cpu_info-r8a7790.c b/arch/arm/cpu/armv7/rmobile/cpu_info-rcar.c index 7232e23774..42ee30fbe7 100644 --- a/arch/arm/cpu/armv7/rmobile/cpu_info-r8a7790.c +++ b/arch/arm/cpu/armv7/rmobile/cpu_info-rcar.c @@ -1,8 +1,7 @@ /* - * arch/arm/cpu/armv7/rmobile/cpu_info-r8a7790.c - * This file is r8a7790 processor support. + * arch/arm/cpu/armv7/rmobile/cpu_info-rcar.c * - * Copyright (C) 2013 Renesas Electronics Corporation + * Copyright (C) 2013,2014 Renesas Electronics Corporation * * SPDX-License-Identifier: GPL-2.0 */ @@ -18,5 +17,10 @@ u32 rmobile_get_cpu_type(void) u32 rmobile_get_cpu_rev_integer(void) { - return (readl(PRR) & 0x000000F0) >> 4; + return ((readl(PRR) & 0x000000F0) >> 4) + 1; +} + +u32 rmobile_get_cpu_rev_fraction(void) +{ + return readl(PRR) & 0x0000000F; } diff --git a/arch/arm/cpu/armv7/rmobile/cpu_info.c b/arch/arm/cpu/armv7/rmobile/cpu_info.c index 83d5282e3e..7a7c97d791 100644 --- a/arch/arm/cpu/armv7/rmobile/cpu_info.c +++ b/arch/arm/cpu/armv7/rmobile/cpu_info.c @@ -44,35 +44,30 @@ static u32 __rmobile_get_cpu_rev_fraction(void) u32 rmobile_get_cpu_rev_fraction(void) __attribute__((weak, alias("__rmobile_get_cpu_rev_fraction"))); +/* CPU infomation table */ +static const struct { + u16 cpu_type; + u8 cpu_name[10]; +} rmobile_cpuinfo[] = { + { 0x37, "SH73A0" }, + { 0x40, "R8A7740" }, + { 0x45, "R8A7790" }, + { 0x47, "R8A7791" }, + { 0x0, "CPU" }, +}; + int print_cpuinfo(void) { - switch (rmobile_get_cpu_type()) { - case 0x37: - printf("CPU: Renesas Electronics SH73A0 rev %d.%d\n", - rmobile_get_cpu_rev_integer(), - rmobile_get_cpu_rev_fraction()); - break; - case 0x40: - printf("CPU: Renesas Electronics R8A7740 rev %d.%d\n", - rmobile_get_cpu_rev_integer(), - rmobile_get_cpu_rev_fraction()); - break; - - case 0x45: - printf("CPU: Renesas Electronics R8A7790 rev %d\n", - rmobile_get_cpu_rev_integer()); - break; - - case 0x47: - printf("CPU: Renesas Electronics R8A7791 rev %d\n", - rmobile_get_cpu_rev_integer()); - break; - - default: - printf("CPU: Renesas Electronics CPU rev %d.%d\n", - rmobile_get_cpu_rev_integer(), - rmobile_get_cpu_rev_fraction()); - break; + int i = 0; + u32 cpu_type = rmobile_get_cpu_type(); + for (; i < ARRAY_SIZE(rmobile_cpuinfo); i++) { + if (rmobile_cpuinfo[i].cpu_type == cpu_type) { + printf("CPU: Renesas Electronics %s rev %d.%d\n", + rmobile_cpuinfo[i].cpu_name, + rmobile_get_cpu_rev_integer(), + rmobile_get_cpu_rev_fraction()); + break; + } } return 0; } diff --git a/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S b/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S index e07cc8093a..287f8d74af 100644 --- a/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S +++ b/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S @@ -2,7 +2,7 @@ * arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S * This file is lager low level initialize. * - * Copyright (C) 2013 Renesas Electronics Corporation + * Copyright (C) 2013, 2014 Renesas Electronics Corporation * * SPDX-License-Identifier: GPL-2.0 */ @@ -36,16 +36,32 @@ do_cpu_waiting: .align 4 do_lowlevel_init: /* surpress wfe if ca15 */ - tst r4, #4 + tst r4, #4 mrceq p15, 0, r0, c1, c0, 1 /* actlr */ orreq r0, r0, #(1<<7) mcreq p15, 0, r0, c1, c0, 1 + /* and set l2 latency */ mrceq p15, 1, r0, c9, c0, 2 /* l2ctlr */ orreq r0, r0, #0x00000800 orreq r0, r0, #0x00000003 mcreq p15, 1, r0, c9, c0, 2 + mrc p15, 0, r0, c0, c0, 5 /* r0 = MPIDR */ + and r0, r0, #0xf00 + lsr r0, r0, #8 + tst r0, #1 /* only need for cluster 0 */ + bne _exit_init_l2_a15 + + mrc p15, 1, r0, c9, c0, 2 /* r0 = L2CTLR */ + and r1, r0, #7 + cmp r1, #3 /* has already been set up */ + bicne r0, r0, #0xe7 + orrne r0, r0, #0x83 /* L2CTLR[7:6] + L2CTLR[2:0] */ + orrne r0, r0, #0x20 /* L2CTLR[5] */ + mcrne p15, 1, r0, c9, c0, 2 + +_exit_init_l2_a15: ldr r3, =(CONFIG_SYS_INIT_SP_ADDR) sub sp, r3, #4 str lr, [sp] diff --git a/arch/arm/cpu/armv7/socfpga/lowlevel_init.S b/arch/arm/cpu/armv7/socfpga/lowlevel_init.S index 1caaa2759f..2f2e9fcc7c 100644 --- a/arch/arm/cpu/armv7/socfpga/lowlevel_init.S +++ b/arch/arm/cpu/armv7/socfpga/lowlevel_init.S @@ -10,20 +10,7 @@ /* Save the parameter pass in by previous boot loader */ .global save_boot_params save_boot_params: - /* save the parameter here */ - - /* - * Setup stack for exception, which is located - * at the end of on-chip RAM. We don't expect exception prior to - * relocation and if that happens, we won't worry -- it will overide - * global data region as the code will goto reset. After relocation, - * this region won't be used by other part of program. - * Hence it is safe. - */ - ldr r0, =(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE) - ldr r1, =IRQ_STACK_START_IN - str r0, [r1] - + /* no parameter to save */ bx lr diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 27be451a89..fedd7c8f7e 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -19,46 +19,6 @@ #include <asm/system.h> #include <linux/linkage.h> -.globl _start -_start: b reset - ldr pc, _undefined_instruction - ldr pc, _software_interrupt - ldr pc, _prefetch_abort - ldr pc, _data_abort - ldr pc, _not_used - ldr pc, _irq - ldr pc, _fiq -#ifdef CONFIG_SPL_BUILD -_undefined_instruction: .word _undefined_instruction -_software_interrupt: .word _software_interrupt -_prefetch_abort: .word _prefetch_abort -_data_abort: .word _data_abort -_not_used: .word _not_used -_irq: .word _irq -_fiq: .word _fiq -_pad: .word 0x12345678 /* now 16*4=64 */ -#else -.globl _undefined_instruction -_undefined_instruction: .word undefined_instruction -.globl _software_interrupt -_software_interrupt: .word software_interrupt -.globl _prefetch_abort -_prefetch_abort: .word prefetch_abort -.globl _data_abort -_data_abort: .word data_abort -.globl _not_used -_not_used: .word not_used -.globl _irq -_irq: .word irq -.globl _fiq -_fiq: .word fiq -_pad: .word 0x12345678 /* now 16*4=64 */ -#endif /* CONFIG_SPL_BUILD */ - -.global _end_vect -_end_vect: - - .balignl 16,0xdeadbeef /************************************************************************* * * Startup Code (reset vector) @@ -70,26 +30,7 @@ _end_vect: * *************************************************************************/ -#ifdef CONFIG_USE_IRQ -/* IRQ stack memory (calculated at run-time) */ -.globl IRQ_STACK_START -IRQ_STACK_START: - .word 0x0badc0de - -/* IRQ stack memory (calculated at run-time) */ -.globl FIQ_STACK_START -FIQ_STACK_START: - .word 0x0badc0de -#endif - -/* IRQ stack memory (calculated at run-time) + 8 bytes */ -.globl IRQ_STACK_START_IN -IRQ_STACK_START_IN: - .word 0x0badc0de - -/* - * the actual reset code - */ + .globl reset reset: bl save_boot_params @@ -250,195 +191,3 @@ ENTRY(cpu_init_crit) b lowlevel_init @ go setup pll,mux,memory ENDPROC(cpu_init_crit) #endif - -#ifndef CONFIG_SPL_BUILD -/* - ************************************************************************* - * - * Interrupt handling - * - ************************************************************************* - */ -@ -@ IRQ stack frame. -@ -#define S_FRAME_SIZE 72 - -#define S_OLD_R0 68 -#define S_PSR 64 -#define S_PC 60 -#define S_LR 56 -#define S_SP 52 - -#define S_IP 48 -#define S_FP 44 -#define S_R10 40 -#define S_R9 36 -#define S_R8 32 -#define S_R7 28 -#define S_R6 24 -#define S_R5 20 -#define S_R4 16 -#define S_R3 12 -#define S_R2 8 -#define S_R1 4 -#define S_R0 0 - -#define MODE_SVC 0x13 -#define I_BIT 0x80 - -/* - * use bad_save_user_regs for abort/prefetch/undef/swi ... - * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling - */ - - .macro bad_save_user_regs - sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current - @ user stack - stmia sp, {r0 - r12} @ Save user registers (now in - @ svc mode) r0-r12 - ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort - @ stack - ldmia r2, {r2 - r3} @ get values for "aborted" pc - @ and cpsr (into parm regs) - add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack - - add r5, sp, #S_SP - mov r1, lr - stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr - mov r0, sp @ save current stack into r0 - @ (param register) - .endm - - .macro irq_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Calling r0-r12 - add r8, sp, #S_PC @ !! R8 NEEDS to be saved !! - @ a reserved stack spot would - @ be good. - stmdb r8, {sp, lr}^ @ Calling SP, LR - str lr, [r8, #0] @ Save calling PC - mrs r6, spsr - str r6, [r8, #4] @ Save CPSR - str r0, [r8, #8] @ Save OLD_R0 - mov r0, sp - .endm - - .macro irq_restore_user_regs - ldmia sp, {r0 - lr}^ @ Calling r0 - lr - mov r0, r0 - ldr lr, [sp, #S_PC] @ Get PC - add sp, sp, #S_FRAME_SIZE - subs pc, lr, #4 @ return & move spsr_svc into - @ cpsr - .endm - - .macro get_bad_stack - ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter - @ in banked mode) - - str lr, [r13] @ save caller lr in position 0 - @ of saved stack - mrs lr, spsr @ get the spsr - str lr, [r13, #4] @ save spsr in position 1 of - @ saved stack - - mov r13, #MODE_SVC @ prepare SVC-Mode - @ msr spsr_c, r13 - msr spsr, r13 @ switch modes, make sure - @ moves will execute - mov lr, pc @ capture return pc - movs pc, lr @ jump to next instruction & - @ switch modes. - .endm - - .macro get_bad_stack_swi - sub r13, r13, #4 @ space on current stack for - @ scratch reg. - str r0, [r13] @ save R0's value. - ldr r0, IRQ_STACK_START_IN @ get data regions start - @ spots for abort stack - str lr, [r0] @ save caller lr in position 0 - @ of saved stack - mrs lr, spsr @ get the spsr - str lr, [r0, #4] @ save spsr in position 1 of - @ saved stack - ldr lr, [r0] @ restore lr - ldr r0, [r13] @ restore r0 - add r13, r13, #4 @ pop stack entry - .endm - - .macro get_irq_stack @ setup IRQ stack - ldr sp, IRQ_STACK_START - .endm - - .macro get_fiq_stack @ setup FIQ stack - ldr sp, FIQ_STACK_START - .endm - -/* - * exception handlers - */ - .align 5 -undefined_instruction: - get_bad_stack - bad_save_user_regs - bl do_undefined_instruction - - .align 5 -software_interrupt: - get_bad_stack_swi - bad_save_user_regs - bl do_software_interrupt - - .align 5 -prefetch_abort: - get_bad_stack - bad_save_user_regs - bl do_prefetch_abort - - .align 5 -data_abort: - get_bad_stack - bad_save_user_regs - bl do_data_abort - - .align 5 -not_used: - get_bad_stack - bad_save_user_regs - bl do_not_used - -#ifdef CONFIG_USE_IRQ - - .align 5 -irq: - get_irq_stack - irq_save_user_regs - bl do_irq - irq_restore_user_regs - - .align 5 -fiq: - get_fiq_stack - /* someone ought to write a more effective fiq_save_user_regs */ - irq_save_user_regs - bl do_fiq - irq_restore_user_regs - -#else - - .align 5 -irq: - get_bad_stack - bad_save_user_regs - bl do_irq - - .align 5 -fiq: - get_bad_stack - bad_save_user_regs - bl do_fiq - -#endif /* CONFIG_USE_IRQ */ -#endif /* CONFIG_SPL_BUILD */ diff --git a/arch/arm/cpu/armv7/zynq/u-boot.lds b/arch/arm/cpu/armv7/zynq/u-boot.lds index f2a5965988..69500a64e2 100644 --- a/arch/arm/cpu/armv7/zynq/u-boot.lds +++ b/arch/arm/cpu/armv7/zynq/u-boot.lds @@ -88,7 +88,7 @@ SECTIONS } /* - * Zynq needs to discard more sections because the user + * Zynq needs to discard these sections because the user * is expected to pass this image on to tools for boot.bin * generation that require them to be dropped. */ diff --git a/arch/arm/cpu/pxa/cpuinfo.c b/arch/arm/cpu/pxa/cpuinfo.c index 9d16079956..17d8be5b5b 100644 --- a/arch/arm/cpu/pxa/cpuinfo.c +++ b/arch/arm/cpu/pxa/cpuinfo.c @@ -11,6 +11,12 @@ #include <errno.h> #include <linux/compiler.h> +#ifdef CONFIG_CPU_PXA25X +#if ((CONFIG_SYS_INIT_SP_ADDR) != 0xfffff800) +#error "Init SP address must be set to 0xfffff800 for PXA250" +#endif +#endif + #define CPU_MASK_PXA_PRODID 0x000003f0 #define CPU_MASK_PXA_REVID 0x0000000f diff --git a/arch/arm/cpu/pxa/start.S b/arch/arm/cpu/pxa/start.S index ae0d13ce8f..c77d51e6d8 100644 --- a/arch/arm/cpu/pxa/start.S +++ b/arch/arm/cpu/pxa/start.S @@ -23,54 +23,6 @@ #include <config.h> #include <version.h> -#ifdef CONFIG_CPU_PXA25X -#if ((CONFIG_SYS_INIT_SP_ADDR) != 0xfffff800) -#error "Init SP address must be set to 0xfffff800 for PXA250" -#endif -#endif - -.globl _start -_start: b reset -#ifdef CONFIG_SPL_BUILD - ldr pc, _hang - ldr pc, _hang - ldr pc, _hang - ldr pc, _hang - ldr pc, _hang - ldr pc, _hang - ldr pc, _hang - -_hang: - .word do_hang - .word 0x12345678 - .word 0x12345678 - .word 0x12345678 - .word 0x12345678 - .word 0x12345678 - .word 0x12345678 - .word 0x12345678 /* now 16*4=64 */ -#else - ldr pc, _undefined_instruction - ldr pc, _software_interrupt - ldr pc, _prefetch_abort - ldr pc, _data_abort - ldr pc, _not_used - ldr pc, _irq - ldr pc, _fiq - -_undefined_instruction: .word undefined_instruction -_software_interrupt: .word software_interrupt -_prefetch_abort: .word prefetch_abort -_data_abort: .word data_abort -_not_used: .word not_used -_irq: .word irq -_fiq: .word fiq -_pad: .word 0x12345678 /* now 16*4=64 */ -#endif /* CONFIG_SPL_BUILD */ -.global _end_vect -_end_vect: - - .balignl 16,0xdeadbeef /* ************************************************************************* * @@ -84,26 +36,7 @@ _end_vect: ************************************************************************* */ -#ifdef CONFIG_USE_IRQ -/* IRQ stack memory (calculated at run-time) */ -.globl IRQ_STACK_START -IRQ_STACK_START: - .word 0x0badc0de - -/* IRQ stack memory (calculated at run-time) */ -.globl FIQ_STACK_START -FIQ_STACK_START: - .word 0x0badc0de -#endif - -/* IRQ stack memory (calculated at run-time) + 8 bytes */ -.globl IRQ_STACK_START_IN -IRQ_STACK_START_IN: - .word 0x0badc0de - -/* - * the actual reset code - */ + .globl reset reset: /* @@ -174,190 +107,6 @@ cpu_init_crit: mov pc, lr /* back to my caller */ #endif /* !CONFIG_SKIP_LOWLEVEL_INIT || CONFIG_CPU_PXA25X */ -#ifndef CONFIG_SPL_BUILD -/* - ************************************************************************* - * - * Interrupt handling - * - ************************************************************************* - */ -@ -@ IRQ stack frame. -@ -#define S_FRAME_SIZE 72 - -#define S_OLD_R0 68 -#define S_PSR 64 -#define S_PC 60 -#define S_LR 56 -#define S_SP 52 - -#define S_IP 48 -#define S_FP 44 -#define S_R10 40 -#define S_R9 36 -#define S_R8 32 -#define S_R7 28 -#define S_R6 24 -#define S_R5 20 -#define S_R4 16 -#define S_R3 12 -#define S_R2 8 -#define S_R1 4 -#define S_R0 0 - -#define MODE_SVC 0x13 -#define I_BIT 0x80 - -/* - * use bad_save_user_regs for abort/prefetch/undef/swi ... - * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling - */ - - .macro bad_save_user_regs - sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack - stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 - - ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort stack - ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs) - add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack - - add r5, sp, #S_SP - mov r1, lr - stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr - mov r0, sp @ save current stack into r0 (param register) - .endm - - .macro irq_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Calling r0-r12 - add r8, sp, #S_PC @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good. - stmdb r8, {sp, lr}^ @ Calling SP, LR - str lr, [r8, #0] @ Save calling PC - mrs r6, spsr - str r6, [r8, #4] @ Save CPSR - str r0, [r8, #8] @ Save OLD_R0 - mov r0, sp - .endm - - .macro irq_restore_user_regs - ldmia sp, {r0 - lr}^ @ Calling r0 - lr - mov r0, r0 - ldr lr, [sp, #S_PC] @ Get PC - add sp, sp, #S_FRAME_SIZE - subs pc, lr, #4 @ return & move spsr_svc into cpsr - .endm - - .macro get_bad_stack - ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter in banked mode) - - str lr, [r13] @ save caller lr in position 0 of saved stack - mrs lr, spsr @ get the spsr - str lr, [r13, #4] @ save spsr in position 1 of saved stack - - mov r13, #MODE_SVC @ prepare SVC-Mode - @ msr spsr_c, r13 - msr spsr, r13 @ switch modes, make sure moves will execute - mov lr, pc @ capture return pc - movs pc, lr @ jump to next instruction & switch modes. - .endm - - .macro get_bad_stack_swi - sub r13, r13, #4 @ space on current stack for scratch reg. - str r0, [r13] @ save R0's value. - ldr r0, IRQ_STACK_START_IN @ get data regions start - str lr, [r0] @ save caller lr in position 0 of saved stack - mrs lr, spsr @ get the spsr - str lr, [r0, #4] @ save spsr in position 1 of saved stack - ldr lr, [r0] @ restore lr - ldr r0, [r13] @ restore r0 - add r13, r13, #4 @ pop stack entry - .endm - - .macro get_irq_stack @ setup IRQ stack - ldr sp, IRQ_STACK_START - .endm - - .macro get_fiq_stack @ setup FIQ stack - ldr sp, FIQ_STACK_START - .endm -#endif /* CONFIG_SPL_BUILD */ - -/* - * exception handlers - */ -#ifdef CONFIG_SPL_BUILD - .align 5 -do_hang: - bl hang /* hang and never return */ -#else /* !CONFIG_SPL_BUILD */ - .align 5 -undefined_instruction: - get_bad_stack - bad_save_user_regs - bl do_undefined_instruction - - .align 5 -software_interrupt: - get_bad_stack_swi - bad_save_user_regs - bl do_software_interrupt - - .align 5 -prefetch_abort: - get_bad_stack - bad_save_user_regs - bl do_prefetch_abort - - .align 5 -data_abort: - get_bad_stack - bad_save_user_regs - bl do_data_abort - - .align 5 -not_used: - get_bad_stack - bad_save_user_regs - bl do_not_used - -#ifdef CONFIG_USE_IRQ - - .align 5 -irq: - get_irq_stack - irq_save_user_regs - bl do_irq - irq_restore_user_regs - - .align 5 -fiq: - get_fiq_stack - /* someone ought to write a more effiction fiq_save_user_regs */ - irq_save_user_regs - bl do_fiq - irq_restore_user_regs - -#else - - .align 5 -irq: - get_bad_stack - bad_save_user_regs - bl do_irq - - .align 5 -fiq: - get_bad_stack - bad_save_user_regs - bl do_fiq - -#endif - .align 5 -#endif /* CONFIG_SPL_BUILD */ - - /* * Enable MMU to use DCache as DRAM. * diff --git a/arch/arm/cpu/sa1100/cpu.c b/arch/arm/cpu/sa1100/cpu.c index 6651898de2..4c9752a1c8 100644 --- a/arch/arm/cpu/sa1100/cpu.c +++ b/arch/arm/cpu/sa1100/cpu.c @@ -17,6 +17,7 @@ #include <common.h> #include <command.h> #include <asm/system.h> +#include <asm/io.h> #ifdef CONFIG_USE_IRQ DECLARE_GLOBAL_DATA_PTR; @@ -52,3 +53,16 @@ static void cache_flush (void) asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); } + +#define RST_BASE 0x90030000 +#define RSRR 0x00 +#define RCSR 0x04 + +__attribute__((noreturn)) void reset_cpu(ulong addr __attribute__((unused))) +{ + /* repeat endlessly */ + while (1) { + writel(0, RST_BASE + RCSR); + writel(1, RST_BASE + RSRR); + } +} diff --git a/arch/arm/cpu/sa1100/start.S b/arch/arm/cpu/sa1100/start.S index bf80937a7c..78e0cb8868 100644 --- a/arch/arm/cpu/sa1100/start.S +++ b/arch/arm/cpu/sa1100/start.S @@ -16,36 +16,6 @@ /* ************************************************************************* * - * Jump vector table as in table 3.1 in [1] - * - ************************************************************************* - */ - - -.globl _start -_start: b reset - ldr pc, _undefined_instruction - ldr pc, _software_interrupt - ldr pc, _prefetch_abort - ldr pc, _data_abort - ldr pc, _not_used - ldr pc, _irq - ldr pc, _fiq - -_undefined_instruction: .word undefined_instruction -_software_interrupt: .word software_interrupt -_prefetch_abort: .word prefetch_abort -_data_abort: .word data_abort -_not_used: .word not_used -_irq: .word irq -_fiq: .word fiq - - .balignl 16,0xdeadbeef - - -/* - ************************************************************************* - * * Startup Code (reset vector) * * do important init only if we don't start from memory! @@ -56,26 +26,7 @@ _fiq: .word fiq ************************************************************************* */ -#ifdef CONFIG_USE_IRQ -/* IRQ stack memory (calculated at run-time) */ -.globl IRQ_STACK_START -IRQ_STACK_START: - .word 0x0badc0de - -/* IRQ stack memory (calculated at run-time) */ -.globl FIQ_STACK_START -FIQ_STACK_START: - .word 0x0badc0de -#endif - -/* IRQ stack memory (calculated at run-time) + 8 bytes */ -.globl IRQ_STACK_START_IN -IRQ_STACK_START_IN: - .word 0x0badc0de - -/* - * the actual reset code - */ + .globl reset reset: /* @@ -173,177 +124,3 @@ cpu_init_crit: mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ mov pc, lr - - -/* - ************************************************************************* - * - * Interrupt handling - * - ************************************************************************* - */ - -@ -@ IRQ stack frame. -@ -#define S_FRAME_SIZE 72 - -#define S_OLD_R0 68 -#define S_PSR 64 -#define S_PC 60 -#define S_LR 56 -#define S_SP 52 - -#define S_IP 48 -#define S_FP 44 -#define S_R10 40 -#define S_R9 36 -#define S_R8 32 -#define S_R7 28 -#define S_R6 24 -#define S_R5 20 -#define S_R4 16 -#define S_R3 12 -#define S_R2 8 -#define S_R1 4 -#define S_R0 0 - -#define MODE_SVC 0x13 -#define I_BIT 0x80 - -/* - * use bad_save_user_regs for abort/prefetch/undef/swi ... - * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling - */ - - .macro bad_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Calling r0-r12 - add r8, sp, #S_PC - - ldr r2, IRQ_STACK_START_IN - ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0 - add r0, sp, #S_FRAME_SIZE @ restore sp_SVC - - add r5, sp, #S_SP - mov r1, lr - stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC, pc, cpsr, old_r - mov r0, sp - .endm - - .macro irq_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Calling r0-r12 - add r8, sp, #S_PC - stmdb r8, {sp, lr}^ @ Calling SP, LR - str lr, [r8, #0] @ Save calling PC - mrs r6, spsr - str r6, [r8, #4] @ Save CPSR - str r0, [r8, #8] @ Save OLD_R0 - mov r0, sp - .endm - - .macro irq_restore_user_regs - ldmia sp, {r0 - lr}^ @ Calling r0 - lr - mov r0, r0 - ldr lr, [sp, #S_PC] @ Get PC - add sp, sp, #S_FRAME_SIZE - subs pc, lr, #4 @ return & move spsr_svc into cpsr - .endm - - .macro get_bad_stack - ldr r13, IRQ_STACK_START_IN @ setup our mode stack - - str lr, [r13] @ save caller lr / spsr - mrs lr, spsr - str lr, [r13, #4] - - mov r13, #MODE_SVC @ prepare SVC-Mode - msr spsr_c, r13 - mov lr, pc - movs pc, lr - .endm - - .macro get_irq_stack @ setup IRQ stack - ldr sp, IRQ_STACK_START - .endm - - .macro get_fiq_stack @ setup FIQ stack - ldr sp, FIQ_STACK_START - .endm - -/* - * exception handlers - */ - .align 5 -undefined_instruction: - get_bad_stack - bad_save_user_regs - bl do_undefined_instruction - - .align 5 -software_interrupt: - get_bad_stack - bad_save_user_regs - bl do_software_interrupt - - .align 5 -prefetch_abort: - get_bad_stack - bad_save_user_regs - bl do_prefetch_abort - - .align 5 -data_abort: - get_bad_stack - bad_save_user_regs - bl do_data_abort - - .align 5 -not_used: - get_bad_stack - bad_save_user_regs - bl do_not_used - -#ifdef CONFIG_USE_IRQ - - .align 5 -irq: - get_irq_stack - irq_save_user_regs - bl do_irq - irq_restore_user_regs - - .align 5 -fiq: - get_fiq_stack - /* someone ought to write a more effiction fiq_save_user_regs */ - irq_save_user_regs - bl do_fiq - irq_restore_user_regs - -#else - - .align 5 -irq: - get_bad_stack - bad_save_user_regs - bl do_irq - - .align 5 -fiq: - get_bad_stack - bad_save_user_regs - bl do_fiq - -#endif - - .align 5 -.globl reset_cpu -reset_cpu: - ldr r0, RST_BASE - mov r1, #0x0 @ set bit 3-0 ... - str r1, [r0, #RCSR] @ ... to clear in RCSR - mov r1, #0x1 - str r1, [r0, #RSRR] @ and perform reset - b reset_cpu @ silly, but repeat endlessly diff --git a/arch/arm/cpu/tegra-common/pinmux-common.c b/arch/arm/cpu/tegra-common/pinmux-common.c index d62618cd0f..6e3ab0c14c 100644 --- a/arch/arm/cpu/tegra-common/pinmux-common.c +++ b/arch/arm/cpu/tegra-common/pinmux-common.c @@ -86,12 +86,31 @@ #define IO_RESET_SHIFT 8 #define RCV_SEL_SHIFT 9 +#if !defined(CONFIG_TEGRA20) && !defined(CONFIG_TEGRA30) +/* This register/field only exists on Tegra114 and later */ +#define APB_MISC_PP_PINMUX_GLOBAL_0 0x40 +#define CLAMP_INPUTS_WHEN_TRISTATED 1 + +void pinmux_set_tristate_input_clamping(void) +{ + u32 *reg = _R(APB_MISC_PP_PINMUX_GLOBAL_0); + u32 val; + + val = readl(reg); + val |= CLAMP_INPUTS_WHEN_TRISTATED; + writel(val, reg); +} +#endif + void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func) { u32 *reg = MUX_REG(pin); int i, mux = -1; u32 val; + if (func == PMUX_FUNC_DEFAULT) + return; + /* Error check on pin and func */ assert(pmux_pingrp_isvalid(pin)); assert(pmux_func_isvalid(func)); diff --git a/arch/arm/cpu/u-boot-spl.lds b/arch/arm/cpu/u-boot-spl.lds index 3e886680e8..4beddf08e7 100644 --- a/arch/arm/cpu/u-boot-spl.lds +++ b/arch/arm/cpu/u-boot-spl.lds @@ -18,6 +18,7 @@ SECTIONS .text : { __image_copy_start = .; + *(.vectors) CPUDIR/start.o (.text*) *(.text*) } diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds index 33c1f99fc0..a7728e0a2d 100644 --- a/arch/arm/cpu/u-boot.lds +++ b/arch/arm/cpu/u-boot.lds @@ -18,6 +18,7 @@ SECTIONS .text : { *(.__image_copy_start) + *(.vectors) CPUDIR/start.o (.text*) *(.text*) } |