diff options
Diffstat (limited to 'arch/arm/cpu')
| -rw-r--r-- | arch/arm/cpu/arm1176/bcm2835/timer.c | 14 | ||||
| -rw-r--r-- | arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c | 18 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/cache_v7.c | 3 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/mx6/soc.c | 12 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/omap-common/hwinit-common.c | 35 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/start.S | 1 |
6 files changed, 70 insertions, 13 deletions
diff --git a/arch/arm/cpu/arm1176/bcm2835/timer.c b/arch/arm/cpu/arm1176/bcm2835/timer.c index d232d7e067..2edd6711da 100644 --- a/arch/arm/cpu/arm1176/bcm2835/timer.c +++ b/arch/arm/cpu/arm1176/bcm2835/timer.c @@ -23,7 +23,7 @@ int timer_init(void) return 0; } -ulong get_timer(ulong base) +ulong get_timer_us(ulong base) { struct bcm2835_timer_regs *regs = (struct bcm2835_timer_regs *)BCM2835_TIMER_PHYSADDR; @@ -31,6 +31,14 @@ ulong get_timer(ulong base) return readl(®s->clo) - base; } +ulong get_timer(ulong base) +{ + ulong us = get_timer_us(0); + us /= (1000000 / CONFIG_SYS_HZ); + us -= base; + return us; +} + unsigned long long get_ticks(void) { return get_timer(0); @@ -46,10 +54,10 @@ void __udelay(unsigned long usec) ulong endtime; signed long diff; - endtime = get_timer(0) + usec; + endtime = get_timer_us(0) + usec; do { - ulong now = get_timer(0); + ulong now = get_timer_us(0); diff = endtime - now; } while (diff >= 0); } diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c index fdac73cfaa..bc2d69c857 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c @@ -46,17 +46,17 @@ static uint32_t dram_vals[] = { 0x00000000, 0x00000000, 0x00010101, 0x01010101, 0x000f0f01, 0x0f02020a, 0x00000000, 0x00010101, 0x00000100, 0x00000100, 0x00000000, 0x00000002, - 0x01010000, 0x05060302, 0x06005003, 0x0a0000c8, - 0x02009c40, 0x0000030c, 0x0036a609, 0x031a0612, + 0x01010000, 0x07080403, 0x06005003, 0x0a0000c8, + 0x02009c40, 0x0002030c, 0x0036a609, 0x031a0612, 0x02030202, 0x00c8001c, 0x00000000, 0x00000000, 0x00012100, 0xffff0303, 0x00012100, 0xffff0303, 0x00012100, 0xffff0303, 0x00012100, 0xffff0303, 0x00000003, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000612, 0x01000F02, - 0x06120612, 0x00000200, 0x00020007, 0xf5014b27, - 0xf5014b27, 0xf5014b27, 0xf5014b27, 0x07000300, - 0x07000300, 0x07000300, 0x07000300, 0x00000006, + 0x06120612, 0x00000200, 0x00020007, 0xf4004a27, + 0xf4004a27, 0xf4004a27, 0xf4004a27, 0x07000300, + 0x07000300, 0x07400300, 0x07400300, 0x00000005, 0x00000000, 0x00000000, 0x01000000, 0x01020408, 0x08040201, 0x000f1133, 0x00000000, 0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04, @@ -77,14 +77,14 @@ static uint32_t dram_vals[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00010000, 0x00020304, - 0x00000004, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00010000, 0x00030404, + 0x00000003, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01010000, 0x01000000, 0x03030000, 0x00010303, 0x01020202, 0x00000000, 0x02040303, 0x21002103, 0x00061200, - 0x06120612, 0x04320432, 0x04320432, 0x00040004, + 0x06120612, 0x04420442, 0x04420442, 0x00040004, 0x00040004, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00010001 + 0x00000000, 0xffffffff /* * i.MX23 DDR at 133MHz diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c index 5f6d0396f3..8748c145c4 100644 --- a/arch/arm/cpu/armv7/cache_v7.c +++ b/arch/arm/cpu/armv7/cache_v7.c @@ -340,6 +340,9 @@ void mmu_page_table_flush(unsigned long start, unsigned long stop) { } +void arm_init_domains(void) +{ +} #endif /* #ifndef CONFIG_SYS_DCACHE_OFF */ #ifndef CONFIG_SYS_ICACHE_OFF diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 193ba1240f..2ea8ca3bd3 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -61,6 +61,18 @@ u32 get_cpu_rev(void) return (type << 12) | (reg + 0x10); } +#ifdef CONFIG_REVISION_TAG +u32 __weak get_board_rev(void) +{ + u32 cpurev = get_cpu_rev(); + u32 type = ((cpurev >> 12) & 0xff); + if (type == MXC_CPU_MX6SOLO) + cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF); + + return cpurev; +} +#endif + void init_aips(void) { struct aipstz_regs *aips1, *aips2; diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c index 05ff2e868f..70d16a8160 100644 --- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c +++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c @@ -34,6 +34,12 @@ #include <asm/emif.h> #include <asm/omap_common.h> #include <linux/compiler.h> +#include <asm/cache.h> +#include <asm/system.h> + +#define ARMV7_DCACHE_WRITEBACK 0xe +#define ARMV7_DOMAIN_CLIENT 1 +#define ARMV7_DOMAIN_MASK (0x3 << 0) DECLARE_GLOBAL_DATA_PTR; @@ -269,4 +275,33 @@ void enable_caches(void) /* Enable D-cache. I-cache is already enabled in start.S */ dcache_enable(); } + +void dram_bank_mmu_setup(int bank) +{ + bd_t *bd = gd->bd; + int i; + + u32 start = bd->bi_dram[bank].start >> 20; + u32 size = bd->bi_dram[bank].size >> 20; + u32 end = start + size; + + debug("%s: bank: %d\n", __func__, bank); + for (i = start; i < end; i++) + set_section_dcache(i, ARMV7_DCACHE_WRITEBACK); + +} + +void arm_init_domains(void) +{ + u32 reg; + + reg = get_dacr(); + /* + * Set DOMAIN to client access so that all permissions + * set in pagetables are validated by the mmu. + */ + reg &= ~ARMV7_DOMAIN_MASK; + reg |= ARMV7_DOMAIN_CLIENT; + set_dacr(reg); +} #endif diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index c0e184994a..36a4c3cfda 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -254,7 +254,6 @@ ENTRY(c_runtime_cpu_setup) #if !defined(CONFIG_TEGRA) /* Set vector address in CP15 VBAR register */ ldr r0, =_start - add r0, r0, r9 mcr p15, 0, r0, c12, c0, 0 @Set VBAR #endif /* !Tegra */ |