diff options
Diffstat (limited to 'arch/arm/dts/dra72-evm-common.dtsi')
| -rw-r--r-- | arch/arm/dts/dra72-evm-common.dtsi | 31 |
1 files changed, 23 insertions, 8 deletions
diff --git a/arch/arm/dts/dra72-evm-common.dtsi b/arch/arm/dts/dra72-evm-common.dtsi index c83f87fa79..2e485a13df 100644 --- a/arch/arm/dts/dra72-evm-common.dtsi +++ b/arch/arm/dts/dra72-evm-common.dtsi @@ -20,7 +20,6 @@ chosen { stdout-path = &uart1; - tick-timer = &timer2; }; evm_12v0: fixedregulator-evm12v0 { @@ -221,9 +220,17 @@ status = "okay"; clock-frequency = <400000>; + pcf_lcd: gpio@20 { + compatible = "nxp,pcf8575"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + pcf_gpio_21: gpio@21 { compatible = "ti,pcf8575", "nxp,pcf8575"; - u-boot,i2c-offset-len = <0>; reg = <0x21>; lines-initial-states = <0x1408>; gpio-controller; @@ -254,7 +261,6 @@ pcf_hdmi: pcf8575@26 { compatible = "ti,pcf8575", "nxp,pcf8575"; - u-boot,i2c-offset-len = <0>; reg = <0x26>; gpio-controller; #gpio-cells = <2>; @@ -287,7 +293,12 @@ }; &gpmc { - status = "okay"; + /* + * For the existing IOdelay configuration via U-Boot we don't + * support NAND on dra72-evm. Keep it disabled. Enabling it + * requires a different configuration by U-Boot. + */ + status = "disabled"; ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */ nand@0,0 { /* To use NAND, DIP switch SW5 must be set like so: @@ -300,6 +311,7 @@ interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ <1 IRQ_TYPE_NONE>; /* termcount */ rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */ + ti,nand-xfer-type = "prefetch-dma"; ti,nand-ecc-opt = "bch8"; ti,elm-id = <&elm>; nand-bus-width = <16>; @@ -381,7 +393,8 @@ }; &usb1 { - dr_mode = "peripheral"; + dr_mode = "otg"; + extcon = <&extcon_usb1>; }; &usb2 { @@ -407,8 +420,6 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mmc2_pins_default>; - - vmmc-supply = <&evm_3v3_sw>; bus-width = <8>; ti,non-removable; max-frequency = <192000000>; @@ -431,7 +442,7 @@ spi-max-frequency = <76800000>; m25p80@0 { - compatible = "s25fl256s1", "spi-flash"; + compatible = "s25fl256s1"; spi-max-frequency = <76800000>; reg = <0>; spi-tx-bus-width = <1>; @@ -552,3 +563,7 @@ status = "okay"; }; }; + +&pcie1_rc { + status = "okay"; +}; |