diff options
Diffstat (limited to 'arch/arm/dts/fsl-imx8qm.dtsi')
| -rw-r--r-- | arch/arm/dts/fsl-imx8qm.dtsi | 155 |
1 files changed, 155 insertions, 0 deletions
diff --git a/arch/arm/dts/fsl-imx8qm.dtsi b/arch/arm/dts/fsl-imx8qm.dtsi index b39c40bd98..af060db3a1 100644 --- a/arch/arm/dts/fsl-imx8qm.dtsi +++ b/arch/arm/dts/fsl-imx8qm.dtsi @@ -22,9 +22,18 @@ ethernet0 = &fec1; ethernet1 = &fec2; serial0 = &lpuart0; + serial1 = &lpuart1; + serial2 = &lpuart2; + serial3 = &lpuart3; + serial4 = &lpuart4; mmc0 = &usdhc1; mmc1 = &usdhc2; mmc2 = &usdhc3; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; }; memory@80000000 { @@ -193,9 +202,103 @@ power-domains = <&pd_dma>; wakeup-irq = <345>; }; + pd_dma_lpuart1: PD_DMA_UART1 { + reg = <SC_R_UART_1>; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + wakeup-irq = <346>; + }; + pd_dma_lpuart2: PD_DMA_UART2 { + reg = <SC_R_UART_2>; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + wakeup-irq = <347>; + }; + pd_dma_lpuart3: PD_DMA_UART3 { + reg = <SC_R_UART_3>; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + wakeup-irq = <348>; + }; + pd_dma_lpuart4: PD_DMA_UART4 { + reg = <SC_R_UART_4>; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + wakeup-irq = <349>; + }; }; }; + i2c0: i2c@5a800000 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x0 0x5a800000 0x0 0x4000>; + interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QM_I2C0_CLK>, + <&clk IMX8QM_I2C0_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_I2C0_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_dma_lpi2c0>; + status = "disabled"; + }; + + i2c1: i2c@5a810000 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x0 0x5a810000 0x0 0x4000>; + interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QM_I2C1_CLK>, + <&clk IMX8QM_I2C1_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_I2C1_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_dma_lpi2c1>; + status = "disabled"; + }; + + i2c2: i2c@5a820000 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x0 0x5a820000 0x0 0x4000>; + interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QM_I2C2_CLK>, + <&clk IMX8QM_I2C2_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_I2C2_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_dma_lpi2c2>; + status = "disabled"; + }; + + i2c3: i2c@5a830000 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x0 0x5a830000 0x0 0x4000>; + interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QM_I2C3_CLK>, + <&clk IMX8QM_I2C3_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_I2C3_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_dma_lpi2c3>; + status = "disabled"; + }; + + i2c4: i2c@5a840000 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x0 0x5a840000 0x0 0x4000>; + interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QM_I2C4_CLK>, + <&clk IMX8QM_I2C4_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_I2C4_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_dma_lpi2c4>; + status = "disabled"; + }; + gpio0: gpio@5d080000 { compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; reg = <0x0 0x5d080000 0x0 0x10000>; @@ -297,6 +400,58 @@ status = "disabled"; }; + lpuart1: serial@5a070000 { + compatible = "fsl,imx8qm-lpuart"; + reg = <0x0 0x5a070000 0x0 0x1000>; + interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8QM_UART1_CLK>, + <&clk IMX8QM_UART1_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_UART1_CLK>; + assigned-clock-rates = <80000000>; + power-domains = <&pd_dma_lpuart1>; + status = "disabled"; + }; + + lpuart2: serial@5a080000 { + compatible = "fsl,imx8qm-lpuart"; + reg = <0x0 0x5a080000 0x0 0x1000>; + interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8QM_UART2_CLK>, + <&clk IMX8QM_UART2_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_UART2_CLK>; + assigned-clock-rates = <80000000>; + power-domains = <&pd_dma_lpuart2>; + status = "disabled"; + }; + + lpuart3: serial@5a090000 { + compatible = "fsl,imx8qm-lpuart"; + reg = <0x0 0x5a090000 0x0 0x1000>; + interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8QM_UART3_CLK>, + <&clk IMX8QM_UART3_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_UART3_CLK>; + assigned-clock-rates = <80000000>; + power-domains = <&pd_dma_lpuart3>; + status = "disabled"; + }; + + lpuart4: serial@5a0a0000 { + compatible = "fsl,imx8qm-lpuart"; + reg = <0x0 0x5a0a0000 0x0 0x1000>; + interrupts = <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8QM_UART4_CLK>, + <&clk IMX8QM_UART4_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_UART4_CLK>; + assigned-clock-rates = <80000000>; + power-domains = <&pd_dma_lpuart4>; + status = "disabled"; + }; + usdhc1: usdhc@5b010000 { compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc"; interrupt-parent = <&gic>; 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