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Diffstat (limited to 'arch/arm/dts/fsl-lx2160a-qds.dts')
-rw-r--r--arch/arm/dts/fsl-lx2160a-qds.dts67
1 files changed, 3 insertions, 64 deletions
diff --git a/arch/arm/dts/fsl-lx2160a-qds.dts b/arch/arm/dts/fsl-lx2160a-qds.dts
index 592fd5977e..e0f5d5e2d3 100644
--- a/arch/arm/dts/fsl-lx2160a-qds.dts
+++ b/arch/arm/dts/fsl-lx2160a-qds.dts
@@ -1,14 +1,14 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
- * NXP LX2160AQDS device tree source
+ * NXP LX2160AQDS default device tree source
*
- * Copyright 2018-2019 NXP
+ * Copyright 2020 NXP
*
*/
/dts-v1/;
-#include "fsl-lx2160a.dtsi"
+#include "fsl-lx2160a-qds.dtsi"
/ {
model = "NXP Layerscape LX2160AQDS Board";
@@ -17,64 +17,3 @@
spi0 = &fspi;
};
};
-
-&esdhc0 {
- status = "okay";
-};
-
-&esdhc1 {
- status = "okay";
-};
-
-&i2c0 {
- status = "okay";
- u-boot,dm-pre-reloc;
-
- i2c-mux@77 {
- compatible = "nxp,pca9547";
- reg = <0x77>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- i2c@3 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x3>;
-
- rtc@51 {
- compatible = "pcf2127-rtc";
- reg = <0x51>;
- };
- };
- };
-};
-
-&fspi {
- status = "okay";
-
- mt35xu512aba0: flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "jedec,spi-nor";
- spi-max-frequency = <50000000>;
- reg = <0>;
- spi-rx-bus-width = <8>;
- spi-tx-bus-width = <1>;
- };
-};
-
-&sata0 {
- status = "okay";
-};
-
-&sata1 {
- status = "okay";
-};
-
-&sata2 {
- status = "okay";
-};
-
-&sata3 {
- status = "okay";
-};