1 files changed, 0 insertions, 81 deletions
diff --git a/arch/arm/dts/imx6ul-phycore-segin.dts b/arch/arm/dts/imx6ul-phycore-segin.dts
deleted file mode 100644
index 7d68bf8430..0000000000
--- a/arch/arm/dts/imx6ul-phycore-segin.dts
+++ /dev/null
@@ -1,81 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Collabora Ltd.
- *
- * Based on dts[i] from Phytec barebox port:
- * Copyright (C) 2016 PHYTEC Messtechnik GmbH
- * Author: Christian Hemp <c.hemp@phytec.de>
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-/dts-v1/;
-
-#include "imx6ul.dtsi"
-#include "pcl063-common.dtsi"
-
-/ {
-	model = "Phytec phyBOARD-i.MX6UL-Segin SBC";
-	compatible = "phytec,phyboard-imx6ul-segin", "phytec,imx6ul-pcl063",
-		     "fsl,imx6ul";
-};
-
-&gpmi {
-	status = "okay";
-};
-
-&i2c1 {
-	i2c_rtc: rtc@68 {
-		compatible = "microcrystal,rv4162";
-		reg = <0x68>;
-		status = "okay";
-	};
-};
-
-&uart5 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_uart5>;
-	uart-has-rtscts;
-	status = "okay";
-};
-
-&usbotg1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_usb_otg1_id>;
-	dr_mode = "otg";
-	srp-disable;
-	hnp-disable;
-	adp-disable;
-	status = "okay";
-};
-
-&usbotg2 {
-	dr_mode = "host";
-	disable-over-current;
-	status = "okay";
-};
-
-&iomuxc {
-	pinctrl-names = "default";
-
-	pinctrl_uart5: uart5grp {
-		fsl,pins = <
-			MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX	0x1b0b1
-			MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX	0x1b0b1
-			MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS	0x1b0b1
-			MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS	0x1b0b1
-		>;
-	};
-
-	pinctrl_usb_otg1_id: usbotg1idgrp {
-		fsl,pins = <
-			MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID    0x17059
-		>;
-	};
-
-};