diff options
Diffstat (limited to 'arch/arm/dts/imx6ull-phycore-segin.dts')
| -rw-r--r-- | arch/arm/dts/imx6ull-phycore-segin.dts | 70 |
1 files changed, 70 insertions, 0 deletions
diff --git a/arch/arm/dts/imx6ull-phycore-segin.dts b/arch/arm/dts/imx6ull-phycore-segin.dts new file mode 100644 index 0000000000..6df3ad2e4a --- /dev/null +++ b/arch/arm/dts/imx6ull-phycore-segin.dts @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Parthiban Nallathambi <parthitce@gmail.com> + */ + +/dts-v1/; + +#include "imx6ull.dtsi" +#include "pcl063-common.dtsi" + +/ { + model = "Phytec phyBOARD-i.MX6ULL-Segin SBC"; + compatible = "phytec,phyboard-imx6ull-segin", "phytec,imx6ull-pcl063", + "fsl,imx6ull"; +}; + +&i2c1 { + i2c_rtc: rtc@68 { + compatible = "microcrystal,rv4162"; + reg = <0x68>; + status = "okay"; + }; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + uart-has-rtscts; + status = "okay"; +}; + +&usdhc2 { + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1_id>; + dr_mode = "otg"; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1 + MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1 + MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x1b0b1 + MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x1b0b1 + >; + }; + + pinctrl_usb_otg1_id: usbotg1idgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 + >; + }; + +}; |