summaryrefslogtreecommitdiff
path: root/arch/arm/dts/imx7d-sdb-qspi.dts
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/dts/imx7d-sdb-qspi.dts')
-rw-r--r--arch/arm/dts/imx7d-sdb-qspi.dts44
1 files changed, 44 insertions, 0 deletions
diff --git a/arch/arm/dts/imx7d-sdb-qspi.dts b/arch/arm/dts/imx7d-sdb-qspi.dts
new file mode 100644
index 0000000000..9bb4c743c1
--- /dev/null
+++ b/arch/arm/dts/imx7d-sdb-qspi.dts
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ * Copyright 2018 NXP
+ */
+
+#include "imx7d-sdb.dts"
+
+/* disable epdc, conflict with qspi */
+&epdc {
+ status = "disabled";
+};
+
+&iomuxc {
+ qspi1 {
+ pinctrl_qspi1_1: qspi1grp_1 {
+ fsl,pins = <
+ MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 0x51
+ MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 0x51
+ MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 0x51
+ MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 0x51
+ MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK 0x51
+ MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B 0x51
+ >;
+ };
+ };
+};
+
+&qspi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_qspi1_1>;
+ status = "okay";
+ ddrsmp=<0>;
+
+ flash0: mx25l51245g@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "macronix,mx25l51245g";
+ spi-max-frequency = <29000000>;
+ /* take off one dummy cycle */
+ spi-nor,ddr-quad-read-dummy = <5>;
+ reg = <0>;
+ };
+};