summaryrefslogtreecommitdiff
path: root/arch/arm/dts/stm32f746-disco-u-boot.dtsi
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/dts/stm32f746-disco-u-boot.dtsi')
-rw-r--r--arch/arm/dts/stm32f746-disco-u-boot.dtsi251
1 files changed, 251 insertions, 0 deletions
diff --git a/arch/arm/dts/stm32f746-disco-u-boot.dtsi b/arch/arm/dts/stm32f746-disco-u-boot.dtsi
new file mode 100644
index 0000000000..bc337b1628
--- /dev/null
+++ b/arch/arm/dts/stm32f746-disco-u-boot.dtsi
@@ -0,0 +1,251 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <stm32f7-u-boot.dtsi>
+/{
+ chosen {
+ bootargs = "root=/dev/ram rdinit=/linuxrc";
+ };
+
+ aliases {
+ /* Aliases for gpios so as to use sequence */
+ gpio0 = &gpioa;
+ gpio1 = &gpiob;
+ gpio2 = &gpioc;
+ gpio3 = &gpiod;
+ gpio4 = &gpioe;
+ gpio5 = &gpiof;
+ gpio6 = &gpiog;
+ gpio7 = &gpioh;
+ gpio8 = &gpioi;
+ gpio9 = &gpioj;
+ gpio10 = &gpiok;
+ mmc0 = &sdio1;
+ spi0 = &qspi;
+ };
+
+ backlight: backlight {
+ compatible = "gpio-backlight";
+ gpios = <&gpiok 3 0>;
+ status = "okay";
+ };
+
+ button1 {
+ compatible = "st,button1";
+ button-gpio = <&gpioi 11 0>;
+ };
+
+ led1 {
+ compatible = "st,led1";
+ led-gpio = <&gpioi 1 0>;
+ };
+
+ panel-rgb@0 {
+ compatible = "simple-panel";
+ backlight = <&backlight>;
+ enable-gpios = <&gpioi 12 0>;
+ status = "okay";
+
+ display-timings {
+ timing@0 {
+ clock-frequency = <9000000>;
+ hactive = <480>;
+ vactive = <272>;
+ hfront-porch = <2>;
+ hback-porch = <2>;
+ hsync-len = <41>;
+ vfront-porch = <2>;
+ vback-porch = <2>;
+ vsync-len = <10>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ de-active = <0>;
+ pixelclk-active = <1>;
+ };
+ };
+ };
+
+ soc {
+ ltdc: display-controller@40016800 {
+ compatible = "st,stm32-ltdc";
+ reg = <0x40016800 0x200>;
+ resets = <&rcc STM32F7_APB2_RESET(LTDC)>;
+ clocks = <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>;
+ pinctrl-0 = <&ltdc_pins>;
+
+ status = "okay";
+ u-boot,dm-pre-reloc;
+ };
+ };
+};
+
+&clk_hse {
+ u-boot,dm-pre-reloc;
+};
+
+&fmc {
+ /* Memory configuration from sdram datasheet MT48LC_4M32_B2B5-6A */
+ bank1: bank@0 {
+ u-boot,dm-pre-reloc;
+ st,sdram-control = /bits/ 8 <NO_COL_8
+ NO_ROW_12
+ MWIDTH_16
+ BANKS_4
+ CAS_3
+ SDCLK_2
+ RD_BURST_EN
+ RD_PIPE_DL_0>;
+ st,sdram-timing = /bits/ 8 <TMRD_2
+ TXSR_6
+ TRAS_4
+ TRC_6
+ TWR_2
+ TRP_2
+ TRCD_2>;
+ /* refcount = (64msec/total_row_sdram)*freq - 20 */
+ st,sdram-refcount = < 1542 >;
+ };
+};
+
+&pinctrl {
+ ethernet_mii: mii@0 {
+ pins {
+ pinmux = <STM32_PINMUX('G',13, AF11)>, /* ETH_RMII_TXD0 */
+ <STM32_PINMUX('G',14, AF11)>, /* ETH_RMII_TXD1 */
+ <STM32_PINMUX('G',11, AF11)>, /* ETH_RMII_TX_EN */
+ <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
+ <STM32_PINMUX('C', 1, AF11)>, /* ETH_MDC */
+ <STM32_PINMUX('A', 1, AF11)>, /* ETH_RMII_REF_CLK */
+ <STM32_PINMUX('A', 7, AF11)>, /* ETH_RMII_CRS_DV */
+ <STM32_PINMUX('C', 4, AF11)>, /* ETH_RMII_RXD0 */
+ <STM32_PINMUX('C', 5, AF11)>; /* ETH_RMII_RXD1 */
+ slew-rate = <2>;
+ };
+ };
+
+ fmc_pins: fmc@0 {
+ u-boot,dm-pre-reloc;
+ pins {
+ u-boot,dm-pre-reloc;
+ pinmux = <STM32_PINMUX('D',10, AF12)>, /* D15 */
+ <STM32_PINMUX('D', 9, AF12)>, /* D14 */
+ <STM32_PINMUX('D', 8, AF12)>, /* D13 */
+ <STM32_PINMUX('E',15, AF12)>, /* D12 */
+ <STM32_PINMUX('E',14, AF12)>, /* D11 */
+ <STM32_PINMUX('E',13, AF12)>, /* D10 */
+ <STM32_PINMUX('E',12, AF12)>, /* D9 */
+ <STM32_PINMUX('E',11, AF12)>, /* D8 */
+ <STM32_PINMUX('E',10, AF12)>, /* D7 */
+ <STM32_PINMUX('E', 9, AF12)>, /* D6 */
+ <STM32_PINMUX('E', 8, AF12)>, /* D5 */
+ <STM32_PINMUX('E', 7, AF12)>, /* D4 */
+ <STM32_PINMUX('D', 1, AF12)>, /* D3 */
+ <STM32_PINMUX('D', 0, AF12)>, /* D2 */
+ <STM32_PINMUX('D',15, AF12)>, /* D1 */
+ <STM32_PINMUX('D',14, AF12)>, /* D0 */
+
+ <STM32_PINMUX('E', 1, AF12)>, /* NBL1 */
+ <STM32_PINMUX('E', 0, AF12)>, /* NBL0 */
+
+ <STM32_PINMUX('G', 5, AF12)>, /* BA1 */
+ <STM32_PINMUX('G', 4, AF12)>, /* BA0 */
+
+ <STM32_PINMUX('G', 1, AF12)>, /* A11 */
+ <STM32_PINMUX('G', 0, AF12)>, /* A10 */
+ <STM32_PINMUX('F',15, AF12)>, /* A9 */
+ <STM32_PINMUX('F',14, AF12)>, /* A8 */
+ <STM32_PINMUX('F',13, AF12)>, /* A7 */
+ <STM32_PINMUX('F',12, AF12)>, /* A6 */
+ <STM32_PINMUX('F', 5, AF12)>, /* A5 */
+ <STM32_PINMUX('F', 4, AF12)>, /* A4 */
+ <STM32_PINMUX('F', 3, AF12)>, /* A3 */
+ <STM32_PINMUX('F', 2, AF12)>, /* A2 */
+ <STM32_PINMUX('F', 1, AF12)>, /* A1 */
+ <STM32_PINMUX('F', 0, AF12)>, /* A0 */
+
+ <STM32_PINMUX('H', 3, AF12)>, /* SDNE0 */
+ <STM32_PINMUX('H', 5, AF12)>, /* SDNWE */
+ <STM32_PINMUX('F',11, AF12)>, /* SDNRAS */
+ <STM32_PINMUX('G',15, AF12)>, /* SDNCAS */
+ <STM32_PINMUX('C', 3, AF12)>, /* SDCKE0 */
+ <STM32_PINMUX('G', 8, AF12)>; /* SDCLK> */
+ slew-rate = <2>;
+ };
+ };
+
+ ltdc_pins: ltdc@0 {
+ pins {
+ pinmux = <STM32_PINMUX('E', 4, AF14)>, /* B0 */
+ <STM32_PINMUX('G',12, AF14)>, /* B4 */
+ <STM32_PINMUX('I', 9, AF14)>, /* VSYNC */
+ <STM32_PINMUX('I',10, AF14)>, /* HSYNC */
+ <STM32_PINMUX('I',14, AF14)>, /* CLK */
+ <STM32_PINMUX('I',15, AF14)>, /* R0 */
+ <STM32_PINMUX('J', 0, AF14)>, /* R1 */
+ <STM32_PINMUX('J', 1, AF14)>, /* R2 */
+ <STM32_PINMUX('J', 2, AF14)>, /* R3 */
+ <STM32_PINMUX('J', 3, AF14)>, /* R4 */
+ <STM32_PINMUX('J', 4, AF14)>, /* R5 */
+ <STM32_PINMUX('J', 5, AF14)>, /* R6 */
+ <STM32_PINMUX('J', 6, AF14)>, /* R7 */
+ <STM32_PINMUX('J', 7, AF14)>, /* G0 */
+ <STM32_PINMUX('J', 8, AF14)>, /* G1 */
+ <STM32_PINMUX('J', 9, AF14)>, /* G2 */
+ <STM32_PINMUX('J',10, AF14)>, /* G3 */
+ <STM32_PINMUX('J',11, AF14)>, /* G4 */
+ <STM32_PINMUX('J',13, AF14)>, /* B1 */
+ <STM32_PINMUX('J',14, AF14)>, /* B2 */
+ <STM32_PINMUX('J',15, AF14)>, /* B3 */
+ <STM32_PINMUX('K', 0, AF14)>, /* G5 */
+ <STM32_PINMUX('K', 1, AF14)>, /* G6 */
+ <STM32_PINMUX('K', 2, AF14)>, /* G7 */
+ <STM32_PINMUX('K', 4, AF14)>, /* B5 */
+ <STM32_PINMUX('K', 5, AF14)>, /* B6 */
+ <STM32_PINMUX('K', 6, AF14)>, /* B7 */
+ <STM32_PINMUX('K', 7, AF14)>; /* DE */
+ slew-rate = <2>;
+ };
+ };
+
+ qspi_pins: qspi@0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 2, AF9)>, /* CLK */
+ <STM32_PINMUX('B', 6, AF10)>, /* BK1_NCS */
+ <STM32_PINMUX('D',11, AF9)>, /* BK1_IO0 */
+ <STM32_PINMUX('D',12, AF9)>, /* BK1_IO1 */
+ <STM32_PINMUX('D',13, AF9)>, /* BK1_IO3 */
+ <STM32_PINMUX('E', 2, AF9)>; /* BK1_IO2 */
+ slew-rate = <2>;
+ };
+ };
+
+ usart1_pins_b: usart1@1 {
+ u-boot,dm-pre-reloc;
+ pins1 {
+ u-boot,dm-pre-reloc;
+ };
+ pins2 {
+ u-boot,dm-pre-reloc;
+ };
+ };
+};
+
+&pwrcfg {
+ u-boot,dm-pre-reloc;
+};
+
+&qspi {
+ qflash0: n25q128a {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "micron,n25q128a13", "jedec,spi-nor";
+ spi-max-frequency = <108000000>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <1>;
+ memory-map = <0x90000000 0x1000000>;
+ reg = <0>;
+ };
+};
+
+&timer5 {
+ u-boot,dm-pre-reloc;
+};
generated by cgit (git 2.34.1) at 2025-01-01 07:35:46 +0000