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-rw-r--r--arch/arm/dts/Makefile4
-rw-r--r--arch/arm/dts/mt7622-bananapi-bpi-r64.dts (renamed from arch/arm/dts/mt7622-bpi-r64.dts)8
-rw-r--r--arch/arm/dts/mt7622-rfb.dts8
-rw-r--r--arch/arm/dts/mt7622.dtsi56
-rw-r--r--arch/arm/dts/mt7623.dtsi46
-rw-r--r--arch/arm/dts/mt7623n-bananapi-bpi-r2.dts16
-rw-r--r--arch/arm/dts/total_compute.dts48
7 files changed, 185 insertions, 1 deletions
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index b2b5360f6d..f8f529435b 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -962,7 +962,7 @@ dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb \
dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt7622-rfb.dtb \
mt7623a-unielec-u7623-02-emmc.dtb \
- mt7622-bpi-r64.dtb \
+ mt7622-bananapi-bpi-r64.dtb \
mt7623n-bananapi-bpi-r2.dtb \
mt7629-rfb.dtb \
mt8512-bm1-emmc.dtb \
@@ -981,6 +981,8 @@ dtb-$(CONFIG_TARGET_VEXPRESS_CA5X2) += vexpress-v2p-ca5s.dtb
dtb-$(CONFIG_TARGET_VEXPRESS_CA9X4) += vexpress-v2p-ca9.dtb
dtb-$(CONFIG_TARGET_VEXPRESS_CA15_TC2) += vexpress-v2p-ca15_a7.dtb
+dtb-$(CONFIG_TARGET_TOTAL_COMPUTE) += total_compute.dtb
+
dtb-$(CONFIG_TARGET_DURIAN) += phytium-durian.dtb
dtb-$(CONFIG_TARGET_PRESIDIO_ASIC) += ca-presidio-engboard.dtb
diff --git a/arch/arm/dts/mt7622-bpi-r64.dts b/arch/arm/dts/mt7622-bananapi-bpi-r64.dts
index 51287cea3a..4f2f04851d 100644
--- a/arch/arm/dts/mt7622-bpi-r64.dts
+++ b/arch/arm/dts/mt7622-bananapi-bpi-r64.dts
@@ -244,3 +244,11 @@
output-low;
};
};
+
+&ssusb {
+ status = "okay";
+};
+
+&u3phy {
+ status = "okay";
+};
diff --git a/arch/arm/dts/mt7622-rfb.dts b/arch/arm/dts/mt7622-rfb.dts
index 317fc78abd..ef7d0f0270 100644
--- a/arch/arm/dts/mt7622-rfb.dts
+++ b/arch/arm/dts/mt7622-rfb.dts
@@ -222,3 +222,11 @@
full-duplex;
};
};
+
+&ssusb {
+ status = "okay";
+};
+
+&u3phy {
+ status = "okay";
+};
diff --git a/arch/arm/dts/mt7622.dtsi b/arch/arm/dts/mt7622.dtsi
index c43ad65702..d888545809 100644
--- a/arch/arm/dts/mt7622.dtsi
+++ b/arch/arm/dts/mt7622.dtsi
@@ -192,6 +192,14 @@
status = "disabled";
};
+ ssusbsys: ssusbsys@1a000000 {
+ compatible = "mediatek,mt7622-ssusbsys",
+ "syscon";
+ reg = <0x1a000000 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
pciesys: pciesys@1a100800 {
compatible = "mediatek,mt7622-pciesys", "syscon";
reg = <0x1a100800 0x1000>;
@@ -302,6 +310,54 @@
};
};
+ ssusb: usb@1a0c0000 {
+ compatible = "mediatek,mt7622-xhci",
+ "mediatek,mtk-xhci";
+ reg = <0x1a0c0000 0x01000>,
+ <0x1a0c4700 0x0100>;
+ reg-names = "mac", "ippc";
+ interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT7629_POWER_DOMAIN_HIF1>;
+ clocks = <&ssusbsys CLK_SSUSB_SYS_EN>,
+ <&ssusbsys CLK_SSUSB_REF_EN>,
+ <&ssusbsys CLK_SSUSB_MCU_EN>,
+ <&ssusbsys CLK_SSUSB_DMA_EN>;
+ clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
+ phys = <&u2port0 PHY_TYPE_USB2>,
+ <&u3port0 PHY_TYPE_USB3>,
+ <&u2port1 PHY_TYPE_USB2>;
+ status = "disabled";
+ };
+
+ u3phy: usb-phy@1a0c4000 {
+ compatible = "mediatek,mt7622-u3phy",
+ "mediatek,generic-tphy-v1";
+ reg = <0x1a0c4000 0x700>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ status = "disabled";
+
+ u2port0: usb-phy@1a0c4800 {
+ reg = <0x1a0c4800 0x0100>;
+ #phy-cells = <1>;
+ clocks = <&ssusbsys CLK_SSUSB_U2_PHY_EN>;
+ clock-names = "ref";
+ };
+
+ u3port0: usb-phy@1a0c4900 {
+ reg = <0x1a0c4900 0x0700>;
+ #phy-cells = <1>;
+ };
+
+ u2port1: usb-phy@1a0c5000 {
+ reg = <0x1a0c5000 0x0100>;
+ #phy-cells = <1>;
+ clocks = <&ssusbsys CLK_SSUSB_U2_PHY_1P_EN>;
+ clock-names = "ref";
+ };
+ };
+
ethsys: syscon@1b000000 {
compatible = "mediatek,mt7622-ethsys", "syscon";
reg = <0x1b000000 0x1000>;
diff --git a/arch/arm/dts/mt7623.dtsi b/arch/arm/dts/mt7623.dtsi
index 0452889ef8..b5a802552b 100644
--- a/arch/arm/dts/mt7623.dtsi
+++ b/arch/arm/dts/mt7623.dtsi
@@ -352,6 +352,52 @@
};
};
+ usb1: usb@1a1c0000 {
+ compatible = "mediatek,mt7623-xhci", "mediatek,mtk-xhci";
+ reg = <0x1a1c0000 0x1000>, <0x1a1c4700 0x0100>;
+ reg-names = "mac", "ippc";
+ power-domains = <&scpsys MT7623_POWER_DOMAIN_HIF>;
+ clocks = <&hifsys CLK_HIFSYS_USB0PHY>, <&topckgen CLK_TOP_ETHIF_SEL>;
+ clock-names = "sys_ck", "ref_ck";
+ phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
+ status = "disabled";
+ };
+
+ u3phy1: usb-phy@1a1c4000 {
+ compatible = "mediatek,mt7623-tphy", "mediatek,generic-tphy-v1";
+
+ reg = <0x1a1c4000 0x0700>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ status = "disabled";
+
+ u2port0: usb-phy@1a1c4800 {
+ reg = <0x1a1c4800 0x0100>;
+ #phy-cells = <1>;
+ clocks = <&topckgen CLK_TOP_USB_PHY48M>;
+ clock-names = "ref";
+ };
+
+ u3port0: usb-phy@1a1c4900 {
+ reg = <0x1a1c4900 0x0700>;
+ #phy-cells = <1>;
+ clocks = <&clk26m>;
+ clock-names = "ref";
+ };
+ };
+
+ usb2: usb@1a240000 {
+ compatible = "mediatek,mt7623-xhci", "mediatek,mtk-xhci";
+ reg = <0x1a240000 0x1000>, <0x1a244700 0x0100>;
+ reg-names = "mac", "ippc";
+ power-domains = <&scpsys MT7623_POWER_DOMAIN_HIF>;
+ clocks = <&hifsys CLK_HIFSYS_USB1PHY>, <&topckgen CLK_TOP_ETHIF_SEL>;
+ clock-names = "sys_ck", "ref_ck";
+ phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>;
+ status = "disabled";
+ };
+
u3phy2: usb-phy@1a244000 {
compatible = "mediatek,generic-tphy-v1";
reg = <0x1a244000 0x0700>;
diff --git a/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts b/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts
index bcedcf20f1..ef07369627 100644
--- a/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts
+++ b/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts
@@ -248,3 +248,19 @@
pinctrl-0 = <&uart2_pins_a>;
status = "okay";
};
+
+&usb1 {
+ status = "okay";
+};
+
+&u3phy1 {
+ status = "okay";
+};
+
+&usb2 {
+ status = "okay";
+};
+
+&u3phy2 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/total_compute.dts b/arch/arm/dts/total_compute.dts
new file mode 100644
index 0000000000..4399269a44
--- /dev/null
+++ b/arch/arm/dts/total_compute.dts
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2020 Arm Limited
+ */
+
+/dts-v1/;
+
+/ {
+ model = "total_compute";
+ compatible = "arm,total_compute";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ sysreg: sysreg@1c010000 {
+ compatible = "arm,vexpress-sysreg";
+ reg = <0x0 0x001c010000 0x0 0x1000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ fixed_3v3: v2m-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ mmci@1c050000 {
+ compatible = "arm,pl180", "arm,primecell";
+ reg = <0x0 0x001c050000 0x0 0x1000>;
+ cd-gpios = <&sysreg 0 0>;
+ arm,primecell-periphid = <0x00880180>;
+ wp-gpios = <&sysreg 1 0>;
+ bus-width = <8>;
+ max-frequency = <12000000>;
+ vmmc-supply = <&fixed_3v3>;
+ clocks = <&clock24mhz>, <&clock24mhz>;
+ clock-names = "mclk", "apb_pclk";
+ };
+
+ clock24mhz: clock24mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ clock-output-names = "bp:clock24mhz";
+ };
+};
generated by cgit (git 2.34.1) at 2024-12-23 13:18:24 +0000