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-rw-r--r--arch/arm/dts/Makefile2
-rw-r--r--arch/arm/dts/am3517-evm.dts50
-rw-r--r--arch/arm/dts/am3517-som.dtsi105
-rw-r--r--arch/arm/dts/am3517.dtsi5
-rw-r--r--arch/arm/dts/at91sam9260-smartweb.dts1
-rw-r--r--arch/arm/dts/at91sam9g20-taurus.dts1
-rw-r--r--arch/arm/dts/bcm6858.dtsi85
-rw-r--r--arch/arm/dts/bcm968580xref.dts31
-rw-r--r--arch/arm/dts/k3-am65-main.dtsi51
-rw-r--r--arch/arm/dts/k3-am65-mcu.dtsi18
-rw-r--r--arch/arm/dts/k3-am65-wakeup.dtsi46
-rw-r--r--arch/arm/dts/k3-am65.dtsi54
-rw-r--r--arch/arm/dts/k3-am654-base-board-ddr4-1600MHz.dtsi156
-rw-r--r--arch/arm/dts/k3-am654-base-board-u-boot.dtsi94
-rw-r--r--arch/arm/dts/k3-am654-ddr.dtsi196
-rw-r--r--arch/arm/dts/k3-am654-r5-base-board.dts139
16 files changed, 933 insertions, 101 deletions
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 1cbb45d679..7ed222db86 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -559,7 +559,7 @@ dtb-$(CONFIG_TARGET_STM32MP1) += \
stm32mp157c-ed1.dtb \
stm32mp157c-ev1.dtb
-dtb-$(CONFIG_SOC_K3_AM6) += k3-am654-base-board.dtb
+dtb-$(CONFIG_SOC_K3_AM6) += k3-am654-base-board.dtb k3-am654-r5-base-board.dtb
targets += $(dtb-y)
diff --git a/arch/arm/dts/am3517-evm.dts b/arch/arm/dts/am3517-evm.dts
index 98aadb0f81..1d158cfda1 100644
--- a/arch/arm/dts/am3517-evm.dts
+++ b/arch/arm/dts/am3517-evm.dts
@@ -127,6 +127,7 @@
status = "okay";
pinctrl-names = "default";
enable-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>; /* gpio176, lcd INI */
+ vcc-supply = <&vdd_io_reg>;
port {
lcd_in: endpoint {
@@ -154,6 +155,7 @@
bl: backlight {
compatible = "pwm-backlight";
pinctrl-names = "default";
+ power-supply = <&vdd_io_reg>;
pinctrl-0 = <&backlight_pins>;
pwms = <&pwm11 0 5000000 0>;
brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
@@ -168,6 +170,13 @@
ti,timers = <&timer11>;
#pwm-cells = <3>;
};
+
+ /* HS USB Host PHY on PORT 1 */
+ hsusb1_phy: hsusb1_phy {
+ compatible = "usb-nop-xceiv";
+ reset-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>; /* gpio_57 */
+ #phy-cells = <0>;
+ };
};
&davinci_emac {
@@ -203,6 +212,7 @@
reg = <0x21>;
gpio-controller;
#gpio-cells = <2>;
+ vcc-supply = <&vdd_io_reg>;
};
};
@@ -220,15 +230,21 @@
cd-gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>; /* gpio_127 */
};
-&mmc2 {
+&mmc3 {
status = "disabled";
};
-&mmc3 {
- status = "disabled";
+&usbhshost {
+ port1-mode = "ehci-phy";
+};
+
+&usbhsehci {
+ phys = <&hsusb1_phy>;
};
&omap3_pmx_core {
+ pinctrl-names = "default";
+ pinctrl-0 = <&hsusb1_rst_pins>;
leds_pins: pinmux_leds_pins {
pinctrl-single,pins = <
@@ -287,4 +303,32 @@
OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */
>;
};
+
+ hsusb1_rst_pins: pinmux_hsusb1_rst_pins {
+ pinctrl-single,pins = <
+ OMAP3_CORE1_IOPAD(0x20ba, PIN_OUTPUT | MUX_MODE4) /* gpmc_ncs6.gpio_57 */
+ >;
+ };
+};
+
+&omap3_pmx_core2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&hsusb1_pins>;
+
+ hsusb1_pins: pinmux_hsusb1_pins {
+ pinctrl-single,pins = <
+ OMAP3430_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE3) /* etk_clk.hsusb1_stp */
+ OMAP3430_CORE2_IOPAD(0x25da, PIN_OUTPUT | MUX_MODE3) /* etk_ctl.hsusb1_clk */
+ OMAP3430_CORE2_IOPAD(0x25ec, PIN_INPUT | MUX_MODE3) /* etk_d8.hsusb1_dir */
+ OMAP3430_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE3) /* etk_d9.hsusb1_nxt */
+ OMAP3430_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE3) /* etk_d0.hsusb1_data0 */
+ OMAP3430_CORE2_IOPAD(0x25de, PIN_INPUT | MUX_MODE3) /* etk_d1.hsusb1_data1 */
+ OMAP3430_CORE2_IOPAD(0x25e0, PIN_INPUT | MUX_MODE3) /* etk_d2.hsusb1_data2 */
+ OMAP3430_CORE2_IOPAD(0x25ea, PIN_INPUT | MUX_MODE3) /* etk_d7.hsusb1_data3 */
+ OMAP3430_CORE2_IOPAD(0x25e4, PIN_INPUT | MUX_MODE3) /* etk_d4.hsusb1_data4 */
+ OMAP3430_CORE2_IOPAD(0x25e6, PIN_INPUT | MUX_MODE3) /* etk_d5.hsusb1_data5 */
+ OMAP3430_CORE2_IOPAD(0x25e8, PIN_INPUT | MUX_MODE3) /* etk_d6.hsusb1_data6 */
+ OMAP3430_CORE2_IOPAD(0x25e2, PIN_INPUT | MUX_MODE3) /* etk_d3.hsusb1_data7 */
+ >;
+ };
};
diff --git a/arch/arm/dts/am3517-som.dtsi b/arch/arm/dts/am3517-som.dtsi
index a6d5ff73c1..dae6e458e5 100644
--- a/arch/arm/dts/am3517-som.dtsi
+++ b/arch/arm/dts/am3517-som.dtsi
@@ -14,6 +14,32 @@
cpu0-supply = <&vdd_core_reg>;
};
};
+
+ wl12xx_buffer: wl12xx_buf {
+ compatible = "regulator-fixed";
+ regulator-name = "wl1271_buf";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&wl12xx_buffer_pins>;
+ gpio = <&gpio5 1 GPIO_ACTIVE_LOW>; /* gpio 129 */
+ regulator-always-on;
+ vin-supply = <&vdd_1v8_reg>;
+ };
+
+ wl12xx_vmmc2: wl12xx_vmmc2 {
+ compatible = "regulator-fixed";
+ regulator-name = "vwl1271";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&wl12xx_wkup_pins>;
+ gpio = <&gpio1 3 GPIO_ACTIVE_HIGH >; /* gpio 3 */
+ startup-delay-us = <70000>;
+ enable-active-high;
+ regulator-always-on;
+ vin-supply = <&wl12xx_buffer>;
+ };
};
&gpmc {
@@ -64,7 +90,6 @@
regulators {
vdd_core_reg: VDCDC1 {
regulator-name = "vdd_core";
- compatible = "regulator-fixed";
regulator-always-on;
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
@@ -72,7 +97,6 @@
vdd_io_reg: VDCDC2 {
regulator-name = "vdd_io";
- compatible = "regulator-fixed";
regulator-always-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
@@ -80,7 +104,6 @@
vdd_1v8_reg: VDCDC3 {
regulator-name = "vdd_1v8";
- compatible = "regulator-fixed";
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
@@ -88,7 +111,6 @@
vdd_usb18_reg: LDO1 {
regulator-name = "vdd_usb18";
- compatible = "regulator-fixed";
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
@@ -96,7 +118,6 @@
vdd_usb33_reg: LDO2 {
regulator-name = "vdd_usb33";
- compatible = "regulator-fixed";
regulator-always-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
@@ -126,8 +147,63 @@
};
};
+&mmc2 {
+ interrupts-extended = <&intc 86 /* &omap3_pmx_core 0x12c */>;
+
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_pins>;
+ vmmc-supply = <&wl12xx_vmmc2>;
+ non-removable;
+ bus-width = <4>;
+ cap-power-off-card;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ wlcore: wlcore@2 {
+ compatible = "ti,wl1271";
+ reg = <2>;
+ interrupt-parent = <&gpio6>;
+ interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; /* gpio_170 */
+ ref-clock-frequency = <26000000>;
+ tcxo-clock-frequency = <26000000>;
+ };
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>;
+
+ bluetooth {
+ compatible = "ti,wl1271-st";
+ enable-gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>; /* gpio 56 */
+ max-speed = <3000000>;
+ };
+};
+
&omap3_pmx_core {
+ wl12xx_buffer_pins: pinmux_wl12xx_buffer_pins {
+ pinctrl-single,pins = <
+ OMAP3_CORE1_IOPAD(0x2156, PIN_OUTPUT | MUX_MODE4) /* mmc1_dat7.gpio_129 */
+ >;
+ };
+
+ mmc2_pins: pinmux_mmc2_pins {
+ pinctrl-single,pins = <
+ OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_clk.mmc2_clk */
+ OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_cmd.mmc2_cmd */
+ OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_dat0.mmc2_dat0 */
+ OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_dat1.mmc2_dat1 */
+ OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_dat2.mmc2_dat2 */
+ OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_dat3.mmc2_dat3 */
+ OMAP3_CORE1_IOPAD(0x2164, PIN_OUTPUT | MUX_MODE1) /* mmc2_dat4.mmc2_dir_dat0 */
+ OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE1) /* mmc2_dat5.mmc2_dir_dat1 */
+ OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE1) /* mmc2_dat6.mmc2_dir_cmd */
+ OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT | MUX_MODE1) /* mmc2_dat7.mmc2_clkin */
+ OMAP3_CORE1_IOPAD(0x21c6, PIN_INPUT_PULLUP | MUX_MODE4) /* hdq_sio.gpio_170 */
+ >;
+ };
+
rtc_pins: pinmux_rtc_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x20b6, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_ncs4.gpio_55 */
@@ -139,4 +215,23 @@
OMAP3_CORE1_IOPAD(0x20d2, PIN_INPUT | MUX_MODE4) /* gpmc_wait3.gpio_65 */
>;
};
+
+ uart2_pins: pinmux_uart2_pins {
+ pinctrl-single,pins = <
+ OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts */
+ OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT_PULLUP | MUX_MODE0) /* uart2_rts */
+ OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx */
+ OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx */
+ OMAP3_CORE1_IOPAD(0x20b8, PIN_INPUT | MUX_MODE0) /* gpio_56 */
+ >;
+ };
+};
+
+&omap3_pmx_wkup {
+
+ wl12xx_wkup_pins: pinmux_wl12xx_wkup_pins {
+ pinctrl-single,pins = <
+ OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE4) /* sys_boot1.gpio_3 */
+ >;
+ };
};
diff --git a/arch/arm/dts/am3517.dtsi b/arch/arm/dts/am3517.dtsi
index 4b6062b631..23ea381d36 100644
--- a/arch/arm/dts/am3517.dtsi
+++ b/arch/arm/dts/am3517.dtsi
@@ -91,6 +91,11 @@
};
};
+/* Table Table 5-79 of the TRM shows 480ab000 is reserved */
+&usb_otg_hs {
+ status = "disabled";
+};
+
&iva {
status = "disabled";
};
diff --git a/arch/arm/dts/at91sam9260-smartweb.dts b/arch/arm/dts/at91sam9260-smartweb.dts
index e59781bf45..a22de2d927 100644
--- a/arch/arm/dts/at91sam9260-smartweb.dts
+++ b/arch/arm/dts/at91sam9260-smartweb.dts
@@ -89,6 +89,7 @@
};
watchdog@fffffd40 {
+ timeout-sec = <15>;
status = "okay";
};
diff --git a/arch/arm/dts/at91sam9g20-taurus.dts b/arch/arm/dts/at91sam9g20-taurus.dts
index 7931c0af7b..cee228bb8c 100644
--- a/arch/arm/dts/at91sam9g20-taurus.dts
+++ b/arch/arm/dts/at91sam9g20-taurus.dts
@@ -98,6 +98,7 @@
};
watchdog@fffffd40 {
+ timeout-sec = <15>;
status = "okay";
};
diff --git a/arch/arm/dts/bcm6858.dtsi b/arch/arm/dts/bcm6858.dtsi
new file mode 100644
index 0000000000..9869d729d3
--- /dev/null
+++ b/arch/arm/dts/bcm6858.dtsi
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Philippe Reynes <philippe.reynes@softathome.com>
+ */
+
+#include "skeleton64.dtsi"
+
+/ {
+ compatible = "brcm,bcm6858";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+ u-boot,dm-pre-reloc;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <0x0 0x0>;
+ next-level-cache = <&l2>;
+ u-boot,dm-pre-reloc;
+ };
+
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <0x0 0x1>;
+ next-level-cache = <&l2>;
+ u-boot,dm-pre-reloc;
+ };
+
+ cpu2: cpu@2 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <0x0 0x2>;
+ next-level-cache = <&l2>;
+ u-boot,dm-pre-reloc;
+ };
+
+ cpu3: cpu@3 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <0x0 0x3>;
+ next-level-cache = <&l2>;
+ u-boot,dm-pre-reloc;
+ };
+
+ l2: l2-cache0 {
+ compatible = "cache";
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ clocks {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ u-boot,dm-pre-reloc;
+
+ periph_osc: periph-osc {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <200000000>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ ubus {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+
+ uart0: serial@ff800640 {
+ compatible = "brcm,bcm6858-uart";
+ reg = <0x0 0xff800640 0x0 0x18>;
+ clocks = <&periph_osc>;
+
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm/dts/bcm968580xref.dts b/arch/arm/dts/bcm968580xref.dts
new file mode 100644
index 0000000000..0c59f94710
--- /dev/null
+++ b/arch/arm/dts/bcm968580xref.dts
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Philippe Reynes <philippe.reynes@softathome.com>
+ */
+
+/dts-v1/;
+
+#include "bcm6858.dtsi"
+
+/ {
+ model = "Broadcom bcm68580xref";
+ compatible = "broadcom,bcm68580xref", "brcm,bcm6858";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x20000000>;
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
diff --git a/arch/arm/dts/k3-am65-main.dtsi b/arch/arm/dts/k3-am65-main.dtsi
index 2409344df4..adcd6341e4 100644
--- a/arch/arm/dts/k3-am65-main.dtsi
+++ b/arch/arm/dts/k3-am65-main.dtsi
@@ -8,13 +8,13 @@
&cbass_main {
gic500: interrupt-controller@1800000 {
compatible = "arm,gic-v3";
- #address-cells = <1>;
- #size-cells = <1>;
+ #address-cells = <2>;
+ #size-cells = <2>;
ranges;
#interrupt-cells = <3>;
interrupt-controller;
- reg = <0x01800000 0x10000>, /* GICD */
- <0x01880000 0x90000>; /* GICR */
+ reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
+ <0x00 0x01880000 0x00 0x90000>; /* GICR */
/*
* vcpumntirq:
* virtual CPU interface maintenance interrupt
@@ -23,9 +23,50 @@
gic_its: gic-its@18200000 {
compatible = "arm,gic-v3-its";
- reg = <0x01820000 0x10000>;
+ reg = <0x00 0x01820000 0x00 0x10000>;
msi-controller;
#msi-cells = <1>;
};
};
+
+ secure_proxy_main: mailbox@32c00000 {
+ compatible = "ti,am654-secure-proxy";
+ #mbox-cells = <1>;
+ reg-names = "target_data", "rt", "scfg";
+ reg = <0x00 0x32c00000 0x00 0x100000>,
+ <0x00 0x32400000 0x00 0x100000>,
+ <0x00 0x32800000 0x00 0x100000>;
+ interrupt-names = "rx_011";
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ main_uart0: serial@2800000 {
+ compatible = "ti,am654-uart";
+ reg = <0x00 0x02800000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ current-speed = <115200>;
+ };
+
+ main_uart1: serial@2810000 {
+ compatible = "ti,am654-uart";
+ reg = <0x00 0x02810000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ current-speed = <115200>;
+ };
+
+ main_uart2: serial@2820000 {
+ compatible = "ti,am654-uart";
+ reg = <0x00 0x02820000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ current-speed = <115200>;
+ };
};
diff --git a/arch/arm/dts/k3-am65-mcu.dtsi b/arch/arm/dts/k3-am65-mcu.dtsi
new file mode 100644
index 0000000000..8c611d16df
--- /dev/null
+++ b/arch/arm/dts/k3-am65-mcu.dtsi
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for AM6 SoC Family MCU Domain peripherals
+ *
+ * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+&cbass_mcu {
+ mcu_uart0: serial@40a00000 {
+ compatible = "ti,am654-uart";
+ reg = <0x00 0x40a00000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <96000000>;
+ current-speed = <115200>;
+ };
+};
diff --git a/arch/arm/dts/k3-am65-wakeup.dtsi b/arch/arm/dts/k3-am65-wakeup.dtsi
new file mode 100644
index 0000000000..8d7b47f9df
--- /dev/null
+++ b/arch/arm/dts/k3-am65-wakeup.dtsi
@@ -0,0 +1,46 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for AM6 SoC Family Wakeup Domain peripherals
+ *
+ * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+&cbass_wakeup {
+ dmsc: dmsc {
+ compatible = "ti,k2g-sci";
+ ti,host-id = <12>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ mbox-names = "rx", "tx";
+
+ mboxes= <&secure_proxy_main 11>,
+ <&secure_proxy_main 13>;
+
+ k3_pds: power-controller {
+ compatible = "ti,sci-pm-domain";
+ #power-domain-cells = <1>;
+ };
+
+ k3_clks: clocks {
+ compatible = "ti,k2g-sci-clk";
+ #clock-cells = <2>;
+ };
+
+ k3_reset: reset-controller {
+ compatible = "ti,sci-reset";
+ #reset-cells = <2>;
+ };
+ };
+
+ wkup_uart0: serial@42300000 {
+ compatible = "ti,am654-uart";
+ reg = <0x42300000 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ current-speed = <115200>;
+ };
+};
diff --git a/arch/arm/dts/k3-am65.dtsi b/arch/arm/dts/k3-am65.dtsi
index cede1fa098..3d4bf369d0 100644
--- a/arch/arm/dts/k3-am65.dtsi
+++ b/arch/arm/dts/k3-am65.dtsi
@@ -16,6 +16,14 @@
#address-cells = <2>;
#size-cells = <2>;
+ aliases {
+ serial0 = &wkup_uart0;
+ serial1 = &mcu_uart0;
+ serial2 = &main_uart0;
+ serial3 = &main_uart1;
+ serial4 = &main_uart2;
+ };
+
chosen { };
firmware {
@@ -46,38 +54,38 @@
cbass_main: interconnect@100000 {
compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x00100000 0x00 0x00100000 0x00020000>, /* ctrl mmr */
- <0x00600000 0x00 0x00600000 0x00001100>, /* GPIO */
- <0x00900000 0x00 0x00900000 0x00012000>, /* serdes */
- <0x01000000 0x00 0x01000000 0x0af02400>, /* Most peripherals */
- <0x30800000 0x00 0x30800000 0x0bc00000>, /* MAIN NAVSS */
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
+ <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
+ <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
+ <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
+ <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */
/* MCUSS Range */
- <0x28380000 0x00 0x28380000 0x03880000>,
- <0x40200000 0x00 0x40200000 0x00900100>,
- <0x42040000 0x00 0x42040000 0x03ac2400>,
- <0x45100000 0x00 0x45100000 0x00c24000>,
- <0x46000000 0x00 0x46000000 0x00200000>,
- <0x47000000 0x00 0x47000000 0x00068400>;
+ <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
+ <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>,
+ <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
+ <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
+ <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
+ <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>;
cbass_mcu: interconnect@28380000 {
compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x28380000 0x28380000 0x03880000>, /* MCU NAVSS*/
- <0x40200000 0x40200000 0x00900100>, /* First peripheral window */
- <0x42040000 0x42040000 0x03ac2400>, /* WKUP */
- <0x45100000 0x45100000 0x00c24000>, /* MMRs, remaining NAVSS */
- <0x46000000 0x46000000 0x00200000>, /* CPSW */
- <0x47000000 0x47000000 0x00068400>; /* OSPI space 1 */
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
+ <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>, /* First peripheral window */
+ <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP */
+ <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
+ <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
+ <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>; /* OSPI space 1 */
cbass_wakeup: interconnect@42040000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
/* WKUP Basic peripherals */
- ranges = <0x42040000 0x42040000 0x03ac2400>;
+ ranges = <0x42040000 0x00 0x42040000 0x03ac2400>;
};
};
};
@@ -85,3 +93,5 @@
/* Now include the peripherals for each bus segments */
#include "k3-am65-main.dtsi"
+#include "k3-am65-mcu.dtsi"
+#include "k3-am65-wakeup.dtsi"
diff --git a/arch/arm/dts/k3-am654-base-board-ddr4-1600MHz.dtsi b/arch/arm/dts/k3-am654-base-board-ddr4-1600MHz.dtsi
new file mode 100644
index 0000000000..e861cb7c67
--- /dev/null
+++ b/arch/arm/dts/k3-am654-base-board-ddr4-1600MHz.dtsi
@@ -0,0 +1,156 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * This file was generated by the AM65x_DRA80xM EMIF Tool:
+ * http://www.ti.com/lit/pdf/spracj0
+ * Configuration Parameters
+ * Memory Type: DDR4
+ * Data Rate: 1600
+ * ECC Enabled: No
+ * Data Width: 32
+ */
+#define DDR_PLL_FREQUENCY 400000000
+#define DDRCTL_MSTR 0x41040010
+#define DDRCTL_RFSHCTL0 0x00210070
+#define DDRCTL_ECCCFG0 0x00000000
+#define DDRCTL_RFSHTMG 0x0061008C
+#define DDRCTL_CRCPARCTL0 0x00008000
+#define DDRCTL_CRCPARCTL1 0x1A000000
+#define DDRCTL_CRCPARCTL2 0x0048051E
+#define DDRCTL_INIT0 0x400100C4
+#define DDRCTL_INIT1 0x004F0000
+#define DDRCTL_INIT3 0x02140501
+#define DDRCTL_INIT4 0x00000020
+#define DDRCTL_INIT5 0x00100000
+#define DDRCTL_INIT6 0x00000480
+#define DDRCTL_INIT7 0x000004E8
+#define DDRCTL_DRAMTMG0 0x0C0A1B0D
+#define DDRCTL_DRAMTMG1 0x00030313
+#define DDRCTL_DRAMTMG2 0x0506050A
+#define DDRCTL_DRAMTMG3 0x0000400C
+#define DDRCTL_DRAMTMG4 0x06020206
+#define DDRCTL_DRAMTMG5 0x04040302
+#define DDRCTL_DRAMTMG6 0x00000004
+#define DDRCTL_DRAMTMG7 0x00000404
+#define DDRCTL_DRAMTMG8 0x03030C05
+#define DDRCTL_DRAMTMG9 0x00020208
+#define DDRCTL_DRAMTMG10 0x001C180A
+#define DDRCTL_DRAMTMG11 0x1106010E
+#define DDRCTL_DRAMTMG12 0x00020008
+#define DDRCTL_DRAMTMG13 0x0B100002
+#define DDRCTL_DRAMTMG14 0x00000000
+#define DDRCTL_DRAMTMG15 0x0000003F
+#define DDRCTL_DRAMTMG17 0x00500028
+#define DDRCTL_ZQCTL0 0x21000040
+#define DDRCTL_ZQCTL1 0x0202FAF0
+#define DDRCTL_DFITMG0 0x04888206
+#define DDRCTL_DFITMG1 0x000A0606
+#define DDRCTL_DFITMG2 0x00000604
+#define DDRCTL_DFIMISC 0x00000001
+#define DDRCTL_ADDRMAP0 0x001F1F1F
+#define DDRCTL_ADDRMAP1 0x003F0808
+#define DDRCTL_ADDRMAP2 0x00000000
+#define DDRCTL_ADDRMAP3 0x00000000
+#define DDRCTL_ADDRMAP4 0x00001F1F
+#define DDRCTL_ADDRMAP5 0x08080808
+#define DDRCTL_ADDRMAP6 0x08080808
+#define DDRCTL_ADDRMAP7 0x00000F0F
+#define DDRCTL_ADDRMAP8 0x00000A0A
+#define DDRCTL_ADDRMAP9 0x00000000
+#define DDRCTL_ADDRMAP10 0x00000000
+#define DDRCTL_ADDRMAP11 0x001F1F00
+#define DDRCTL_DQMAP0 0x00000000
+#define DDRCTL_DQMAP1 0x00000000
+#define DDRCTL_DQMAP4 0x00000000
+#define DDRCTL_DQMAP5 0x00000000
+#define DDRCTL_PWRCTL 0x00000000
+#define DDRCTL_RANKCTL 0x00000000
+#define DDRCTL_ODTCFG 0x0600060C
+#define DDRCTL_ODTMAP 0x00000001
+#define DDRPHY_PGCR0 0x07001E00
+#define DDRPHY_PGCR1 0x020046C0
+#define DDRPHY_PGCR2 0x00F0BFE0
+#define DDRPHY_PGCR3 0x55AA0080
+#define DDRPHY_PGCR6 0x00013001
+#define DDRPHY_PTR2 0x00083DEF
+#define DDRPHY_PTR3 0x00061A80
+#define DDRPHY_PTR4 0x00000120
+#define DDRPHY_PTR5 0x00027100
+#define DDRPHY_PTR6 0x04000320
+#define DDRPHY_PLLCR0 0x021c4000
+#define DDRPHY_DXCCR 0x00000038
+#define DDRPHY_DSGCR 0x02A0C129
+#define DDRPHY_DCR 0x0000040C
+#define DDRPHY_DTPR0 0x041A0B06
+#define DDRPHY_DTPR1 0x28140000
+#define DDRPHY_DTPR2 0x0034E300
+#define DDRPHY_DTPR3 0x02800800
+#define DDRPHY_DTPR4 0x31180805
+#define DDRPHY_DTPR5 0x00250B06
+#define DDRPHY_DTPR6 0x00000505
+#define DDRPHY_ZQCR 0x008A2A58
+#define DDRPHY_ZQ0PR0 0x000077DD
+#define DDRPHY_ZQ1PR0 0x000077DD
+#define DDRPHY_MR0 0x00000214
+#define DDRPHY_MR1 0x00000501
+#define DDRPHY_MR2 0x00000000
+#define DDRPHY_MR3 0x00000020
+#define DDRPHY_MR4 0x00000000
+#define DDRPHY_MR5 0x00000480
+#define DDRPHY_MR6 0x000004E8
+#define DDRPHY_MR11 0x00000000
+#define DDRPHY_MR12 0x00000000
+#define DDRPHY_MR13 0x00000000
+#define DDRPHY_MR14 0x00000000
+#define DDRPHY_MR22 0x00000000
+#define DDRPHY_VTCR0 0xF3C32028
+#define DDRPHY_DX8SL0PLLCR0 0x021c4000
+#define DDRPHY_DX8SL1PLLCR0 0x021c4000
+#define DDRPHY_DX8SL2PLLCR0 0x021c4000
+#define DDRPHY_DTCR0 0x8000B1C7
+#define DDRPHY_DTCR1 0x00010236
+#define DDRPHY_ACIOCR5 0x04800000
+#define DDRPHY_IOVCR0 0x0F0C0C0C
+#define DDRPHY_DX0GCR0 0x00000000
+#define DDRPHY_DX0GCR1 0x00000000
+#define DDRPHY_DX0GCR2 0x00000000
+#define DDRPHY_DX0GCR3 0x00000000
+#define DDRPHY_DX1GCR0 0x00000000
+#define DDRPHY_DX1GCR1 0x00000000
+#define DDRPHY_DX1GCR2 0x00000000
+#define DDRPHY_DX1GCR3 0x00000000
+#define DDRPHY_DX2GCR0 0x40700204
+#define DDRPHY_DX2GCR1 0x00007FFF
+#define DDRPHY_DX2GCR2 0x00000000
+#define DDRPHY_DX2GCR3 0xFFC0010B
+#define DDRPHY_DX3GCR0 0x40700204
+#define DDRPHY_DX3GCR1 0x00007FFF
+#define DDRPHY_DX3GCR2 0x00000000
+#define DDRPHY_DX3GCR3 0xFFC0010B
+#define DDRPHY_DX4GCR0 0x40703220
+#define DDRPHY_DX4GCR1 0x55556000
+#define DDRPHY_DX4GCR2 0xAAAA0000
+#define DDRPHY_DX4GCR3 0xFFE18587
+#define DDRPHY_DX0GCR4 0x0E00B03C
+#define DDRPHY_DX1GCR4 0x0E00B03C
+#define DDRPHY_DX2GCR4 0x0E00B03C
+#define DDRPHY_DX3GCR4 0x0E00B03C
+#define DDRPHY_DX4GCR4 0x0E00B03C
+#define DDRPHY_PGCR5 0x01010004
+#define DDRPHY_DX0GCR5 0x00000049
+#define DDRPHY_DX1GCR5 0x00000049
+#define DDRPHY_DX2GCR5 0x00000049
+#define DDRPHY_DX3GCR5 0x00000049
+#define DDRPHY_DX4GCR5 0x00000049
+#define DDRPHY_DX0GTR0 0x00020002
+#define DDRPHY_DX1GTR0 0x00020002
+#define DDRPHY_DX2GTR0 0x00020002
+#define DDRPHY_DX3GTR0 0x00020002
+#define DDRPHY_DX4GTR0 0x00020002
+#define DDRPHY_ODTCR 0x00010000
+#define DDRPHY_DX8SL0IOCR 0x04800000
+#define DDRPHY_DX8SL1IOCR 0x04800000
+#define DDRPHY_DX8SL2IOCR 0x04800000
+#define DDRPHY_DX8SL0DXCTL2 0x00141830
+#define DDRPHY_DX8SL1DXCTL2 0x00141830
+#define DDRPHY_DX8SL2DXCTL2 0x00141830
diff --git a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
index d4ecb3be10..143eb6d630 100644
--- a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
@@ -17,56 +17,10 @@
&cbass_main{
u-boot,dm-spl;
- secure_proxy: secure_proxy@32c00000 {
- compatible = "ti,am654-secure-proxy";
- #mbox-cells = <1>;
- reg-names = "target_data", "rt", "scfg";
- reg = <0x32c00000 0x100000>,
- <0x32400000 0x100000>,
- <0x32800000 0x100000>;
- interrupt-names = "rx_011";
- interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- dmsc: dmsc {
- compatible = "ti,k2g-sci";
- ti,host-id = <12>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- /*
- * In case of rare platforms that does not use am6 as
- * system master, use /delete-property/
- */
- ti,system-reboot-controller;
- mbox-names = "rx", "tx";
-
- mboxes= <&secure_proxy 11>,
- <&secure_proxy 13>;
-
- k3_pds: power-controller {
- compatible = "ti,sci-pm-domain";
- #power-domain-cells = <1>;
- };
-
- k3_clks: clocks {
- compatible = "ti,k2g-sci-clk";
- #clock-cells = <2>;
- };
-
- k3_reset: reset-controller {
- compatible = "ti,sci-reset";
- #reset-cells = <2>;
- };
-
- k3_sysreset: sysreset-controller {
- compatible = "ti,sci-sysreset";
- };
- };
main_pmx0: pinmux@11c000 {
compatible = "pinctrl-single";
- reg = <0x11c000 0x2e4>;
+ reg = <0x0 0x11c000 0x0 0x2e4>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;
@@ -74,28 +28,16 @@
main_pmx1: pinmux@11c2e8 {
compatible = "pinctrl-single";
- reg = <0x11c2e8 0x24>;
+ reg = <0x0 0x11c2e8 0x0 0x24>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;
};
- main_uart0: serial@2800000 {
- compatible = "ti,am654-uart", "ti,omap4-uart", "ns16550a";
- reg = <0x02800000 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
- interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <48000000>;
- current-speed = <115200>;
- status = "disabled";
- u-boot,dm-pre-reloc;
- };
-
sdhci0: sdhci@04F80000 {
compatible = "arasan,sdhci-5.1";
- reg = <0x4F80000 0x1000>,
- <0x4F90000 0x400>;
+ reg = <0x0 0x4F80000 0x0 0x1000>,
+ <0x0 0x4F90000 0x0 0x400>;
clocks = <&k3_clks 47 1>;
power-domains = <&k3_pds 47>;
max-frequency = <25000000>;
@@ -103,8 +45,8 @@
sdhci1: sdhci@04FA0000 {
compatible = "arasan,sdhci-5.1";
- reg = <0x4FA0000 0x1000>,
- <0x4FB0000 0x400>;
+ reg = <0x0 0x4FA0000 0x0 0x1000>,
+ <0x0 0x4FB0000 0x0 0x400>;
clocks = <&k3_clks 48 1>;
power-domains = <&k3_pds 48>;
max-frequency = <25000000>;
@@ -112,12 +54,31 @@
};
-&secure_proxy {
+&cbass_mcu {
+ u-boot,dm-spl;
+ wkup_pmx0: pinmux@4301c000 {
+ compatible = "pinctrl-single";
+ reg = <0x0 0x4301c000 0x0 0x118>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0xffffffff>;
+ };
+};
+
+&cbass_wakeup {
+ u-boot,dm-spl;
+};
+
+&secure_proxy_main {
u-boot,dm-spl;
};
&dmsc {
u-boot,dm-spl;
+ k3_sysreset: sysreset-controller {
+ compatible = "ti,sci-sysreset";
+ u-boot,dm-spl;
+ };
};
&k3_pds {
@@ -141,6 +102,7 @@
AM65X_IOPAD(0x01ec, PIN_INPUT | MUX_MODE0) /* (AG11) UART0_CTSn */
AM65X_IOPAD(0x01f0, PIN_OUTPUT | MUX_MODE0) /* (AD11) UART0_RTSn */
>;
+ u-boot,dm-spl;
};
main_mmc0_pins_default: main_mmc0_pins_default {
@@ -157,6 +119,7 @@
AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP | MUX_MODE0) /* (D25) MMC0_DAT7 */
AM65X_IOPAD(0x01b0, PIN_INPUT | MUX_MODE0) /* (C25) MMC0_DS */
>;
+ u-boot,dm-spl;
};
main_mmc1_pins_default: main_mmc1_pins_default {
@@ -170,6 +133,7 @@
AM65X_IOPAD(0x02dc, PIN_INPUT_PULLUP | MUX_MODE0) /* (B24) MMC1_SDCD */
AM65X_IOPAD(0x02e0, PIN_INPUT | MUX_MODE0) /* (C24) MMC1_SDWP */
>;
+ u-boot,dm-spl;
};
};
diff --git a/arch/arm/dts/k3-am654-ddr.dtsi b/arch/arm/dts/k3-am654-ddr.dtsi
new file mode 100644
index 0000000000..964eb173eb
--- /dev/null
+++ b/arch/arm/dts/k3-am654-ddr.dtsi
@@ -0,0 +1,196 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+/ {
+ memorycontroller: memorycontroller@0298e000 {
+ compatible = "ti,am654-ddrss";
+ reg = <0x0 0x0298e000 0x0 0x200>,
+ <0x0 0x02980000 0x0 0x4000>,
+ <0x0 0x02988000 0x0 0x2000>;
+ reg-names = "ss", "ctl", "phy";
+ clocks = <&k3_clks 20 0>;
+ power-domains = <&k3_pds 20>,
+ <&k3_pds 244>;
+ assigned-clocks = <&k3_clks 20 1>;
+ assigned-clock-rates = <DDR_PLL_FREQUENCY>;
+ u-boot,dm-spl;
+
+ ti,ctl-reg = <
+ DDRCTL_DFIMISC
+ DDRCTL_DFITMG0
+ DDRCTL_DFITMG1
+ DDRCTL_DFITMG2
+ DDRCTL_INIT0
+ DDRCTL_INIT1
+ DDRCTL_INIT3
+ DDRCTL_INIT4
+ DDRCTL_INIT5
+ DDRCTL_INIT6
+ DDRCTL_INIT7
+ DDRCTL_MSTR
+ DDRCTL_ODTCFG
+ DDRCTL_ODTMAP
+ DDRCTL_RANKCTL
+ DDRCTL_RFSHCTL0
+ DDRCTL_RFSHTMG
+ DDRCTL_ZQCTL0
+ DDRCTL_ZQCTL1
+ >;
+
+ ti,ctl-crc = <
+ DDRCTL_CRCPARCTL0
+ DDRCTL_CRCPARCTL1
+ DDRCTL_CRCPARCTL2
+ >;
+
+ ti,ctl-ecc = <
+ DDRCTL_ECCCFG0
+ >;
+
+ ti,ctl-map = <
+ DDRCTL_ADDRMAP0
+ DDRCTL_ADDRMAP1
+ DDRCTL_ADDRMAP2
+ DDRCTL_ADDRMAP3
+ DDRCTL_ADDRMAP4
+ DDRCTL_ADDRMAP5
+ DDRCTL_ADDRMAP6
+ DDRCTL_ADDRMAP7
+ DDRCTL_ADDRMAP8
+ DDRCTL_ADDRMAP9
+ DDRCTL_ADDRMAP10
+ DDRCTL_ADDRMAP11
+ DDRCTL_DQMAP0
+ DDRCTL_DQMAP1
+ DDRCTL_DQMAP4
+ DDRCTL_DQMAP5
+ >;
+
+ ti,ctl-pwr = <
+ DDRCTL_PWRCTL
+ >;
+
+ ti,ctl-timing = <
+ DDRCTL_DRAMTMG0
+ DDRCTL_DRAMTMG1
+ DDRCTL_DRAMTMG2
+ DDRCTL_DRAMTMG3
+ DDRCTL_DRAMTMG4
+ DDRCTL_DRAMTMG5
+ DDRCTL_DRAMTMG6
+ DDRCTL_DRAMTMG7
+ DDRCTL_DRAMTMG8
+ DDRCTL_DRAMTMG9
+ DDRCTL_DRAMTMG11
+ DDRCTL_DRAMTMG12
+ DDRCTL_DRAMTMG13
+ DDRCTL_DRAMTMG14
+ DDRCTL_DRAMTMG15
+ DDRCTL_DRAMTMG17
+ >;
+
+ ti,phy-cfg = <
+ DDRPHY_DCR
+ DDRPHY_DSGCR
+ DDRPHY_DX0GCR0
+ DDRPHY_DX0GCR1
+ DDRPHY_DX0GCR2
+ DDRPHY_DX0GCR3
+ DDRPHY_DX0GCR4
+ DDRPHY_DX0GCR5
+ DDRPHY_DX0GTR0
+ DDRPHY_DX1GCR0
+ DDRPHY_DX1GCR1
+ DDRPHY_DX1GCR2
+ DDRPHY_DX1GCR3
+ DDRPHY_DX1GCR4
+ DDRPHY_DX1GCR5
+ DDRPHY_DX1GTR0
+ DDRPHY_DX2GCR0
+ DDRPHY_DX2GCR1
+ DDRPHY_DX2GCR2
+ DDRPHY_DX2GCR3
+ DDRPHY_DX2GCR4
+ DDRPHY_DX2GCR5
+ DDRPHY_DX2GTR0
+ DDRPHY_DX3GCR0
+ DDRPHY_DX3GCR1
+ DDRPHY_DX3GCR2
+ DDRPHY_DX3GCR3
+ DDRPHY_DX3GCR4
+ DDRPHY_DX3GCR5
+ DDRPHY_DX3GTR0
+ DDRPHY_DX4GCR0
+ DDRPHY_DX4GCR1
+ DDRPHY_DX4GCR2
+ DDRPHY_DX4GCR3
+ DDRPHY_DX4GCR4
+ DDRPHY_DX4GCR5
+ DDRPHY_DX4GTR0
+ DDRPHY_DX8SL0DXCTL2
+ DDRPHY_DX8SL0IOCR
+ DDRPHY_DX8SL0PLLCR0
+ DDRPHY_DX8SL1DXCTL2
+ DDRPHY_DX8SL1IOCR
+ DDRPHY_DX8SL1PLLCR0
+ DDRPHY_DX8SL2DXCTL2
+ DDRPHY_DX8SL2IOCR
+ DDRPHY_DX8SL2PLLCR0
+ DDRPHY_DXCCR
+ DDRPHY_ODTCR
+ DDRPHY_PGCR0
+ DDRPHY_PGCR1
+ DDRPHY_PGCR2
+ DDRPHY_PGCR3
+ DDRPHY_PGCR5
+ DDRPHY_PGCR6
+ >;
+
+ ti,phy-ctl = <
+ DDRPHY_DTCR0
+ DDRPHY_DTCR1
+ DDRPHY_MR0
+ DDRPHY_MR1
+ DDRPHY_MR2
+ DDRPHY_MR3
+ DDRPHY_MR4
+ DDRPHY_MR5
+ DDRPHY_MR6
+ DDRPHY_MR11
+ DDRPHY_MR12
+ DDRPHY_MR13
+ DDRPHY_MR14
+ DDRPHY_MR22
+ DDRPHY_PLLCR0
+ DDRPHY_VTCR0
+ >;
+
+ ti,phy-ioctl = <
+ DDRPHY_ACIOCR5
+ DDRPHY_IOVCR0
+ >;
+
+ ti,phy-timing = <
+ DDRPHY_DTPR0
+ DDRPHY_DTPR1
+ DDRPHY_DTPR2
+ DDRPHY_DTPR3
+ DDRPHY_DTPR4
+ DDRPHY_DTPR5
+ DDRPHY_DTPR6
+ DDRPHY_PTR2
+ DDRPHY_PTR3
+ DDRPHY_PTR4
+ DDRPHY_PTR5
+ DDRPHY_PTR6
+ >;
+
+ ti,phy-zq = <
+ DDRPHY_ZQ0PR0
+ DDRPHY_ZQ1PR0
+ DDRPHY_ZQCR
+ >;
+ };
+};
diff --git a/arch/arm/dts/k3-am654-r5-base-board.dts b/arch/arm/dts/k3-am654-r5-base-board.dts
new file mode 100644
index 0000000000..081a2eceb2
--- /dev/null
+++ b/arch/arm/dts/k3-am654-r5-base-board.dts
@@ -0,0 +1,139 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+/dts-v1/;
+
+#include "k3-am654.dtsi"
+#include "k3-am654-base-board-u-boot.dtsi"
+#include "k3-am654-base-board-ddr4-1600MHz.dtsi"
+#include "k3-am654-ddr.dtsi"
+
+/ {
+ compatible = "ti,am654-evm", "ti,am654";
+ model = "Texas Instruments AM654 R5 Base Board";
+
+ aliases {
+ serial0 = &wkup_uart0;
+ serial2 = &main_uart0;
+ };
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ tick-timer = &timer1;
+ };
+
+ aliases {
+ remoteproc0 = &sysctrler;
+ remoteproc1 = &a53_0;
+ };
+
+ a53_0: a53@0 {
+ compatible = "ti,am654-rproc";
+ reg = <0x0 0x00a90000 0x0 0x10>;
+ power-domains = <&k3_pds 61>,
+ <&k3_pds 202>;
+ resets = <&k3_reset 202 0>;
+ assigned-clocks = <&k3_clks 202 0>;
+ assigned-clock-rates = <800000000>;
+ ti,sci = <&dmsc>;
+ ti,sci-proc-id = <32>;
+ ti,sci-host-id = <10>;
+ u-boot,dm-spl;
+ };
+
+ vtt_supply: vtt_supply {
+ compatible = "regulator-gpio";
+ regulator-name = "vtt";
+ regulator-min-microvolt = <0>;
+ regulator-max-microvolt = <3300000>;
+ gpios = <&wkup_gpio0 28 GPIO_ACTIVE_HIGH>;
+ states = <0 0x0 3300000 0x1>;
+ u-boot,dm-spl;
+ };
+};
+
+&cbass_main {
+ timer1: timer@40400000 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x0 0x40400000 0x0 0x80>;
+ ti,timer-alwon;
+ clock-frequency = <25000000>;
+ u-boot,dm-pre-reloc;
+ };
+};
+
+&cbass_mcu {
+ mcu_secproxy: secproxy@28380000 {
+ compatible = "ti,am654-secure-proxy";
+ reg = <0x0 0x2a380000 0x0 0x80000>,
+ <0x0 0x2a400000 0x0 0x80000>,
+ <0x0 0x2a480000 0x0 0x80000>;
+ reg-names = "rt", "scfg", "target_data";
+ #mbox-cells = <1>;
+ u-boot,dm-spl;
+ };
+};
+
+&cbass_wakeup {
+ sysctrler: sysctrler {
+ compatible = "ti,am654-system-controller";
+ mboxes= <&mcu_secproxy 4>, <&mcu_secproxy 5>;
+ mbox-names = "tx", "rx";
+ u-boot,dm-spl;
+ };
+
+ wkup_gpio0: wkup_gpio0@42110000 {
+ compatible = "ti,k2g-gpio", "ti,keystone-gpio";
+ reg = <0x42110000 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ti,ngpio = <56>;
+ ti,davinci-gpio-unbanked = <0>;
+ clocks = <&k3_clks 59 0>;
+ clock-names = "gpio";
+ u-boot,dm-spl;
+ };
+
+};
+
+&dmsc {
+ mboxes= <&mcu_secproxy 7>, <&mcu_secproxy 6>, <&mcu_secproxy 5>;
+ mbox-names = "tx", "rx", "notify";
+ ti,host-id = <4>;
+ ti,secure-host;
+};
+
+&wkup_uart0 {
+ u-boot,dm-spl;
+ pinctrl-names = "default";
+ pinctrl-0 = <&wkup_uart0_pins_default>;
+ status = "okay";
+};
+
+&wkup_pmx0 {
+ u-boot,dm-spl;
+ wkup_uart0_pins_default: wkup_uart0_pins_default {
+ pinctrl-single,pins = <
+ AM65X_WKUP_IOPAD(0x00a0, PIN_INPUT | MUX_MODE0) /* (AB1) WKUP_UART0_RXD */
+ AM65X_WKUP_IOPAD(0x00a4, PIN_OUTPUT | MUX_MODE0) /* (AB5) WKUP_UART0_TXD */
+ AM65X_WKUP_IOPAD(0x00c8, PIN_INPUT | MUX_MODE1) /* (AC2) WKUP_GPIO0_6.WKUP_UART0_CTSn */
+ AM65X_WKUP_IOPAD(0x00cc, PIN_OUTPUT | MUX_MODE1) /* (AC1) WKUP_GPIO0_7.WKUP_UART0_RTSn */
+ >;
+ u-boot,dm-spl;
+ };
+
+ wkup_vtt_pins_default: wkup_vtt_pins_default {
+ pinctrl-single,pins = <
+ AM65X_WKUP_IOPAD(0x0040, PIN_OUTPUT_PULLUP | MUX_MODE7) /* WKUP_GPIO0_28 */
+ >;
+ u-boot,dm-spl;
+ };
+};
+
+&memorycontroller {
+ vtt-supply = <&vtt_supply>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&wkup_vtt_pins_default>;
+};
generated by cgit (git 2.34.1) at 2025-01-13 22:18:55 +0000