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-rw-r--r--arch/arm/dts/Makefile8
-rw-r--r--arch/arm/dts/socfpga.dtsi2
-rw-r--r--arch/arm/dts/socfpga_arria10.dtsi594
-rw-r--r--arch/arm/dts/socfpga_arria10_socdk.dtsi167
-rw-r--r--arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts44
-rw-r--r--arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi734
-rw-r--r--arch/arm/dts/socfpga_stratix10.dtsi22
-rw-r--r--arch/arm/dts/socfpga_stratix10_socdk.dts3
8 files changed, 810 insertions, 764 deletions
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index b3a240590f..a0349a8975 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -183,20 +183,20 @@ dtb-$(CONFIG_TI816X) += dm8168-evm.dtb
dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb
dtb-$(CONFIG_ARCH_SOCFPGA) += \
- socfpga_arria10_socdk_sdmmc.dtb \
socfpga_arria5_socdk.dtb \
+ socfpga_arria10_socdk_sdmmc.dtb \
socfpga_cyclone5_is1.dtb \
socfpga_cyclone5_mcvevk.dtb \
socfpga_cyclone5_socdk.dtb \
socfpga_cyclone5_dbm_soc1.dtb \
- socfpga_cyclone5_de0_nano_soc.dtb \
+ socfpga_cyclone5_de0_nano_soc.dtb \
socfpga_cyclone5_de1_soc.dtb \
socfpga_cyclone5_de10_nano.dtb \
socfpga_cyclone5_sockit.dtb \
socfpga_cyclone5_socrates.dtb \
socfpga_cyclone5_sr1500.dtb \
- socfpga_stratix10_socdk.dtb \
- socfpga_cyclone5_vining_fpga.dtb
+ socfpga_cyclone5_vining_fpga.dtb \
+ socfpga_stratix10_socdk.dtb
dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb \
dra72-evm-revc.dtb dra71-evm.dtb dra76-evm.dtb
diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi
index e64127fcb2..314449478d 100644
--- a/arch/arm/dts/socfpga.dtsi
+++ b/arch/arm/dts/socfpga.dtsi
@@ -737,6 +737,7 @@
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&l4_sp_clk>;
+ clock-frequency = <100000000>;
};
uart1: serial1@ffc03000 {
@@ -746,6 +747,7 @@
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&l4_sp_clk>;
+ clock-frequency = <100000000>;
};
rst: rstmgr@ffd05000 {
diff --git a/arch/arm/dts/socfpga_arria10.dtsi b/arch/arm/dts/socfpga_arria10.dtsi
index abfd0bc4f8..b51febda9c 100644
--- a/arch/arm/dts/socfpga_arria10.dtsi
+++ b/arch/arm/dts/socfpga_arria10.dtsi
@@ -1,5 +1,5 @@
/*
- * Copyright Altera Corporation (C) 2014-2017. All rights reserved.
+ * Copyright Altera Corporation (C) 2014. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms and conditions of the GNU General Public License,
@@ -14,7 +14,6 @@
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
-#include "skeleton.dtsi"
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/altr,rst-mgr-a10.h>
@@ -22,29 +21,10 @@
#address-cells = <1>;
#size-cells = <1>;
- aliases {
- ethernet0 = &gmac0;
- ethernet1 = &gmac1;
- ethernet2 = &gmac2;
- serial0 = &uart0;
- serial1 = &uart1;
- timer0 = &timer0;
- timer1 = &timer1;
- timer2 = &timer2;
- timer3 = &timer3;
- spi0 = &spi0;
- spi1 = &spi1;
- };
-
- memory {
- name = "memory";
- device_type = "memory";
- reg = <0x0 0x40000000>; /* 1GB */
- };
-
cpus {
#address-cells = <1>;
#size-cells = <0>;
+ enable-method = "altr,socfpga-a10-smp";
cpu@0 {
compatible = "arm,cortex-a9";
@@ -102,321 +82,335 @@
};
};
- clkmgr@ffd04000 {
- compatible = "altr,clk-mgr";
- reg = <0xffd04000 0x1000>;
- reg-names = "soc_clock_manager_OCP_SLV";
-
- clocks {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- };
-
- cb_intosc_ls_clk: cb_intosc_ls_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- };
+ base_fpga_region {
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
- f2s_free_clk: f2s_free_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- };
+ compatible = "fpga-region";
+ fpga-mgr = <&fpga_mgr>;
+ };
- osc1: osc1 {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- };
+ clkmgr@ffd04000 {
+ compatible = "altr,clk-mgr";
+ reg = <0xffd04000 0x1000>;
- main_pll: main_pll {
+ clocks {
#address-cells = <1>;
#size-cells = <0>;
- #clock-cells = <0>;
- compatible = "altr,socfpga-a10-pll-clock";
- clocks = <&osc1>, <&cb_intosc_ls_clk>,
- <&f2s_free_clk>;
- reg = <0x40>;
- main_mpu_base_clk: main_mpu_base_clk {
+ cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk {
#clock-cells = <0>;
- compatible = "altr,socfpga-a10-perip-clk";
- clocks = <&main_pll>;
- div-reg = <0x140 0 11>;
+ compatible = "fixed-clock";
};
- main_noc_base_clk: main_noc_base_clk {
+ cb_intosc_ls_clk: cb_intosc_ls_clk {
#clock-cells = <0>;
- compatible = "altr,socfpga-a10-perip-clk";
- clocks = <&main_pll>;
- div-reg = <0x144 0 11>;
+ compatible = "fixed-clock";
};
- main_emaca_clk: main_emaca_clk {
+ f2s_free_clk: f2s_free_clk {
#clock-cells = <0>;
- compatible = "altr,socfpga-a10-perip-clk";
- clocks = <&main_pll>;
- reg = <0x68>;
+ compatible = "fixed-clock";
};
- main_emacb_clk: main_emacb_clk {
+ osc1: osc1 {
#clock-cells = <0>;
- compatible = "altr,socfpga-a10-perip-clk";
- clocks = <&main_pll>;
- reg = <0x6C>;
+ compatible = "fixed-clock";
};
- main_emac_ptp_clk: main_emac_ptp_clk {
+ main_pll: main_pll@40 {
+ #address-cells = <1>;
+ #size-cells = <0>;
#clock-cells = <0>;
- compatible = "altr,socfpga-a10-perip-clk";
- clocks = <&main_pll>;
- reg = <0x70>;
+ compatible = "altr,socfpga-a10-pll-clock";
+ clocks = <&osc1>, <&cb_intosc_ls_clk>,
+ <&f2s_free_clk>;
+ reg = <0x40>;
+
+ main_mpu_base_clk: main_mpu_base_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&main_pll>;
+ div-reg = <0x140 0 11>;
+ };
+
+ main_noc_base_clk: main_noc_base_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&main_pll>;
+ div-reg = <0x144 0 11>;
+ };
+
+ main_emaca_clk: main_emaca_clk@68 {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&main_pll>;
+ reg = <0x68>;
+ };
+
+ main_emacb_clk: main_emacb_clk@6c {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&main_pll>;
+ reg = <0x6C>;
+ };
+
+ main_emac_ptp_clk: main_emac_ptp_clk@70 {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&main_pll>;
+ reg = <0x70>;
+ };
+
+ main_gpio_db_clk: main_gpio_db_clk@74 {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&main_pll>;
+ reg = <0x74>;
+ };
+
+ main_sdmmc_clk: main_sdmmc_clk@78 {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk"
+;
+ clocks = <&main_pll>;
+ reg = <0x78>;
+ };
+
+ main_s2f_usr0_clk: main_s2f_usr0_clk@7c {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&main_pll>;
+ reg = <0x7C>;
+ };
+
+ main_s2f_usr1_clk: main_s2f_usr1_clk@80 {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&main_pll>;
+ reg = <0x80>;
+ };
+
+ main_hmc_pll_ref_clk: main_hmc_pll_ref_clk@84 {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&main_pll>;
+ reg = <0x84>;
+ };
+
+ main_periph_ref_clk: main_periph_ref_clk@9c {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&main_pll>;
+ reg = <0x9C>;
+ };
};
- main_gpio_db_clk: main_gpio_db_clk {
+ periph_pll: periph_pll@c0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
#clock-cells = <0>;
- compatible = "altr,socfpga-a10-perip-clk";
- clocks = <&main_pll>;
- reg = <0x74>;
+ compatible = "altr,socfpga-a10-pll-clock";
+ clocks = <&osc1>, <&cb_intosc_ls_clk>,
+ <&f2s_free_clk>, <&main_periph_ref_clk>;
+ reg = <0xC0>;
+
+ peri_mpu_base_clk: peri_mpu_base_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&periph_pll>;
+ div-reg = <0x140 16 11>;
+ };
+
+ peri_noc_base_clk: peri_noc_base_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&periph_pll>;
+ div-reg = <0x144 16 11>;
+ };
+
+ peri_emaca_clk: peri_emaca_clk@e8 {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&periph_pll>;
+ reg = <0xE8>;
+ };
+
+ peri_emacb_clk: peri_emacb_clk@ec {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&periph_pll>;
+ reg = <0xEC>;
+ };
+
+ peri_emac_ptp_clk: peri_emac_ptp_clk@f0 {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&periph_pll>;
+ reg = <0xF0>;
+ };
+
+ peri_gpio_db_clk: peri_gpio_db_clk@f4 {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&periph_pll>;
+ reg = <0xF4>;
+ };
+
+ peri_sdmmc_clk: peri_sdmmc_clk@f8 {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&periph_pll>;
+ reg = <0xF8>;
+ };
+
+ peri_s2f_usr0_clk: peri_s2f_usr0_clk@fc {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&periph_pll>;
+ reg = <0xFC>;
+ };
+
+ peri_s2f_usr1_clk: peri_s2f_usr1_clk@100 {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&periph_pll>;
+ reg = <0x100>;
+ };
+
+ peri_hmc_pll_ref_clk: peri_hmc_pll_ref_clk@104 {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&periph_pll>;
+ reg = <0x104>;
+ };
};
- main_sdmmc_clk: main_sdmmc_clk {
+ mpu_free_clk: mpu_free_clk@60 {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
- clocks = <&main_pll>;
- reg = <0x78>;
+ clocks = <&main_mpu_base_clk>, <&peri_mpu_base_clk>,
+ <&osc1>, <&cb_intosc_hs_div2_clk>,
+ <&f2s_free_clk>;
+ reg = <0x60>;
};
- main_s2f_usr0_clk: main_s2f_usr0_clk {
+ noc_free_clk: noc_free_clk@64 {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
- clocks = <&main_pll>;
- reg = <0x7C>;
+ clocks = <&main_noc_base_clk>, <&peri_noc_base_clk>,
+ <&osc1>, <&cb_intosc_hs_div2_clk>,
+ <&f2s_free_clk>;
+ reg = <0x64>;
};
- main_s2f_usr1_clk: main_s2f_usr1_clk {
+ s2f_user1_free_clk: s2f_user1_free_clk@104 {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
- clocks = <&main_pll>;
- reg = <0x80>;
+ clocks = <&main_s2f_usr1_clk>, <&peri_s2f_usr1_clk>,
+ <&osc1>, <&cb_intosc_hs_div2_clk>,
+ <&f2s_free_clk>;
+ reg = <0x104>;
};
- main_hmc_pll_ref_clk: main_hmc_pll_ref_clk {
+ sdmmc_free_clk: sdmmc_free_clk@f8 {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
- clocks = <&main_pll>;
- reg = <0x84>;
+ clocks = <&main_sdmmc_clk>, <&peri_sdmmc_clk>,
+ <&osc1>, <&cb_intosc_hs_div2_clk>,
+ <&f2s_free_clk>;
+ fixed-divider = <4>;
+ reg = <0xF8>;
};
- main_periph_ref_clk: main_periph_ref_clk {
+ l4_sys_free_clk: l4_sys_free_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
- clocks = <&main_pll>;
- reg = <0x9C>;
+ clocks = <&noc_free_clk>;
+ fixed-divider = <4>;
};
- };
-
- periph_pll: periph_pll {
- #address-cells = <1>;
- #size-cells = <0>;
- #clock-cells = <0>;
- compatible = "altr,socfpga-a10-pll-clock";
- clocks = <&osc1>, <&cb_intosc_ls_clk>,
- <&f2s_free_clk>, <&main_periph_ref_clk>;
- reg = <0xC0>;
- peri_mpu_base_clk: peri_mpu_base_clk {
+ l4_main_clk: l4_main_clk {
#clock-cells = <0>;
- compatible = "altr,socfpga-a10-perip-clk";
- clocks = <&periph_pll>;
- div-reg = <0x140 16 11>;
+ compatible = "altr,socfpga-a10-gate-clk";
+ clocks = <&noc_free_clk>;
+ div-reg = <0xA8 0 2>;
+ clk-gate = <0x48 1>;
};
- peri_noc_base_clk: peri_noc_base_clk {
+ l4_mp_clk: l4_mp_clk {
#clock-cells = <0>;
- compatible = "altr,socfpga-a10-perip-clk";
- clocks = <&periph_pll>;
- div-reg = <0x144 16 11>;
+ compatible = "altr,socfpga-a10-gate-clk";
+ clocks = <&noc_free_clk>;
+ div-reg = <0xA8 8 2>;
+ clk-gate = <0x48 2>;
};
- peri_emaca_clk: peri_emaca_clk {
+ l4_sp_clk: l4_sp_clk {
#clock-cells = <0>;
- compatible = "altr,socfpga-a10-perip-clk";
- clocks = <&periph_pll>;
- reg = <0xE8>;
+ compatible = "altr,socfpga-a10-gate-clk";
+ clocks = <&noc_free_clk>;
+ div-reg = <0xA8 16 2>;
+ clk-gate = <0x48 3>;
};
- peri_emacb_clk: peri_emacb_clk {
+ mpu_periph_clk: mpu_periph_clk {
#clock-cells = <0>;
- compatible = "altr,socfpga-a10-perip-clk";
- clocks = <&periph_pll>;
- reg = <0xEC>;
+ compatible = "altr,socfpga-a10-gate-clk";
+ clocks = <&mpu_free_clk>;
+ fixed-divider = <4>;
+ clk-gate = <0x48 0>;
};
- peri_emac_ptp_clk: peri_emac_ptp_clk {
+ sdmmc_clk: sdmmc_clk {
#clock-cells = <0>;
- compatible = "altr,socfpga-a10-perip-clk";
- clocks = <&periph_pll>;
- reg = <0xF0>;
+ compatible = "altr,socfpga-a10-gate-clk";
+ clocks = <&sdmmc_free_clk>;
+ clk-gate = <0xC8 5>;
+ clk-phase = <0 135>;
};
- peri_gpio_db_clk: peri_gpio_db_clk {
+ qspi_clk: qspi_clk {
#clock-cells = <0>;
- compatible = "altr,socfpga-a10-perip-clk";
- clocks = <&periph_pll>;
- reg = <0xF4>;
+ compatible = "altr,socfpga-a10-gate-clk";
+ clocks = <&l4_main_clk>;
+ clk-gate = <0xC8 11>;
};
- peri_sdmmc_clk: peri_sdmmc_clk {
+ nand_clk: nand_clk {
#clock-cells = <0>;
- compatible = "altr,socfpga-a10-perip-clk";
- clocks = <&periph_pll>;
- reg = <0xF8>;
+ compatible = "altr,socfpga-a10-gate-clk";
+ clocks = <&l4_mp_clk>;
+ clk-gate = <0xC8 10>;
};
- peri_s2f_usr0_clk: peri_s2f_usr0_clk {
+ spi_m_clk: spi_m_clk {
#clock-cells = <0>;
- compatible = "altr,socfpga-a10-perip-clk";
- clocks = <&periph_pll>;
- reg = <0xFC>;
+ compatible = "altr,socfpga-a10-gate-clk";
+ clocks = <&l4_main_clk>;
+ clk-gate = <0xC8 9>;
};
- peri_s2f_usr1_clk: peri_s2f_usr1_clk {
+ usb_clk: usb_clk {
#clock-cells = <0>;
- compatible = "altr,socfpga-a10-perip-clk";
- clocks = <&periph_pll>;
- reg = <0x100>;
+ compatible = "altr,socfpga-a10-gate-clk";
+ clocks = <&l4_mp_clk>;
+ clk-gate = <0xC8 8>;
};
- peri_hmc_pll_ref_clk: peri_hmc_pll_ref_clk {
+ s2f_usr1_clk: s2f_usr1_clk {
#clock-cells = <0>;
- compatible = "altr,socfpga-a10-perip-clk";
- clocks = <&periph_pll>;
- reg = <0x104>;
+ compatible = "altr,socfpga-a10-gate-clk";
+ clocks = <&peri_s2f_usr1_clk>;
+ clk-gate = <0xC8 6>;
};
};
+ };
- mpu_free_clk: mpu_free_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-a10-perip-clk";
- clocks = <&main_mpu_base_clk>, <&peri_mpu_base_clk>,
- <&osc1>, <&cb_intosc_hs_div2_clk>,
- <&f2s_free_clk>;
- reg = <0x60>;
- };
-
- noc_free_clk: noc_free_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-a10-perip-clk";
- clocks = <&main_noc_base_clk>, <&peri_noc_base_clk>,
- <&osc1>, <&cb_intosc_hs_div2_clk>,
- <&f2s_free_clk>;
- reg = <0x64>;
- };
-
- s2f_user1_free_clk: s2f_user1_free_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-a10-perip-clk";
- clocks = <&main_s2f_usr1_clk>, <&peri_s2f_usr1_clk>,
- <&osc1>, <&cb_intosc_hs_div2_clk>,
- <&f2s_free_clk>;
- reg = <0x104>;
- };
-
- sdmmc_free_clk: sdmmc_free_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-a10-perip-clk";
- clocks = <&main_sdmmc_clk>, <&peri_sdmmc_clk>,
- <&osc1>, <&cb_intosc_hs_div2_clk>,
- <&f2s_free_clk>;
- fixed-divider = <4>;
- reg = <0xF8>;
- };
-
- l4_sys_free_clk: l4_sys_free_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-a10-perip-clk";
- clocks = <&noc_free_clk>;
- fixed-divider = <4>;
- };
-
- l4_main_clk: l4_main_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-a10-gate-clk";
- clocks = <&noc_free_clk>;
- div-reg = <0xA8 0 2>;
- clk-gate = <0x48 1>;
- };
-
- l4_mp_clk: l4_mp_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-a10-gate-clk";
- clocks = <&noc_free_clk>;
- div-reg = <0xA8 8 2>;
- clk-gate = <0x48 2>;
- };
-
- l4_sp_clk: l4_sp_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-a10-gate-clk";
- clocks = <&noc_free_clk>;
- div-reg = <0xA8 16 2>;
- clk-gate = <0x48 3>;
- };
-
- mpu_periph_clk: mpu_periph_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-a10-gate-clk";
- clocks = <&mpu_free_clk>;
- fixed-divider = <4>;
- clk-gate = <0x48 0>;
- };
-
- sdmmc_clk: sdmmc_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-a10-gate-clk";
- clocks = <&sdmmc_free_clk>;
- clk-gate = <0xC8 5>;
- clk-phase = <0 135>;
- };
-
- qspi_clk: qspi_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-a10-gate-clk";
- clocks = <&l4_main_clk>;
- clk-gate = <0xC8 11>;
- };
-
- nand_clk: nand_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-a10-gate-clk";
- clocks = <&l4_mp_clk>;
- clk-gate = <0xC8 10>;
- };
-
- spi_m_clk: spi_m_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-a10-gate-clk";
- clocks = <&l4_main_clk>;
- clk-gate = <0xC8 9>;
- };
-
- usb_clk: usb_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-a10-gate-clk";
- clocks = <&l4_mp_clk>;
- clk-gate = <0xC8 8>;
- };
-
- s2f_usr1_clk: s2f_usr1_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-a10-gate-clk";
- clocks = <&peri_s2f_usr1_clk>;
- clk-gate = <0xC8 6>;
- };
- };
+ socfpga_axi_setup: stmmac-axi-config {
+ snps,wr_osr_lmt = <0xf>;
+ snps,rd_osr_lmt = <0xf>;
+ snps,blen = <0 0 0 0 16 0 0>;
};
gmac0: ethernet@ff800000 {
@@ -435,6 +429,7 @@
clock-names = "stmmaceth";
resets = <&rst EMAC0_RESET>;
reset-names = "stmmaceth";
+ snps,axi-config = <&socfpga_axi_setup>;
status = "disabled";
};
@@ -454,6 +449,7 @@
clock-names = "stmmaceth";
resets = <&rst EMAC1_RESET>;
reset-names = "stmmaceth";
+ snps,axi-config = <&socfpga_axi_setup>;
status = "disabled";
};
@@ -471,6 +467,7 @@
rx-fifo-depth = <16384>;
clocks = <&l4_mp_clk>;
clock-names = "stmmaceth";
+ snps,axi-config = <&socfpga_axi_setup>;
status = "disabled";
};
@@ -483,6 +480,7 @@
porta: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
+ bank-name = "porta";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <29>;
@@ -502,6 +500,7 @@
portb: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
+ bank-name = "portb";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <29>;
@@ -521,6 +520,7 @@
portc: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
+ bank-name = "portc";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <27>;
@@ -590,37 +590,24 @@
status = "disabled";
};
- sdr: sdr@0xffcfb100 {
- compatible = "syscon";
- reg = <0xffcfb100 0x80>;
- };
-
- spi0: spi@ffda4000 {
+ spi1: spi@ffda5000 {
compatible = "snps,dw-apb-ssi";
#address-cells = <1>;
#size-cells = <0>;
- reg = <0xffda4000 0x100>;
- interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xffda5000 0x100>;
+ interrupts = <0 102 4>;
num-chipselect = <4>;
bus-num = <0>;
+ /*32bit_access;*/
tx-dma-channel = <&pdma 16>;
rx-dma-channel = <&pdma 17>;
clocks = <&spi_m_clk>;
status = "disabled";
};
- spi1: spi@ffda5000 {
- compatible = "snps,dw-apb-ssi";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0xffda5000 0x100>;
- interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>;
- num-chipselect = <4>;
- bus-num = <0>;
- tx-dma-channel = <&pdma 20>;
- rx-dma-channel = <&pdma 21>;
- clocks = <&spi_m_clk>;
- status = "disabled";
+ sdr: sdr@ffc25000 {
+ compatible = "altr,sdr-ctl", "syscon";
+ reg = <0xffcfb100 0x80>;
};
L2: l2-cache@fffff000 {
@@ -629,6 +616,9 @@
interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
cache-unified;
cache-level = <2>;
+ prefetch-data = <1>;
+ prefetch-instr = <1>;
+ arm,shared-override;
};
mmc: dwmmc0@ff808000 {
@@ -638,18 +628,30 @@
reg = <0xff808000 0x1000>;
interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
fifo-depth = <0x400>;
- bus-width = <4>;
clocks = <&l4_mp_clk>, <&sdmmc_clk>;
clock-names = "biu", "ciu";
status = "disabled";
};
+ nand: nand@ffb90000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "denali,denali-nand-dt", "altr,socfpga-denali-nand";
+ reg = <0xffb90000 0x72000>,
+ <0xffb80000 0x10000>;
+ reg-names = "nand_data", "denali_reg";
+ interrupts = <0 99 4>;
+ dma-mask = <0xffffffff>;
+ clocks = <&nand_clk>;
+ status = "disabled";
+ };
+
ocram: sram@ffe00000 {
compatible = "mmio-sram";
reg = <0xffe00000 0x40000>;
};
- eccmgr: eccmgr@ffd06000 {
+ eccmgr: eccmgr {
compatible = "altr,socfpga-a10-ecc-manager";
altr,sysmgr-syscon = <&sysmgr>;
#address-cells = <1>;
@@ -681,16 +683,6 @@
<33 IRQ_TYPE_LEVEL_HIGH>;
};
- sdmmca-ecc@ff8c2c00 {
- compatible = "altr,socfpga-sdmmc-ecc";
- reg = <0xff8c2c00 0x400>;
- altr,ecc-parent = <&mmc>;
- interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
- <47 IRQ_TYPE_LEVEL_HIGH>,
- <16 IRQ_TYPE_LEVEL_HIGH>,
- <48 IRQ_TYPE_LEVEL_HIGH>;
- };
-
emac0-rx-ecc@ff8c0800 {
compatible = "altr,socfpga-eth-mac-ecc";
reg = <0xff8c0800 0x400>;
@@ -724,19 +716,17 @@
};
};
- qspi: qspi@ff809000 {
+ qspi: spi@ff809000 {
+ compatible = "cdns,qspi-nor", "cadence,qspi";
#address-cells = <1>;
#size-cells = <0>;
- compatible = "cadence,qspi";
reg = <0xff809000 0x100>,
- <0xffa00000 0x100000>;
+ <0xffa00000 0x100000>;
interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&l4_main_clk>;
- ext-decoder = <0>; /* external decoder */
- num-chipselect = <4>;
cdns,fifo-depth = <128>;
cdns,fifo-width = <4>;
- bus-num = <2>;
+ cdns,trigger-address = <0x00000000>;
+ clocks = <&qspi_clk>;
status = "disabled";
};
@@ -818,7 +808,7 @@
status = "disabled";
};
- usbphy0: usbphy@0 {
+ usbphy0: usbphy {
#phy-cells = <0>;
compatible = "usb-nop-xceiv";
status = "okay";
diff --git a/arch/arm/dts/socfpga_arria10_socdk.dtsi b/arch/arm/dts/socfpga_arria10_socdk.dtsi
new file mode 100644
index 0000000000..d7616dd1c5
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10_socdk.dtsi
@@ -0,0 +1,167 @@
+/*
+ * Copyright (C) 2015 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+#include "socfpga_arria10_socdk_sdmmc_handoff.dtsi"
+
+/ {
+ model = "Altera SOCFPGA Arria 10";
+ compatible = "altr,socfpga-arria10", "altr,socfpga";
+
+ aliases {
+ ethernet0 = &gmac0;
+ serial0 = &uart1;
+ };
+
+ chosen {
+ bootargs = "earlyprintk";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ name = "memory";
+ device_type = "memory";
+ reg = <0x0 0x40000000>; /* 1GB */
+ };
+
+ a10leds {
+ compatible = "gpio-leds";
+
+ a10sr_led0 {
+ label = "a10sr-led0";
+ gpios = <&a10sr_gpio 0 1>;
+ };
+
+ a10sr_led1 {
+ label = "a10sr-led1";
+ gpios = <&a10sr_gpio 1 1>;
+ };
+
+ a10sr_led2 {
+ label = "a10sr-led2";
+ gpios = <&a10sr_gpio 2 1>;
+ };
+
+ a10sr_led3 {
+ label = "a10sr-led3";
+ gpios = <&a10sr_gpio 3 1>;
+ };
+ };
+
+ soc {
+ u-boot,dm-pre-reloc;
+ };
+};
+
+&gmac0 {
+ phy-mode = "rgmii";
+ phy-addr = <0xffffffff>; /* probe for phy addr */
+
+ /*
+ * These skews assume the user's FPGA design is adding 600ps of delay
+ * for TX_CLK on Arria 10.
+ *
+ * All skews are offset since hardware skew values for the ksz9031
+ * range from a negative skew to a positive skew.
+ * See the micrel-ksz90x1.txt Documentation file for details.
+ */
+ txd0-skew-ps = <0>; /* -420ps */
+ txd1-skew-ps = <0>; /* -420ps */
+ txd2-skew-ps = <0>; /* -420ps */
+ txd3-skew-ps = <0>; /* -420ps */
+ rxd0-skew-ps = <420>; /* 0ps */
+ rxd1-skew-ps = <420>; /* 0ps */
+ rxd2-skew-ps = <420>; /* 0ps */
+ rxd3-skew-ps = <420>; /* 0ps */
+ txen-skew-ps = <0>; /* -420ps */
+ txc-skew-ps = <1860>; /* 960ps */
+ rxdv-skew-ps = <420>; /* 0ps */
+ rxc-skew-ps = <1680>; /* 780ps */
+ max-frame-size = <3800>;
+ status = "okay";
+};
+
+&gpio1 {
+ status = "okay";
+};
+
+&spi1 {
+ status = "okay";
+
+ resource-manager@0 {
+ compatible = "altr,a10sr";
+ reg = <0>;
+ spi-max-frequency = <100000>;
+ /* low-level active IRQ at GPIO1_5 */
+ interrupt-parent = <&portb>;
+ interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ a10sr_gpio: gpio-controller {
+ compatible = "altr,a10sr-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ a10sr_rst: reset-controller {
+ compatible = "altr,a10sr-reset";
+ #reset-cells = <1>;
+ };
+ };
+};
+
+&i2c1 {
+ status = "okay";
+
+ /*
+ * adjust the falling times to decrease the i2c frequency to 50Khz
+ * because the LCD module does not work at the standard 100Khz
+ */
+ clock-frequency = <100000>;
+ i2c-sda-falling-time-ns = <6000>;
+ i2c-scl-falling-time-ns = <6000>;
+
+ eeprom@51 {
+ compatible = "atmel,24c32";
+ reg = <0x51>;
+ pagesize = <32>;
+ };
+
+ rtc@68 {
+ compatible = "dallas,ds1339";
+ reg = <0x68>;
+ };
+
+ ltc@5c {
+ compatible = "ltc2977";
+ reg = <0x5c>;
+ };
+};
+
+&uart1 {
+ clock-frequency = <50000000>;
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+ disable-over-current;
+};
+
+&watchdog1 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
index b573d0e658..9c6070ded9 100644
--- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
+++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
@@ -1,32 +1,22 @@
/*
- * Copyright (C) 2015-2017 Altera Corporation. All rights reserved.
+ * Copyright (C) 2014-2015 Altera Corporation <www.altera.com>
*
* This program is free software; you can redistribute it and/or modify
- * it under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
*
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
*
- * You should have received a copy of the GNU General Public License along with
- * this program. If not, see <http://www.gnu.org/licenses/>.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/dts-v1/;
-#include "socfpga_arria10_socdk_sdmmc_handoff.dtsi"
-
-/ {
- chosen {
- bootargs = "console=ttyS0,115200";
- };
-};
-
-&uart1 {
- u-boot,dm-pre-reloc;
- status = "okay";
-};
+#include "socfpga_arria10_socdk.dtsi"
&mmc {
u-boot,dm-pre-reloc;
@@ -36,3 +26,15 @@
broken-cd;
bus-width = <4>;
};
+
+&eccmgr {
+ sdmmca-ecc@ff8c2c00 {
+ compatible = "altr,socfpga-sdmmc-ecc";
+ reg = <0xff8c2c00 0x400>;
+ altr,ecc-parent = <&mmc>;
+ interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
+ <47 IRQ_TYPE_LEVEL_HIGH>,
+ <16 IRQ_TYPE_LEVEL_HIGH>,
+ <48 IRQ_TYPE_LEVEL_HIGH>;
+ };
+};
diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi b/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi
index b6939b011a..39009654d9 100644
--- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi
+++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi
@@ -14,467 +14,337 @@
#include "socfpga_arria10.dtsi"
/ {
- model = "Altera SOCFPGA Arria 10";
- compatible = "altr,socfpga-arria10", "altr,socfpga";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ model = "SOCFPGA Arria10 Dev Kit"; /* Bootloader setting: uboot.model */
chosen {
- /* Bootloader setting: uboot.rbf_filename */
- cff-file = "ghrd_10as066n2.periph.rbf";
- early-release-fpga-config;
+ cff-file = "socfpga.rbf"; /* Bootloader setting: uboot.rbf_filename */
};
- soc {
+ /* Clock sources */
+ clocks {
u-boot,dm-pre-reloc;
- clkmgr@ffd04000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /* Clock source: altera_arria10_hps_eosc1 */
+ altera_arria10_hps_eosc1: altera_arria10_hps_eosc1 {
+ u-boot,dm-pre-reloc;
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ clock-output-names = "altera_arria10_hps_eosc1-clk";
+ };
+
+ /* Clock source: altera_arria10_hps_cb_intosc_ls */
+ altera_arria10_hps_cb_intosc_ls: altera_arria10_hps_cb_intosc_ls {
+ u-boot,dm-pre-reloc;
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <60000000>;
+ clock-output-names = "altera_arria10_hps_cb_intosc_ls-clk";
+ };
+
+ /* Clock source: altera_arria10_hps_f2h_free */
+ altera_arria10_hps_f2h_free: altera_arria10_hps_f2h_free {
+ u-boot,dm-pre-reloc;
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <200000000>;
+ clock-output-names = "altera_arria10_hps_f2h_free-clk";
+ };
+ };
+
+ /*
+ * Driver: altera_arria10_soc_clock_manager_arria10_uboot_driver
+ * Version: 1.0
+ * Binding: device
+ */
+ i_clk_mgr: clock_manager@0xffd04000 {
+ u-boot,dm-pre-reloc;
+ compatible = "altr,socfpga-a10-clk-init";
+ reg = <0xffd04000 0x00000200>;
+ reg-names = "soc_clock_manager_OCP_SLV";
+
+ /* Address Block: soc_clock_manager_OCP_SLV.i_clk_mgr_mainpllgrp */
+ mainpll {
u-boot,dm-pre-reloc;
- clocks {
- u-boot,dm-pre-reloc;
- osc1 {
- u-boot,dm-pre-reloc;
- clock-frequency = <25000000>;
- clock-output-names = "altera_arria10_hps_eosc1-clk";
- };
+ vco0-psrc = <0>; /* Field: vco0.psrc */
+ vco1-denom = <1>; /* Field: vco1.denom */
+ vco1-numer = <191>; /* Field: vco1.numer */
+ mpuclk-cnt = <0>; /* Field: mpuclk.cnt */
+ mpuclk-src = <0>; /* Field: mpuclk.src */
+ nocclk-cnt = <0>; /* Field: nocclk.cnt */
+ nocclk-src = <0>; /* Field: nocclk.src */
+ cntr2clk-cnt = <900>; /* Field: cntr2clk.cnt */
+ cntr3clk-cnt = <900>; /* Field: cntr3clk.cnt */
+ cntr4clk-cnt = <900>; /* Field: cntr4clk.cnt */
+ cntr5clk-cnt = <900>; /* Field: cntr5clk.cnt */
+ cntr6clk-cnt = <900>; /* Field: cntr6clk.cnt */
+ cntr7clk-cnt = <900>; /* Field: cntr7clk.cnt */
+ cntr7clk-src = <0>; /* Field: cntr7clk.src */
+ cntr8clk-cnt = <900>; /* Field: cntr8clk.cnt */
+ cntr9clk-cnt = <900>; /* Field: cntr9clk.cnt */
+ cntr9clk-src = <0>; /* Field: cntr9clk.src */
+ cntr15clk-cnt = <900>; /* Field: cntr15clk.cnt */
+ nocdiv-l4mainclk = <0>; /* Field: nocdiv.l4mainclk */
+ nocdiv-l4mpclk = <0>; /* Field: nocdiv.l4mpclk */
+ nocdiv-l4spclk = <2>; /* Field: nocdiv.l4spclk */
+ nocdiv-csatclk = <0>; /* Field: nocdiv.csatclk */
+ nocdiv-cstraceclk = <1>; /* Field: nocdiv.cstraceclk */
+ nocdiv-cspdbgclk = <1>; /* Field: nocdiv.cspdbgclk */
+ };
- cb_intosc_ls_clk {
- u-boot,dm-pre-reloc;
- clock-frequency = <60000000>;
- clock-output-names = "altera_arria10_hps_cb_intosc_ls-clk";
- };
+ /* Address Block: soc_clock_manager_OCP_SLV.i_clk_mgr_perpllgrp */
+ perpll {
+ u-boot,dm-pre-reloc;
+ vco0-psrc = <0>; /* Field: vco0.psrc */
+ vco1-denom = <1>; /* Field: vco1.denom */
+ vco1-numer = <159>; /* Field: vco1.numer */
+ cntr2clk-cnt = <7>; /* Field: cntr2clk.cnt */
+ cntr2clk-src = <1>; /* Field: cntr2clk.src */
+ cntr3clk-cnt = <900>; /* Field: cntr3clk.cnt */
+ cntr3clk-src = <1>; /* Field: cntr3clk.src */
+ cntr4clk-cnt = <19>; /* Field: cntr4clk.cnt */
+ cntr4clk-src = <1>; /* Field: cntr4clk.src */
+ cntr5clk-cnt = <499>; /* Field: cntr5clk.cnt */
+ cntr5clk-src = <1>; /* Field: cntr5clk.src */
+ cntr6clk-cnt = <9>; /* Field: cntr6clk.cnt */
+ cntr6clk-src = <1>; /* Field: cntr6clk.src */
+ cntr7clk-cnt = <900>; /* Field: cntr7clk.cnt */
+ cntr8clk-cnt = <900>; /* Field: cntr8clk.cnt */
+ cntr8clk-src = <0>; /* Field: cntr8clk.src */
+ cntr9clk-cnt = <900>; /* Field: cntr9clk.cnt */
+ emacctl-emac0sel = <0>; /* Field: emacctl.emac0sel */
+ emacctl-emac1sel = <0>; /* Field: emacctl.emac1sel */
+ emacctl-emac2sel = <0>; /* Field: emacctl.emac2sel */
+ gpiodiv-gpiodbclk = <32000>; /* Field: gpiodiv.gpiodbclk */
+ };
- f2s_free_clk {
- u-boot,dm-pre-reloc;
- clock-frequency = <200000000>;
- clock-output-names = "altera_arria10_hps_f2h_free-clk";
- };
+ /* Address Block: soc_clock_manager_OCP_SLV.i_clk_mgr_alteragrp */
+ alteragrp {
+ u-boot,dm-pre-reloc;
+ nocclk = <0x0384000b>; /* Register: nocclk */
+ mpuclk = <0x03840001>; /* Register: mpuclk */
+ };
+ };
- main_pll {
- u-boot,dm-pre-reloc;
- /*
- * Address Block: soc_clock_manager_OCP_SLV.
- * i_clk_mgr_mainpllgrp
- */
- altr,of_reg_value = <
- 0 /* Field: vco0.psrc */
- 1 /* Field: vco1.denom */
- 191 /* Field: vco1.numer */
- 0 /* Field: mpuclk */
- 0 /* Field: mpuclk.cnt */
- 0 /* Field: mpuclk.src */
- 0 /* Field: nocclk */
- 0 /* Field: nocclk.cnt */
- 0 /* Field: nocclk.src */
- 900 /* Field: cntr2clk.cnt */
- 900 /* Field: cntr3clk.cnt */
- 900 /* Field: cntr4clk.cnt */
- 900 /* Field: cntr5clk.cnt */
- 900 /* Field: cntr6clk.cnt */
- 900 /* Field: cntr7clk.cnt */
- 0 /* Field: cntr7clk.src */
- 900 /* Field: cntr8clk.cnt */
- 900 /* Field: cntr9clk.cnt */
- 0 /* Field: cntr9clk.src */
- 900 /* Field: cntr15clk.cnt */
- 0 /* Field: nocdiv.l4mainclk */
- 0 /* Field: nocdiv.l4mpclk */
- 2 /* Field: nocdiv.l4spclk */
- 0 /* Field: nocdiv.csatclk */
- 1 /* Field: nocdiv.cstraceclk */
- 1 /* Field: nocdiv.cspdbgclk */
- >;
- };
+ /*
+ * Driver: altera_arria10_soc_3v_io48_pin_mux_arria10_uboot_driver
+ * Version: 1.0
+ * Binding: pinmux
+ */
+ i_io48_pin_mux: pinmux@0xffd07000 {
+ u-boot,dm-pre-reloc;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "pinctrl-single";
+ reg = <0xffd07000 0x00000800>;
+ reg-names = "soc_3v_io48_pin_mux_OCP_SLV";
- periph_pll {
- u-boot,dm-pre-reloc;
- /*
- * Address Block: soc_clock_manager_OCP_SLV.
- * i_clk_mgr_perpllgrp
- */
- altr,of_reg_value = <
- 0 /* Field: vco0.psrc */
- 1 /* Field: vco1.denom */
- 159 /* Field: vco1.numer */
- 7 /* Field: cntr2clk.cnt */
- 1 /* Field: cntr2clk.src */
- 900 /* Field: cntr3clk.cnt */
- 1 /* Field: cntr3clk.src */
- 19 /* Field: cntr4clk.cnt */
- 1 /* Field: cntr4clk.src */
- 499 /* Field: cntr5clk.cnt */
- 1 /* Field: cntr5clk.src */
- 9 /* Field: cntr6clk.cnt */
- 1 /* Field: cntr6clk.src */
- 900 /* Field: cntr7clk.cnt */
- 900 /* Field: cntr8clk.cnt */
- 0 /* Field: cntr8clk.src */
- 900 /* Field: cntr9clk.cnt */
- 0 /* Field: emacctl.emac0sel */
- 0 /* Field: emacctl.emac1sel */
- 0 /* Field: emacctl.emac2sel */
- 32000 /* Field: gpiodiv.gpiodbclk */
- >;
- };
+ /* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_shared_3v_io_grp */
+ shared {
+ u-boot,dm-pre-reloc;
+ reg = <0xffd07000 0x00000200>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x0000000f>;
+ pinctrl-single,pins =
+ <0x00000000 0x00000008>, /* Register: pinmux_shared_io_q1_1 */
+ <0x00000004 0x00000008>, /* Register: pinmux_shared_io_q1_2 */
+ <0x00000008 0x00000008>, /* Register: pinmux_shared_io_q1_3 */
+ <0x0000000c 0x00000008>, /* Register: pinmux_shared_io_q1_4 */
+ <0x00000010 0x00000008>, /* Register: pinmux_shared_io_q1_5 */
+ <0x00000014 0x00000008>, /* Register: pinmux_shared_io_q1_6 */
+ <0x00000018 0x00000008>, /* Register: pinmux_shared_io_q1_7 */
+ <0x0000001c 0x00000008>, /* Register: pinmux_shared_io_q1_8 */
+ <0x00000020 0x00000008>, /* Register: pinmux_shared_io_q1_9 */
+ <0x00000024 0x00000008>, /* Register: pinmux_shared_io_q1_10 */
+ <0x00000028 0x00000008>, /* Register: pinmux_shared_io_q1_11 */
+ <0x0000002c 0x00000008>, /* Register: pinmux_shared_io_q1_12 */
+ <0x00000030 0x00000004>, /* Register: pinmux_shared_io_q2_1 */
+ <0x00000034 0x00000004>, /* Register: pinmux_shared_io_q2_2 */
+ <0x00000038 0x00000004>, /* Register: pinmux_shared_io_q2_3 */
+ <0x0000003c 0x00000004>, /* Register: pinmux_shared_io_q2_4 */
+ <0x00000040 0x00000004>, /* Register: pinmux_shared_io_q2_5 */
+ <0x00000044 0x00000004>, /* Register: pinmux_shared_io_q2_6 */
+ <0x00000048 0x00000004>, /* Register: pinmux_shared_io_q2_7 */
+ <0x0000004c 0x00000004>, /* Register: pinmux_shared_io_q2_8 */
+ <0x00000050 0x00000004>, /* Register: pinmux_shared_io_q2_9 */
+ <0x00000054 0x00000004>, /* Register: pinmux_shared_io_q2_10 */
+ <0x00000058 0x00000004>, /* Register: pinmux_shared_io_q2_11 */
+ <0x0000005c 0x00000004>, /* Register: pinmux_shared_io_q2_12 */
+ <0x00000060 0x00000003>, /* Register: pinmux_shared_io_q3_1 */
+ <0x00000064 0x00000003>, /* Register: pinmux_shared_io_q3_2 */
+ <0x00000068 0x00000003>, /* Register: pinmux_shared_io_q3_3 */
+ <0x0000006c 0x00000003>, /* Register: pinmux_shared_io_q3_4 */
+ <0x00000070 0x00000003>, /* Register: pinmux_shared_io_q3_5 */
+ <0x00000074 0x0000000f>, /* Register: pinmux_shared_io_q3_6 */
+ <0x00000078 0x0000000a>, /* Register: pinmux_shared_io_q3_7 */
+ <0x0000007c 0x0000000a>, /* Register: pinmux_shared_io_q3_8 */
+ <0x00000080 0x0000000a>, /* Register: pinmux_shared_io_q3_9 */
+ <0x00000084 0x0000000a>, /* Register: pinmux_shared_io_q3_10 */
+ <0x00000088 0x00000001>, /* Register: pinmux_shared_io_q3_11 */
+ <0x0000008c 0x00000001>, /* Register: pinmux_shared_io_q3_12 */
+ <0x00000090 0x00000000>, /* Register: pinmux_shared_io_q4_1 */
+ <0x00000094 0x00000000>, /* Register: pinmux_shared_io_q4_2 */
+ <0x00000098 0x0000000f>, /* Register: pinmux_shared_io_q4_3 */
+ <0x0000009c 0x0000000c>, /* Register: pinmux_shared_io_q4_4 */
+ <0x000000a0 0x0000000f>, /* Register: pinmux_shared_io_q4_5 */
+ <0x000000a4 0x0000000f>, /* Register: pinmux_shared_io_q4_6 */
+ <0x000000a8 0x0000000a>, /* Register: pinmux_shared_io_q4_7 */
+ <0x000000ac 0x0000000a>, /* Register: pinmux_shared_io_q4_8 */
+ <0x000000b0 0x0000000c>, /* Register: pinmux_shared_io_q4_9 */
+ <0x000000b4 0x0000000c>, /* Register: pinmux_shared_io_q4_10 */
+ <0x000000b8 0x0000000c>, /* Register: pinmux_shared_io_q4_11 */
+ <0x000000bc 0x0000000c>; /* Register: pinmux_shared_io_q4_12 */
+ };
+
+ /* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_dedicated_io_grp */
+ dedicated {
+ u-boot,dm-pre-reloc;
+ reg = <0xffd07200 0x00000200>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x0000000f>;
+ pinctrl-single,pins =
+ <0x0000000c 0x00000008>, /* Register: pinmux_dedicated_io_4 */
+ <0x00000010 0x00000008>, /* Register: pinmux_dedicated_io_5 */
+ <0x00000014 0x00000008>, /* Register: pinmux_dedicated_io_6 */
+ <0x00000018 0x00000008>, /* Register: pinmux_dedicated_io_7 */
+ <0x0000001c 0x00000008>, /* Register: pinmux_dedicated_io_8 */
+ <0x00000020 0x00000008>, /* Register: pinmux_dedicated_io_9 */
+ <0x00000024 0x0000000a>, /* Register: pinmux_dedicated_io_10 */
+ <0x00000028 0x0000000a>, /* Register: pinmux_dedicated_io_11 */
+ <0x0000002c 0x00000008>, /* Register: pinmux_dedicated_io_12 */
+ <0x00000030 0x00000008>, /* Register: pinmux_dedicated_io_13 */
+ <0x00000034 0x00000008>, /* Register: pinmux_dedicated_io_14 */
+ <0x00000038 0x00000008>, /* Register: pinmux_dedicated_io_15 */
+ <0x0000003c 0x0000000d>, /* Register: pinmux_dedicated_io_16 */
+ <0x00000040 0x0000000d>; /* Register: pinmux_dedicated_io_17 */
+ };
- altera {
- u-boot,dm-pre-reloc;
- /*
- * Address Block: soc_clock_manager_OCP_SLV.
- * i_clk_mgr_alteragrp
- */
- altr,of_reg_value = <
- 0x0384000b /* Register: nocclk */
- 0x03840001 /* Register: mpuclk */
- >;
- };
- };
+ /* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_dedicated_io_grp */
+ dedicated_cfg {
+ u-boot,dm-pre-reloc;
+ reg = <0xffd07200 0x00000200>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x003f3f3f>;
+ pinctrl-single,pins =
+ <0x00000100 0x00000101>, /* Register: configuration_dedicated_io_bank */
+ <0x00000104 0x000b080a>, /* Register: configuration_dedicated_io_1 */
+ <0x00000108 0x000b080a>, /* Register: configuration_dedicated_io_2 */
+ <0x0000010c 0x000b080a>, /* Register: configuration_dedicated_io_3 */
+ <0x00000110 0x000a282a>, /* Register: configuration_dedicated_io_4 */
+ <0x00000114 0x000a282a>, /* Register: configuration_dedicated_io_5 */
+ <0x00000118 0x0008282a>, /* Register: configuration_dedicated_io_6 */
+ <0x0000011c 0x000a282a>, /* Register: configuration_dedicated_io_7 */
+ <0x00000120 0x000a282a>, /* Register: configuration_dedicated_io_8 */
+ <0x00000124 0x000a282a>, /* Register: configuration_dedicated_io_9 */
+ <0x00000128 0x00090000>, /* Register: configuration_dedicated_io_10 */
+ <0x0000012c 0x00090000>, /* Register: configuration_dedicated_io_11 */
+ <0x00000130 0x000b282a>, /* Register: configuration_dedicated_io_12 */
+ <0x00000134 0x000b282a>, /* Register: configuration_dedicated_io_13 */
+ <0x00000138 0x000b282a>, /* Register: configuration_dedicated_io_14 */
+ <0x0000013c 0x000b282a>, /* Register: configuration_dedicated_io_15 */
+ <0x00000140 0x0008282a>, /* Register: configuration_dedicated_io_16 */
+ <0x00000144 0x000a282a>; /* Register: configuration_dedicated_io_17 */
};
- /*
- * Driver: altera_arria10_soc_3v_io48_pin_mux_arria10_uboot_driver
- * Binding: pinmux
- */
- i_io48_pin_mux: pinmux@0xffd07000 {
+ /* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_fpga_interface_grp */
+ fpga {
u-boot,dm-pre-reloc;
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "pinctrl-single";
- reg = <0xffd07000 0x00000800>;
- reg-names = "soc_3v_io48_pin_mux_OCP_SLV";
+ reg = <0xffd07400 0x00000100>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x00000001>;
+ pinctrl-single,pins =
+ <0x00000000 0x00000000>, /* Register: pinmux_emac0_usefpga */
+ <0x00000004 0x00000000>, /* Register: pinmux_emac1_usefpga */
+ <0x00000008 0x00000000>, /* Register: pinmux_emac2_usefpga */
+ <0x0000000c 0x00000000>, /* Register: pinmux_i2c0_usefpga */
+ <0x00000010 0x00000000>, /* Register: pinmux_i2c1_usefpga */
+ <0x00000014 0x00000000>, /* Register: pinmux_i2c_emac0_usefpga */
+ <0x00000018 0x00000000>, /* Register: pinmux_i2c_emac1_usefpga */
+ <0x0000001c 0x00000000>, /* Register: pinmux_i2c_emac2_usefpga */
+ <0x00000020 0x00000000>, /* Register: pinmux_nand_usefpga */
+ <0x00000024 0x00000000>, /* Register: pinmux_qspi_usefpga */
+ <0x00000028 0x00000000>, /* Register: pinmux_sdmmc_usefpga */
+ <0x0000002c 0x00000000>, /* Register: pinmux_spim0_usefpga */
+ <0x00000030 0x00000000>, /* Register: pinmux_spim1_usefpga */
+ <0x00000034 0x00000000>, /* Register: pinmux_spis0_usefpga */
+ <0x00000038 0x00000000>, /* Register: pinmux_spis1_usefpga */
+ <0x0000003c 0x00000000>, /* Register: pinmux_uart0_usefpga */
+ <0x00000040 0x00000000>; /* Register: pinmux_uart1_usefpga */
+ };
+ };
+
+ /*
+ * Driver: altera_arria10_soc_noc_arria10_uboot_driver
+ * Version: 1.0
+ * Binding: device
+ */
+ i_noc: noc@0xffd10000 {
+ u-boot,dm-pre-reloc;
+ compatible = "altr,socfpga-a10-noc";
+ reg = <0xffd10000 0x00008000>;
+ reg-names = "mpu_m0";
+ firewall {
+ u-boot,dm-pre-reloc;
/*
- * Address Block: soc_3v_io48_pin_mux_OCP_SLV.
- * i_io48_pin_mux_shared_3v_io_grp
+ * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.mpuregion0addr.base
+ * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.mpuregion0addr.limit
*/
- shared {
- u-boot,dm-pre-reloc;
- reg = <0xffd07000 0x00000200>;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0x0000000f>;
- pinctrl-single,pins =
- /* Reg: pinmux_shared_io_q1_1 */
- <0x00000000 0x00000008>,
- /* Reg: pinmux_shared_io_q1_2 */
- <0x00000004 0x00000008>,
- /* Reg: pinmux_shared_io_q1_3 */
- <0x00000008 0x00000008>,
- /* Reg: pinmux_shared_io_q1_4 */
- <0x0000000c 0x00000008>,
- /* Reg: pinmux_shared_io_q1_5 */
- <0x00000010 0x00000008>,
- /* Reg: pinmux_shared_io_q1_6 */
- <0x00000014 0x00000008>,
- /* Reg: pinmux_shared_io_q1_7 */
- <0x00000018 0x00000008>,
- /* Reg: pinmux_shared_io_q1_8 */
- <0x0000001c 0x00000008>,
- /* Reg: pinmux_shared_io_q1_9 */
- <0x00000020 0x00000008>,
- /* Reg: pinmux_shared_io_q1_10 */
- <0x00000024 0x00000008>,
- /* Reg: pinmux_shared_io_q1_11 */
- <0x00000028 0x00000008>,
- /* Reg: pinmux_shared_io_q1_12 */
- <0x0000002c 0x00000008>,
- /* Reg: pinmux_shared_io_q2_1 */
- <0x00000030 0x00000004>,
- /* Reg: pinmux_shared_io_q2_2 */
- <0x00000034 0x00000004>,
- /* Reg: pinmux_shared_io_q2_3 */
- <0x00000038 0x00000004>,
- /* Reg: pinmux_shared_io_q2_4 */
- <0x0000003c 0x00000004>,
- /* Reg: pinmux_shared_io_q2_5 */
- <0x00000040 0x00000004>,
- /* Reg: pinmux_shared_io_q2_6 */
- <0x00000044 0x00000004>,
- /* Reg: pinmux_shared_io_q2_7 */
- <0x00000048 0x00000004>,
- /* Reg: pinmux_shared_io_q2_8 */
- <0x0000004c 0x00000004>,
- /* Reg: pinmux_shared_io_q2_9 */
- <0x00000050 0x00000004>,
- /* Reg: pinmux_shared_io_q2_10 */
- <0x00000054 0x00000004>,
- /* Reg: pinmux_shared_io_q2_11 */
- <0x00000058 0x00000004>,
- /* Reg: pinmux_shared_io_q2_12 */
- <0x0000005c 0x00000004>,
- /* Reg: pinmux_shared_io_q3_1 */
- <0x00000060 0x00000003>,
- /* Reg: pinmux_shared_io_q3_2 */
- <0x00000064 0x00000003>,
- /* Reg: pinmux_shared_io_q3_3 */
- <0x00000068 0x00000003>,
- /* Reg: pinmux_shared_io_q3_4 */
- <0x0000006c 0x00000003>,
- /* Reg: pinmux_shared_io_q3_5 */
- <0x00000070 0x00000003>,
- /* Reg: pinmux_shared_io_q3_6 */
- <0x00000074 0x0000000f>,
- /* Reg: pinmux_shared_io_q3_7 */
- <0x00000078 0x0000000a>,
- /* Reg: pinmux_shared_io_q3_8 */
- <0x0000007c 0x0000000a>,
- /* Reg: pinmux_shared_io_q3_9 */
- <0x00000080 0x0000000a>,
- /* Reg: pinmux_shared_io_q3_10 */
- <0x00000084 0x0000000a>,
- /* Reg: pinmux_shared_io_q3_11 */
- <0x00000088 0x00000001>,
- /* Reg: pinmux_shared_io_q3_12 */
- <0x0000008c 0x00000001>,
- /* Reg: pinmux_shared_io_q4_1 */
- <0x00000090 0x00000000>,
- /* Reg: pinmux_shared_io_q4_2 */
- <0x00000094 0x00000000>,
- /* Reg: pinmux_shared_io_q4_3 */
- <0x00000098 0x0000000f>,
- /* Reg: pinmux_shared_io_q4_4 */
- <0x0000009c 0x0000000c>,
- /* Reg: pinmux_shared_io_q4_5 */
- <0x000000a0 0x0000000f>,
- /* Reg: pinmux_shared_io_q4_6 */
- <0x000000a4 0x0000000f>,
- /* Reg: pinmux_shared_io_q4_7 */
- <0x000000a8 0x0000000a>,
- /* Reg: pinmux_shared_io_q4_8 */
- <0x000000ac 0x0000000a>,
- /* Reg: pinmux_shared_io_q4_9 */
- <0x000000b0 0x0000000c>,
- /* Reg: pinmux_shared_io_q4_10 */
- <0x000000b4 0x0000000c>,
- /* Reg: pinmux_shared_io_q4_11 */
- <0x000000b8 0x0000000c>,
- /* Reg: pinmux_shared_io_q4_12 */
- <0x000000bc 0x0000000c>;
- };
-
+ mpu0 = <0x00000000 0x0000ffff>;
/*
- * Address Block: soc_3v_io48_pin_mux_OCP_SLV.
- * i_io48_pin_mux_dedicated_io_grp
+ * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr.hpsregion0addr.base
+ * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr.hpsregion0addr.limit
*/
- dedicated {
- u-boot,dm-pre-reloc;
- reg = <0xffd07200 0x00000200>;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0x0000000f>;
- pinctrl-single,pins =
- /* Reg: pinmux_dedicated_io_4 */
- <0x0000000c 0x00000008>,
- /* Reg: pinmux_dedicated_io_5 */
- <0x00000010 0x00000008>,
- /* Reg: pinmux_dedicated_io_6 */
- <0x00000014 0x00000008>,
- /* Regi: pinmux_dedicated_io_7 */
- <0x00000018 0x00000008>,
- /* Reg: pinmux_dedicated_io_8 */
- <0x0000001c 0x00000008>,
- /* Reg: pinmux_dedicated_io_9 */
- <0x00000020 0x00000008>,
- /* Reg: pinmux_dedicated_io_10 */
- <0x00000024 0x0000000a>,
- /* Reg: pinmux_dedicated_io_11 */
- <0x00000028 0x0000000a>,
- /* Reg: pinmux_dedicated_io_12 */
- <0x0000002c 0x00000008>,
- /* Reg: pinmux_dedicated_io_13 */
- <0x00000030 0x00000008>,
- /* Reg: pinmux_dedicated_io_14 */
- <0x00000034 0x00000008>,
- /* Reg: pinmux_dedicated_io_15 */
- <0x00000038 0x00000008>,
- /* Reg: pinmux_dedicated_io_16 */
- <0x0000003c 0x0000000d>,
- /* Reg: pinmux_dedicated_io_17 */
- <0x00000040 0x0000000d>;
- };
-
+ l3-0 = <0x00000000 0x0000ffff>;
/*
- * Address Block: soc_3v_io48_pin_mux_OCP_SLV.
- * i_io48_pin_mux_dedicated_io_grp
+ * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram0region0addr.base
+ * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram0region0addr.limit
*/
- dedicated_cfg {
- u-boot,dm-pre-reloc;
- reg = <0xffd07200 0x00000200>;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0x003f3f3f>;
- pinctrl-single,pins =
- /* Reg: cfg_dedicated_io_bank */
- <0x00000100 0x00000101>,
- /* Reg: cfg_dedicated_io_1 */
- <0x00000104 0x000b080a>,
- /* Reg: cfg_dedicated_io_2 */
- <0x00000108 0x000b080a>,
- /* Reg: cfg_dedicated_io_3 */
- <0x0000010c 0x000b080a>,
- /* Reg: cfg_dedicated_io_4 */
- <0x00000110 0x000a282a>,
- /* Reg: cfg_dedicated_io_5 */
- <0x00000114 0x000a282a>,
- /* Reg: cfg_dedicated_io_6 */
- <0x00000118 0x0008282a>,
- /* Reg: cfg_dedicated_io_7 */
- <0x0000011c 0x000a282a>,
- /* Reg: cfg_dedicated_io_8 */
- <0x00000120 0x000a282a>,
- /* Reg: cfg_dedicated_io_9 */
- <0x00000124 0x000a282a>,
- /* Reg: cfg_dedicated_io_10 */
- <0x00000128 0x00090000>,
- /* Reg: cfg_dedicated_io_11 */
- <0x0000012c 0x00090000>,
- /* Reg: cfg_dedicated_io_12 */
- <0x00000130 0x000b282a>,
- /* Reg: cfg_dedicated_io_13 */
- <0x00000134 0x000b282a>,
- /* Reg: cfg_dedicated_io_14 */
- <0x00000138 0x000b282a>,
- /* Reg: cfg_dedicated_io_15 */
- <0x0000013c 0x000b282a>,
- /* Reg: cfg_dedicated_io_16 */
- <0x00000140 0x0008282a>,
- /* Reg: cfg_dedicated_io_17 */
- <0x00000144 0x000a282a>;
- };
-
+ fpga2sdram0-0 = <0x00000000 0x0000ffff>;
/*
- * Address Block: soc_3v_io48_pin_mux_OCP_SLV.
- * i_io48_pin_mux_fpga_interface_grp
+ * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram1region0addr.base
+ * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram1region0addr.limit
*/
- fpga {
- u-boot,dm-pre-reloc;
- reg = <0xffd07400 0x00000100>;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0x00000001>;
- pinctrl-single,pins =
- /* Reg: pinmux_emac0_usefpga */
- <0x00000000 0x00000000>,
- /* Reg: pinmux_emac1_usefpga */
- <0x00000004 0x00000000>,
- /* Reg: pinmux_emac2_usefpga */
- <0x00000008 0x00000000>,
- /* Reg: pinmux_i2c0_usefpga */
- <0x0000000c 0x00000000>,
- /* Reg: pinmux_i2c1_usefpga */
- <0x00000010 0x00000000>,
- /* Reg: pinmux_i2c_emac0_usefpga */
- <0x00000014 0x00000000>,
- /* Reg: pinmux_i2c_emac1_usefpga */
- <0x00000018 0x00000000>,
- /* Reg: pinmux_i2c_emac2_usefpga */
- <0x0000001c 0x00000000>,
- /* Reg: pinmux_nand_usefpga */
- <0x00000020 0x00000000>,
- /* Reg: pinmux_qspi_usefpga */
- <0x00000024 0x00000000>,
- /* Reg: pinmux_sdmmc_usefpga */
- <0x00000028 0x00000000>,
- /* Reg: pinmux_spim0_usefpga */
- <0x0000002c 0x00000000>,
- /* Reg: pinmux_spim1_usefpga */
- <0x00000030 0x00000000>,
- /* Reg: pinmux_spis0_usefpga */
- <0x00000034 0x00000000>,
- /* Reg: pinmux_spis1_usefpga */
- <0x00000038 0x00000000>,
- /* Reg: pinmux_uart0_usefpga */
- <0x0000003c 0x00000000>,
- /* Reg: pinmux_uart1_usefpga */
- <0x00000040 0x00000000>;
- };
- };
-
- i_noc: noc@0xffd10000 {
- u-boot,dm-pre-reloc;
- compatible = "altr,socfpga-a10-noc";
- reg = <0xffd10000 0x00008000>;
- reg-names = "mpu_m0";
-
- firewall {
- u-boot,dm-pre-reloc;
- /*
- * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
- * I_NOC.mpu_m0.
- * noc_fw_ddr_mpu_fpga2sdram_ddr_scr.
- * mpuregion0addr.base
- * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
- * I_NOC.mpu_m0.
- * noc_fw_ddr_mpu_fpga2sdram_ddr_scr.
- * mpuregion0addr.limit
- */
- altr,mpu0 = <0x00000000 0x0000ffff>;
- /*
- * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
- * I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr.
- * hpsregion0addr.base
- * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
- * I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr.
- * hpsregion0addr.limit
- */
- altr,l3-0 = <0x00000000 0x0000ffff>;
- /*
- * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
- * I_NOC.mpu_m0.
- * noc_fw_ddr_mpu_fpga2sdram_ddr_scr.
- * fpga2sdram0region0addr.base
- * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
- * I_NOC.mpu_m0.
- * noc_fw_ddr_mpu_fpga2sdram_ddr_scr.
- * fpga2sdram0region0addr.limit
- */
- altr,fpga2sdram0-0 = <0x00000000 0x0000ffff>;
- /*
- * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
- * I_NOC.mpu_m0.
- * noc_fw_ddr_mpu_fpga2sdram_ddr_scr.
- * fpga2sdram1region0addr.base
- * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
- * I_NOC.mpu_m0.
- * noc_fw_ddr_mpu_fpga2sdram_ddr_scr.
- * fpga2sdram1region0addr.limit
- */
- altr,fpga2sdram1-0 = <0x00000000 0x0000ffff>;
- /*
- * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
- * I_NOC.mpu_m0.
- * noc_fw_ddr_mpu_fpga2sdram_ddr_scr.
- * fpga2sdram2region0addr.base
- * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
- * I_NOC.mpu_m0.
- * noc_fw_ddr_mpu_fpga2sdram_ddr_scr.
- * fpga2sdram2region0addr.limit
- */
- altr,fpga2sdram2-0 = <0x00000000 0x0000ffff>;
- };
+ fpga2sdram1-0 = <0x00000000 0x0000ffff>;
+ /*
+ * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram2region0addr.base
+ * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram2region0addr.limit
+ */
+ fpga2sdram2-0 = <0x00000000 0x0000ffff>;
};
+ };
- hps_fpgabridge0: fpgabridge@0 {
- compatible = "altr,socfpga-hps2fpga-bridge";
- altr,init-val = <1>;
- };
+ hps_fpgabridge0: fpgabridge@0 {
+ compatible = "altr,socfpga-hps2fpga-bridge";
+ init-val = <1>;
+ };
- hps_fpgabridge1: fpgabridge@1 {
- compatible = "altr,socfpga-lwhps2fpga-bridge";
- altr,init-val = <1>;
- };
+ hps_fpgabridge1: fpgabridge@1 {
+ compatible = "altr,socfpga-lwhps2fpga-bridge";
+ init-val = <1>;
+ };
- hps_fpgabridge2: fpgabridge@2 {
- compatible = "altr,socfpga-fpga2hps-bridge";
- altr,init-val = <1>;
- };
+ hps_fpgabridge2: fpgabridge@2 {
+ compatible = "altr,socfpga-fpga2hps-bridge";
+ init-val = <1>;
+ };
- hps_fpgabridge3: fpgabridge@3 {
- compatible = "altr,socfpga-fpga2sdram0-bridge";
- altr,init-val = <1>;
- };
+ hps_fpgabridge3: fpgabridge@3 {
+ compatible = "altr,socfpga-fpga2sdram0-bridge";
+ init-val = <1>;
+ };
- hps_fpgabridge4: fpgabridge@4 {
- compatible = "altr,socfpga-fpga2sdram1-bridge";
- altr,init-val = <0>;
- };
+ hps_fpgabridge4: fpgabridge@4 {
+ compatible = "altr,socfpga-fpga2sdram1-bridge";
+ init-val = <0>;
+ };
- hps_fpgabridge5: fpgabridge@5 {
- compatible = "altr,socfpga-fpga2sdram2-bridge";
- altr,init-val = <1>;
- };
+ hps_fpgabridge5: fpgabridge@5 {
+ compatible = "altr,socfpga-fpga2sdram2-bridge";
+ init-val = <1>;
};
};
diff --git a/arch/arm/dts/socfpga_stratix10.dtsi b/arch/arm/dts/socfpga_stratix10.dtsi
index db8eb7ce7a..ccd3f32301 100644
--- a/arch/arm/dts/socfpga_stratix10.dtsi
+++ b/arch/arm/dts/socfpga_stratix10.dtsi
@@ -80,6 +80,7 @@
device_type = "soc";
interrupt-parent = <&intc>;
ranges = <0 0 0 0xffffffff>;
+ u-boot,dm-pre-reloc;
clkmgr@ffd1000 {
compatible = "altr,clk-mgr";
@@ -92,7 +93,7 @@
interrupts = <0 90 4>;
interrupt-names = "macirq";
mac-address = [00 00 00 00 00 00];
- resets = <&rst EMAC0_RESET>;
+ resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
reset-names = "stmmaceth";
status = "disabled";
};
@@ -103,7 +104,7 @@
interrupts = <0 91 4>;
interrupt-names = "macirq";
mac-address = [00 00 00 00 00 00];
- resets = <&rst EMAC1_RESET>;
+ resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
reset-names = "stmmaceth";
status = "disabled";
};
@@ -114,7 +115,7 @@
interrupts = <0 92 4>;
interrupt-names = "macirq";
mac-address = [00 00 00 00 00 00];
- resets = <&rst EMAC2_RESET>;
+ resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
reset-names = "stmmaceth";
status = "disabled";
};
@@ -136,6 +137,7 @@
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <0 110 4>;
+ bank-name = "porta";
};
};
@@ -156,6 +158,7 @@
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <0 111 4>;
+ bank-name = "portb";
};
};
@@ -166,6 +169,7 @@
reg = <0xffc02800 0x100>;
interrupts = <0 103 4>;
resets = <&rst I2C0_RESET>;
+ reset-names = "i2c";
status = "disabled";
};
@@ -176,6 +180,7 @@
reg = <0xffc02900 0x100>;
interrupts = <0 104 4>;
resets = <&rst I2C1_RESET>;
+ reset-names = "i2c";
status = "disabled";
};
@@ -186,6 +191,7 @@
reg = <0xffc02a00 0x100>;
interrupts = <0 105 4>;
resets = <&rst I2C2_RESET>;
+ reset-names = "i2c";
status = "disabled";
};
@@ -196,6 +202,7 @@
reg = <0xffc02b00 0x100>;
interrupts = <0 106 4>;
resets = <&rst I2C3_RESET>;
+ reset-names = "i2c";
status = "disabled";
};
@@ -206,6 +213,7 @@
reg = <0xffc02c00 0x100>;
interrupts = <0 107 4>;
resets = <&rst I2C4_RESET>;
+ reset-names = "i2c";
status = "disabled";
};
@@ -216,8 +224,8 @@
reg = <0xff808000 0x1000>;
interrupts = <0 96 4>;
fifo-depth = <0x400>;
- resets = <&rst SDMMC_RESET>;
- reset-names = "reset";
+ resets = <&rst SDMMC_RESET>, <&rst SDMMC_OCP_RESET>;
+ u-boot,dm-pre-reloc;
status = "disabled";
};
@@ -231,6 +239,7 @@
compatible = "altr,rst-mgr";
reg = <0xffd11000 0x1000>;
altr,modrst-offset = <0x20>;
+ u-boot,dm-pre-reloc;
};
spi0: spi@ffda4000 {
@@ -304,6 +313,8 @@
reg-shift = <2>;
reg-io-width = <4>;
resets = <&rst UART0_RESET>;
+ clock-frequency = <100000000>;
+ u-boot,dm-pre-reloc;
status = "disabled";
};
@@ -350,6 +361,7 @@
reg = <0xffd00200 0x100>;
interrupts = <0 117 4>;
resets = <&rst WATCHDOG0_RESET>;
+ u-boot,dm-pre-reloc;
status = "disabled";
};
diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts b/arch/arm/dts/socfpga_stratix10_socdk.dts
index d5f43a23e7..c6ab0ae992 100644
--- a/arch/arm/dts/socfpga_stratix10_socdk.dts
+++ b/arch/arm/dts/socfpga_stratix10_socdk.dts
@@ -78,8 +78,11 @@
&mmc {
status = "okay";
cap-sd-highspeed;
+ cap-mmc-highspeed;
broken-cd;
bus-width = <4>;
+ drvsel = <3>;
+ smplsel = <0>;
};
&uart0 {
generated by cgit (git 2.34.1) at 2025-01-09 15:16:45 +0000