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-rw-r--r--arch/arm/dts/Makefile4
-rw-r--r--arch/arm/dts/versal-mini-emmc0.dts64
-rw-r--r--arch/arm/dts/versal-mini-emmc1.dts64
-rw-r--r--arch/arm/dts/versal-mini.dts36
-rw-r--r--arch/arm/dts/zynq-7000.dtsi4
-rw-r--r--arch/arm/dts/zynq-cc108.dts2
-rw-r--r--arch/arm/dts/zynq-microzed.dts2
-rw-r--r--arch/arm/dts/zynq-syzygy-hub.dts6
-rw-r--r--arch/arm/dts/zynq-zc702.dts2
-rw-r--r--arch/arm/dts/zynq-zc706.dts2
-rw-r--r--arch/arm/dts/zynq-zc770-xm010.dts3
-rw-r--r--arch/arm/dts/zynq-zc770-xm011.dts2
-rw-r--r--arch/arm/dts/zynq-zc770-xm012.dts2
-rw-r--r--arch/arm/dts/zynq-zc770-xm013.dts2
-rw-r--r--arch/arm/dts/zynq-zed.dts4
-rw-r--r--arch/arm/dts/zynq-zybo.dts2
-rw-r--r--arch/arm/dts/zynqmp-zc1275-revB.dts2
-rw-r--r--arch/arm/dts/zynqmp-zcu100-revC.dts2
-rw-r--r--arch/arm/dts/zynqmp-zcu102-revA.dts17
-rw-r--r--arch/arm/dts/zynqmp-zcu104-revC.dts1
-rw-r--r--arch/arm/dts/zynqmp-zcu106-revA.dts21
-rw-r--r--arch/arm/dts/zynqmp-zcu111-revA.dts21
-rw-r--r--arch/arm/dts/zynqmp.dtsi5
23 files changed, 195 insertions, 75 deletions
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 13ab3cc0b5..fbc0f8afea 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -186,6 +186,10 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
zynqmp-zc1751-xm017-dc3.dtb \
zynqmp-zc1751-xm018-dc4.dtb \
zynqmp-zc1751-xm019-dc5.dtb
+dtb-$(CONFIG_ARCH_VERSAL) += \
+ versal-mini.dtb \
+ versal-mini-emmc0.dtb \
+ versal-mini-emmc1.dtb
dtb-$(CONFIG_ARCH_ZYNQMP_R5) += \
zynqmp-r5.dtb
dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-bone.dtb \
diff --git a/arch/arm/dts/versal-mini-emmc0.dts b/arch/arm/dts/versal-mini-emmc0.dts
new file mode 100644
index 0000000000..7f57d232b7
--- /dev/null
+++ b/arch/arm/dts/versal-mini-emmc0.dts
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx Versal Mini eMMC0 Configuration
+ *
+ * (C) Copyright 2018-2019, Xilinx, Inc.
+ *
+ * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+/dts-v1/;
+
+/ {
+ compatible = "xlnx,versal";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ model = "Xilinx Versal MINI eMMC0";
+
+ clk25: clk25 {
+ compatible = "fixed-clock";
+ #clock-cells = <0x0>;
+ clock-frequency = <25000000>;
+ };
+
+ dcc: dcc {
+ compatible = "arm,dcc";
+ status = "okay";
+ u-boot,dm-pre-reloc;
+ };
+
+ amba: amba {
+ u-boot,dm-pre-reloc;
+ compatible = "simple-bus";
+ #address-cells = <0x2>;
+ #size-cells = <0x2>;
+ ranges;
+
+ sdhci0: sdhci@f1040000 {
+ compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a";
+ status = "okay";
+ reg = <0x0 0xf1040000 0x0 0x10000>;
+ clock-names = "clk_xin", "clk_ahb";
+ clocks = <&clk25 &clk25>;
+ xlnx,device_id = <0>;
+ no-1-8-v;
+ xlnx,mio_bank = <0>;
+ #stream-id-cells = <1>;
+ };
+ };
+
+ aliases {
+ serial0 = &dcc;
+ mmc0 = &sdhci0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x20000000>;
+ };
+};
diff --git a/arch/arm/dts/versal-mini-emmc1.dts b/arch/arm/dts/versal-mini-emmc1.dts
new file mode 100644
index 0000000000..9ecb1ce5dc
--- /dev/null
+++ b/arch/arm/dts/versal-mini-emmc1.dts
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx Versal Mini eMMC1 Configuration
+ *
+ * (C) Copyright 2018-2019, Xilinx, Inc.
+ *
+ * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+/dts-v1/;
+
+/ {
+ compatible = "xlnx,versal";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ model = "Xilinx Versal MINI eMMC1";
+
+ clk25: clk25 {
+ compatible = "fixed-clock";
+ #clock-cells = <0x0>;
+ clock-frequency = <25000000>;
+ };
+
+ dcc: dcc {
+ compatible = "arm,dcc";
+ status = "okay";
+ u-boot,dm-pre-reloc;
+ };
+
+ amba: amba {
+ u-boot,dm-pre-reloc;
+ compatible = "simple-bus";
+ #address-cells = <0x2>;
+ #size-cells = <0x2>;
+ ranges;
+
+ sdhci1: sdhci@f105000 {
+ compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a";
+ status = "okay";
+ reg = <0x0 0xf1050000 0x0 0x10000>;
+ clock-names = "clk_xin", "clk_ahb";
+ clocks = <&clk25 &clk25>;
+ xlnx,device_id = <1>;
+ no-1-8-v;
+ xlnx,mio_bank = <0>;
+ #stream-id-cells = <1>;
+ };
+ };
+
+ aliases {
+ serial0 = &dcc;
+ mmc0 = &sdhci1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x20000000>;
+ };
+};
diff --git a/arch/arm/dts/versal-mini.dts b/arch/arm/dts/versal-mini.dts
new file mode 100644
index 0000000000..6a83981cc2
--- /dev/null
+++ b/arch/arm/dts/versal-mini.dts
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx Versal Mini Configuration
+ *
+ * (C) Copyright 2019, Xilinx, Inc.
+ *
+ * Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
+ */
+
+/dts-v1/;
+
+/ {
+ model = "Versal MINI";
+ compatible = "xlnx,versal";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ serial0 = &dcc;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0xfffc0000 0x0 0x40000>, <0x0 0x0 0x0 0x80000000>;
+ };
+
+ dcc: dcc {
+ compatible = "arm,dcc";
+ status = "okay";
+ u-boot,dm-pre-reloc;
+ };
+};
diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
index 286059d56e..e1b0816a34 100644
--- a/arch/arm/dts/zynq-7000.dtsi
+++ b/arch/arm/dts/zynq-7000.dtsi
@@ -235,7 +235,7 @@
#size-cells = <0>;
};
- sdhci0: sdhci@e0100000 {
+ sdhci0: mmc@e0100000 {
compatible = "arasan,sdhci-8.9a";
status = "disabled";
clock-names = "clk_xin", "clk_ahb";
@@ -245,7 +245,7 @@
reg = <0xe0100000 0x1000>;
};
- sdhci1: sdhci@e0101000 {
+ sdhci1: mmc@e0101000 {
compatible = "arasan,sdhci-8.9a";
status = "disabled";
clock-names = "clk_xin", "clk_ahb";
diff --git a/arch/arm/dts/zynq-cc108.dts b/arch/arm/dts/zynq-cc108.dts
index 5f8a0d2555..64d73ecbc5 100644
--- a/arch/arm/dts/zynq-cc108.dts
+++ b/arch/arm/dts/zynq-cc108.dts
@@ -12,8 +12,8 @@
/include/ "zynq-7000.dtsi"
/ {
+ model = "Xilinx CC108 board";
compatible = "xlnx,zynq-cc108", "xlnx,zynq-7000";
- model = "Xilinx Zynq";
aliases {
ethernet0 = &gem0;
diff --git a/arch/arm/dts/zynq-microzed.dts b/arch/arm/dts/zynq-microzed.dts
index 79f878eab2..0766398605 100644
--- a/arch/arm/dts/zynq-microzed.dts
+++ b/arch/arm/dts/zynq-microzed.dts
@@ -9,7 +9,7 @@
/ {
model = "Zynq MicroZED Board";
- compatible = "xlnx,zynq-microzed", "xlnx,zynq-7000";
+ compatible = "avnet,zynq-microzed", "xlnx,zynq-microzed", "xlnx,zynq-7000";
aliases {
serial0 = &uart1;
diff --git a/arch/arm/dts/zynq-syzygy-hub.dts b/arch/arm/dts/zynq-syzygy-hub.dts
index a30d667146..55f8e8a2da 100644
--- a/arch/arm/dts/zynq-syzygy-hub.dts
+++ b/arch/arm/dts/zynq-syzygy-hub.dts
@@ -16,6 +16,7 @@
ethernet0 = &gem0;
serial0 = &uart0;
mmc0 = &sdhci0;
+ i2c0 = &i2c1;
};
memory@0 {
@@ -26,6 +27,7 @@
chosen {
bootargs = "";
stdout-path = "serial0:115200n8";
+ xlnx,eeprom = &eeprom;
};
usb_phy0: phy0 {
@@ -52,6 +54,10 @@
&i2c1 {
status = "okay";
+ eeprom: eeprom@57 {
+ compatible = "atmel,24c08"; /* not sure if this is correct */
+ reg = <0x57>;
+ };
};
&sdhci0 {
diff --git a/arch/arm/dts/zynq-zc702.dts b/arch/arm/dts/zynq-zc702.dts
index 12e35618f8..54231cd580 100644
--- a/arch/arm/dts/zynq-zc702.dts
+++ b/arch/arm/dts/zynq-zc702.dts
@@ -7,7 +7,7 @@
#include "zynq-7000.dtsi"
/ {
- model = "Zynq ZC702 Development Board";
+ model = "Xilinx ZC702 board";
compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000";
aliases {
diff --git a/arch/arm/dts/zynq-zc706.dts b/arch/arm/dts/zynq-zc706.dts
index f24364b385..84729e9feb 100644
--- a/arch/arm/dts/zynq-zc706.dts
+++ b/arch/arm/dts/zynq-zc706.dts
@@ -7,7 +7,7 @@
#include "zynq-7000.dtsi"
/ {
- model = "Zynq ZC706 Development Board";
+ model = "Xilinx ZC706 board";
compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000";
aliases {
diff --git a/arch/arm/dts/zynq-zc770-xm010.dts b/arch/arm/dts/zynq-zc770-xm010.dts
index a779672f3a..e1f34653ec 100644
--- a/arch/arm/dts/zynq-zc770-xm010.dts
+++ b/arch/arm/dts/zynq-zc770-xm010.dts
@@ -8,8 +8,8 @@
#include "zynq-7000.dtsi"
/ {
+ model = "Xilinx ZC770 XM010 board";
compatible = "xlnx,zynq-zc770-xm010", "xlnx,zynq-7000";
- model = "Xilinx Zynq";
aliases {
ethernet0 = &gem0;
@@ -58,7 +58,6 @@
compatible = "atmel,24c02";
reg = <0x52>;
};
-
};
&qspi {
diff --git a/arch/arm/dts/zynq-zc770-xm011.dts b/arch/arm/dts/zynq-zc770-xm011.dts
index 3fe6eb559e..1123bfc743 100644
--- a/arch/arm/dts/zynq-zc770-xm011.dts
+++ b/arch/arm/dts/zynq-zc770-xm011.dts
@@ -8,8 +8,8 @@
#include "zynq-7000.dtsi"
/ {
+ model = "Xilinx ZC770 XM011 board";
compatible = "xlnx,zynq-zc770-xm011", "xlnx,zynq-7000";
- model = "Xilinx Zynq";
aliases {
i2c0 = &i2c1;
diff --git a/arch/arm/dts/zynq-zc770-xm012.dts b/arch/arm/dts/zynq-zc770-xm012.dts
index 19d5b275ae..0d001c9161 100644
--- a/arch/arm/dts/zynq-zc770-xm012.dts
+++ b/arch/arm/dts/zynq-zc770-xm012.dts
@@ -8,8 +8,8 @@
#include "zynq-7000.dtsi"
/ {
+ model = "Xilinx ZC770 XM012 board";
compatible = "xlnx,zynq-zc770-xm012", "xlnx,zynq-7000";
- model = "Xilinx Zynq";
aliases {
i2c0 = &i2c0;
diff --git a/arch/arm/dts/zynq-zc770-xm013.dts b/arch/arm/dts/zynq-zc770-xm013.dts
index efd0833eab..05a49982cc 100644
--- a/arch/arm/dts/zynq-zc770-xm013.dts
+++ b/arch/arm/dts/zynq-zc770-xm013.dts
@@ -8,8 +8,8 @@
#include "zynq-7000.dtsi"
/ {
+ model = "Xilinx ZC770 XM013 board";
compatible = "xlnx,zynq-zc770-xm013", "xlnx,zynq-7000";
- model = "Xilinx Zynq";
aliases {
ethernet0 = &gem1;
diff --git a/arch/arm/dts/zynq-zed.dts b/arch/arm/dts/zynq-zed.dts
index 9c505fb7b8..d2b7fc2c99 100644
--- a/arch/arm/dts/zynq-zed.dts
+++ b/arch/arm/dts/zynq-zed.dts
@@ -7,8 +7,8 @@
#include "zynq-7000.dtsi"
/ {
- model = "Zynq Zed Development Board";
- compatible = "xlnx,zynq-zed", "xlnx,zynq-7000";
+ model = "Avnet ZedBoard board";
+ compatible = "avnet,zynq-zed", "xlnx,zynq-zed", "xlnx,zynq-7000";
aliases {
ethernet0 = &gem0;
diff --git a/arch/arm/dts/zynq-zybo.dts b/arch/arm/dts/zynq-zybo.dts
index 3844822305..0ac54ebbdc 100644
--- a/arch/arm/dts/zynq-zybo.dts
+++ b/arch/arm/dts/zynq-zybo.dts
@@ -7,7 +7,7 @@
#include "zynq-7000.dtsi"
/ {
- model = "Zynq ZYBO Development Board";
+ model = "Digilent Zybo board";
compatible = "digilent,zynq-zybo", "xlnx,zynq-7000";
aliases {
diff --git a/arch/arm/dts/zynqmp-zc1275-revB.dts b/arch/arm/dts/zynqmp-zc1275-revB.dts
index e84b2da164..1a7975b551 100644
--- a/arch/arm/dts/zynqmp-zc1275-revB.dts
+++ b/arch/arm/dts/zynqmp-zc1275-revB.dts
@@ -47,7 +47,7 @@
#size-cells = <1>;
reg = <0x0>;
spi-tx-bus-width = <1>;
- spi-rx-bus-width = <4>;
+ spi-rx-bus-width = <1>;
spi-max-frequency = <108000000>; /* Based on DC1 spec */
partition@qspi-fsbl-uboot { /* for testing purpose */
label = "qspi-fsbl-uboot";
diff --git a/arch/arm/dts/zynqmp-zcu100-revC.dts b/arch/arm/dts/zynqmp-zcu100-revC.dts
index 05491e9bbc..5285f62d1a 100644
--- a/arch/arm/dts/zynqmp-zcu100-revC.dts
+++ b/arch/arm/dts/zynqmp-zcu100-revC.dts
@@ -296,7 +296,6 @@
compatible = "ti,wl1831-st";
enable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;
};
-
};
&uart1 {
@@ -332,7 +331,6 @@
&watchdog0 {
status = "okay";
- reset-on-timeout;
};
&xilinx_ams {
diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts
index 05be919f6f..0e96a36188 100644
--- a/arch/arm/dts/zynqmp-zcu102-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu102-revA.dts
@@ -36,6 +36,7 @@
chosen {
bootargs = "earlycon";
stdout-path = "serial0:115200n8";
+ xlnx,eeprom = &eeprom;
};
memory@0 {
@@ -360,7 +361,6 @@
status = "disabled"; /* unreachable */
reg = <0x20>;
};
-
max20751@72 { /* u95 */
compatible = "maxim,max20751";
reg = <0x72>;
@@ -485,21 +485,6 @@
#size-cells = <0>;
reg = <3>;
/* DDR4 SODIMM */
- dev@19 {
- reg = <0x19>;
- };
- dev@30 {
- reg = <0x30>;
- };
- dev@35 {
- reg = <0x35>;
- };
- dev@36 {
- reg = <0x36>;
- };
- dev@51 {
- reg = <0x51>;
- };
};
i2c@4 {
#address-cells = <1>;
diff --git a/arch/arm/dts/zynqmp-zcu104-revC.dts b/arch/arm/dts/zynqmp-zcu104-revC.dts
index becc6a0fe1..623d2c96cd 100644
--- a/arch/arm/dts/zynqmp-zcu104-revC.dts
+++ b/arch/arm/dts/zynqmp-zcu104-revC.dts
@@ -34,6 +34,7 @@
chosen {
bootargs = "earlycon";
stdout-path = "serial0:115200n8";
+ xlnx,eeprom = &eeprom;
};
memory@0 {
diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts b/arch/arm/dts/zynqmp-zcu106-revA.dts
index 7735e9d2c8..00f6e30ef3 100644
--- a/arch/arm/dts/zynqmp-zcu106-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu106-revA.dts
@@ -36,6 +36,7 @@
chosen {
bootargs = "earlycon";
stdout-path = "serial0:115200n8";
+ xlnx,eeprom = &eeprom;
};
memory@0 {
@@ -462,26 +463,6 @@
#size-cells = <0>;
reg = <3>;
/* DDR4 SODIMM */
- dev@19 { /* u-boot detection */
- compatible = "xxx";
- reg = <0x19>;
- };
- dev@30 { /* u-boot detection */
- compatible = "xxx";
- reg = <0x30>;
- };
- dev@35 { /* u-boot detection */
- compatible = "xxx";
- reg = <0x35>;
- };
- dev@36 { /* u-boot detection */
- compatible = "xxx";
- reg = <0x36>;
- };
- dev@51 { /* u-boot detection - maybe SPD */
- compatible = "xxx";
- reg = <0x51>;
- };
};
i2c@4 {
#address-cells = <1>;
diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts
index 172e6cc2ca..58021be9bf 100644
--- a/arch/arm/dts/zynqmp-zcu111-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu111-revA.dts
@@ -35,6 +35,7 @@
chosen {
bootargs = "earlycon";
stdout-path = "serial0:115200n8";
+ xlnx,eeprom = &eeprom;
};
memory@0 {
@@ -399,26 +400,6 @@
#size-cells = <0>;
reg = <3>;
/* DDR4 SODIMM */
- dev@19 { /* u-boot detection FIXME */
- compatible = "xxx";
- reg = <0x19>;
- };
- dev@30 { /* u-boot detection */
- compatible = "xxx";
- reg = <0x30>;
- };
- dev@35 { /* u-boot detection */
- compatible = "xxx";
- reg = <0x35>;
- };
- dev@36 { /* u-boot detection */
- compatible = "xxx";
- reg = <0x36>;
- };
- dev@51 { /* u-boot detection - maybe SPD */
- compatible = "xxx";
- reg = <0x51>;
- };
};
i2c@4 {
#address-cells = <1>;
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index 831d6e1ecc..dfb6ebc64c 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -58,7 +58,7 @@
};
idle-states {
- entry-method = "arm,psci";
+ entry-method = "psci";
CPU_SLEEP_0: cpu-sleep-0 {
compatible = "arm,idle-state";
@@ -884,7 +884,8 @@
interrupt-parent = <&gic>;
interrupts = <0 113 1>;
reg = <0x0 0xfd4d0000 0x0 0x1000>;
- timeout-sec = <10>;
+ timeout-sec = <60>;
+ reset-on-timeout;
};
xilinx_ams: ams@ffa50000 {
generated by cgit (git 2.34.1) at 2025-01-11 22:39:42 +0000