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-rw-r--r--arch/arm/dts/Makefile4
-rw-r--r--arch/arm/dts/armada-388-clearfog-u-boot.dtsi9
-rw-r--r--arch/arm/dts/armada-388-clearfog.dts449
-rw-r--r--arch/arm/dts/armada-388-helios4.dts8
-rw-r--r--arch/arm/dts/armada-38x-solidrun-microsom.dtsi2
-rw-r--r--arch/arm/dts/avnet-ultra96-rev1.dts19
-rw-r--r--arch/arm/dts/exynos4210-pinctrl-uboot.dtsi4
-rw-r--r--arch/arm/dts/exynos4210-universal_c210.dts2
-rw-r--r--arch/arm/dts/exynos4x12-pinctrl-uboot.dtsi4
-rw-r--r--arch/arm/dts/exynos5.dtsi2
-rw-r--r--arch/arm/dts/exynos5250-pinctrl-uboot.dtsi4
-rw-r--r--arch/arm/dts/exynos5250-spring.dts2
-rw-r--r--arch/arm/dts/exynos54xx-pinctrl-uboot.dtsi8
-rw-r--r--arch/arm/dts/kirkwood-atl-sbx81lifxcat.dts145
-rw-r--r--arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi24
-rw-r--r--arch/arm/dts/zynq-cse-nand.dts3
-rw-r--r--arch/arm/dts/zynq-cse-nor.dts2
-rw-r--r--arch/arm/dts/zynq-zed.dts7
-rw-r--r--arch/arm/dts/zynq-zybo-z7.dts81
-rw-r--r--arch/arm/dts/zynqmp-mini-emmc1.dts3
20 files changed, 451 insertions, 331 deletions
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 89032bb545..ebfa227262 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -149,8 +149,10 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \
zynq-zc770-xm013.dtb \
zynq-zed.dtb \
zynq-zturn.dtb \
- zynq-zybo.dtb
+ zynq-zybo.dtb \
+ zynq-zybo-z7.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += \
+ avnet-ultra96-rev1.dtb \
zynqmp-mini-emmc0.dtb \
zynqmp-mini-emmc1.dtb \
zynqmp-mini-nand.dtb \
diff --git a/arch/arm/dts/armada-388-clearfog-u-boot.dtsi b/arch/arm/dts/armada-388-clearfog-u-boot.dtsi
new file mode 100644
index 0000000000..f31691ee94
--- /dev/null
+++ b/arch/arm/dts/armada-388-clearfog-u-boot.dtsi
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+&spi1 {
+ u-boot,dm-spl;
+
+ spi-flash@0 {
+ u-boot,dm-spl;
+ };
+};
diff --git a/arch/arm/dts/armada-388-clearfog.dts b/arch/arm/dts/armada-388-clearfog.dts
index a0b566a5ae..16a47d59e6 100644
--- a/arch/arm/dts/armada-388-clearfog.dts
+++ b/arch/arm/dts/armada-388-clearfog.dts
@@ -50,6 +50,7 @@
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include "armada-388.dtsi"
+#include "armada-38x-solidrun-microsom.dtsi"
/ {
model = "SolidRun Clearfog A1";
@@ -70,11 +71,6 @@
stdout-path = "serial0:115200n8";
};
- memory {
- device_type = "memory";
- reg = <0x00000000 0x10000000>; /* 256 MB */
- };
-
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "3P3V";
@@ -84,211 +80,7 @@
};
soc {
- ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
- MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
- MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
- MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>;
-
internal-regs {
- ethernet@30000 {
- mac-address = [00 50 43 02 02 02];
- phy-mode = "sgmii";
- status = "okay";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
-
- ethernet@34000 {
- mac-address = [00 50 43 02 02 03];
- managed = "in-band-status";
- phy-mode = "sgmii";
- status = "okay";
- };
-
- ethernet@70000 {
- mac-address = [00 50 43 02 02 01];
- pinctrl-0 = <&ge0_rgmii_pins>;
- pinctrl-names = "default";
- phy = <&phy_dedicated>;
- phy-mode = "rgmii-id";
- status = "okay";
- };
-
- i2c@11000 {
- /* Is there anything on this? */
- clock-frequency = <100000>;
- pinctrl-0 = <&i2c0_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- /*
- * PCA9655 GPIO expander, up to 1MHz clock.
- * 0-CON3 CLKREQ#
- * 1-CON3 PERST#
- * 2-CON2 PERST#
- * 3-CON3 W_DISABLE
- * 4-CON2 CLKREQ#
- * 5-USB3 overcurrent
- * 6-USB3 power
- * 7-CON2 W_DISABLE
- * 8-JP4 P1
- * 9-JP4 P4
- * 10-JP4 P5
- * 11-m.2 DEVSLP
- * 12-SFP_LOS
- * 13-SFP_TX_FAULT
- * 14-SFP_TX_DISABLE
- * 15-SFP_MOD_DEF0
- */
- expander0: gpio-expander@20 {
- /*
- * This is how it should be:
- * compatible = "onnn,pca9655",
- * "nxp,pca9555";
- * but you can't do this because of
- * the way I2C works.
- */
- compatible = "nxp,pca9555";
- gpio-controller;
- #gpio-cells = <2>;
- reg = <0x20>;
-
- pcie1_0_clkreq {
- gpio-hog;
- gpios = <0 GPIO_ACTIVE_LOW>;
- input;
- line-name = "pcie1.0-clkreq";
- };
- pcie1_0_w_disable {
- gpio-hog;
- gpios = <3 GPIO_ACTIVE_LOW>;
- output-low;
- line-name = "pcie1.0-w-disable";
- };
- pcie2_0_clkreq {
- gpio-hog;
- gpios = <4 GPIO_ACTIVE_LOW>;
- input;
- line-name = "pcie2.0-clkreq";
- };
- pcie2_0_w_disable {
- gpio-hog;
- gpios = <7 GPIO_ACTIVE_LOW>;
- output-low;
- line-name = "pcie2.0-w-disable";
- };
- usb3_ilimit {
- gpio-hog;
- gpios = <5 GPIO_ACTIVE_LOW>;
- input;
- line-name = "usb3-current-limit";
- };
- usb3_power {
- gpio-hog;
- gpios = <6 GPIO_ACTIVE_HIGH>;
- output-high;
- line-name = "usb3-power";
- };
- m2_devslp {
- gpio-hog;
- gpios = <11 GPIO_ACTIVE_HIGH>;
- output-low;
- line-name = "m.2 devslp";
- };
- };
-
- /* The MCP3021 is 100kHz clock only */
- mikrobus_adc: mcp3021@4c {
- compatible = "microchip,mcp3021";
- reg = <0x4c>;
- };
-
- /* Also something at 0x64 */
- };
-
- i2c@11100 {
- /*
- * Routed to SFP, mikrobus, and PCIe.
- * SFP limits this to 100kHz, and requires
- * an AT24C01A/02/04 with address pins tied
- * low, which takes addresses 0x50 and 0x51.
- * Mikrobus doesn't specify beyond an I2C
- * bus being present.
- * PCIe uses ARP to assign addresses, or
- * 0x63-0x64.
- */
- clock-frequency = <100000>;
- pinctrl-0 = <&clearfog_i2c1_pins>;
- pinctrl-names = "default";
- status = "okay";
- };
-
- mdio@72004 {
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
-
- phy_dedicated: ethernet-phy@0 {
- /*
- * Annoyingly, the marvell phy driver
- * configures the LED register, rather
- * than preserving reset-loaded setting.
- * We undo that rubbish here.
- */
- marvell,reg-init = <3 16 0 0x101e>;
- reg = <0>;
- };
- };
-
- pinctrl@18000 {
- clearfog_dsa0_clk_pins: clearfog-dsa0-clk-pins {
- marvell,pins = "mpp46";
- marvell,function = "ref";
- };
- clearfog_dsa0_pins: clearfog-dsa0-pins {
- marvell,pins = "mpp23", "mpp41";
- marvell,function = "gpio";
- };
- clearfog_i2c1_pins: i2c1-pins {
- /* SFP, PCIe, mSATA, mikrobus */
- marvell,pins = "mpp26", "mpp27";
- marvell,function = "i2c1";
- };
- clearfog_sdhci_cd_pins: clearfog-sdhci-cd-pins {
- marvell,pins = "mpp20";
- marvell,function = "gpio";
- };
- clearfog_sdhci_pins: clearfog-sdhci-pins {
- marvell,pins = "mpp21", "mpp28",
- "mpp37", "mpp38",
- "mpp39", "mpp40";
- marvell,function = "sd0";
- };
- clearfog_spi1_cs_pins: spi1-cs-pins {
- marvell,pins = "mpp55";
- marvell,function = "spi1";
- };
- mikro_pins: mikro-pins {
- /* int: mpp22 rst: mpp29 */
- marvell,pins = "mpp22", "mpp29";
- marvell,function = "gpio";
- };
- mikro_spi_pins: mikro-spi-pins {
- marvell,pins = "mpp43";
- marvell,function = "spi1";
- };
- mikro_uart_pins: mikro-uart-pins {
- marvell,pins = "mpp24", "mpp25";
- marvell,function = "ua1";
- };
- rear_button_pins: rear-button-pins {
- marvell,pins = "mpp34";
- marvell,function = "gpio";
- };
- };
-
rtc@a3800 {
/*
* If the rtc doesn't work, run "date reset"
@@ -311,7 +103,7 @@
bus-width = <4>;
cd-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
no-1-8-v;
- pinctrl-0 = <&clearfog_sdhci_pins
+ pinctrl-0 = <&microsom_sdhci_pins
&clearfog_sdhci_cd_pins>;
pinctrl-names = "default";
status = "okay";
@@ -319,13 +111,6 @@
wp-inverted;
};
- serial@12000 {
- pinctrl-0 = <&uart0_pins>;
- pinctrl-names = "default";
- status = "okay";
- u-boot,dm-pre-reloc;
- };
-
serial@12100 {
/* mikrobus uart */
pinctrl-0 = <&mikro_uart_pins>;
@@ -342,17 +127,10 @@
pinctrl-0 = <&spi1_pins &clearfog_spi1_cs_pins &mikro_spi_pins>;
pinctrl-names = "default";
status = "okay";
-
- spi-flash@0 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "w25q32", "jedec,spi-nor", "spi-flash";
- reg = <0>; /* Chip select 0 */
- spi-max-frequency = <3000000>;
- };
};
- usb3@f8000 {
+ usb0: usb3@f8000 {
+ /* CON7, USB-A port on back of device */
status = "okay";
};
};
@@ -376,72 +154,6 @@
};
};
- sfp: sfp {
- compatible = "sff,sfp";
- i2c-bus = <&i2c1>;
- los-gpio = <&expander0 12 GPIO_ACTIVE_HIGH>;
- moddef0-gpio = <&expander0 15 GPIO_ACTIVE_LOW>;
- sfp,ethernet = <&eth2>;
- tx-disable-gpio = <&expander0 14 GPIO_ACTIVE_HIGH>;
- tx-fault-gpio = <&expander0 13 GPIO_ACTIVE_HIGH>;
- };
-
- dsa@0 {
- compatible = "marvell,dsa";
- dsa,ethernet = <&eth1>;
- dsa,mii-bus = <&mdio>;
- pinctrl-0 = <&clearfog_dsa0_clk_pins &clearfog_dsa0_pins>;
- pinctrl-names = "default";
- #address-cells = <2>;
- #size-cells = <0>;
-
- switch@0 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <4 0>;
-
- port@0 {
- reg = <0>;
- label = "lan1";
- };
-
- port@1 {
- reg = <1>;
- label = "lan2";
- };
-
- port@2 {
- reg = <2>;
- label = "lan3";
- };
-
- port@3 {
- reg = <3>;
- label = "lan4";
- };
-
- port@4 {
- reg = <4>;
- label = "lan5";
- };
-
- port@5 {
- reg = <5>;
- label = "cpu";
- };
-
- port@6 {
- /* 88E1512 external phy */
- reg = <6>;
- label = "lan6";
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
- };
- };
-
gpio-keys {
compatible = "gpio-keys";
pinctrl-0 = <&rear_button_pins>;
@@ -457,6 +169,159 @@
};
};
+&w25q32 {
+ status = "okay";
+};
+
+&eth1 {
+ managed = "in-band-status";
+ phy-mode = "sgmii";
+ status = "okay";
+};
+
+&eth2 {
+ phy-mode = "sgmii";
+ status = "okay";
+};
+
+&i2c0 {
+ clock-frequency = <400000>;
+ pinctrl-0 = <&i2c0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ /*
+ * PCA9655 GPIO expander, up to 1MHz clock.
+ * 0-CON3 CLKREQ#
+ * 1-CON3 PERST#
+ * 2-CON2 PERST#
+ * 3-CON3 W_DISABLE
+ * 4-CON2 CLKREQ#
+ * 5-USB3 overcurrent
+ * 6-USB3 power
+ * 7-CON2 W_DISABLE
+ * 8-JP4 P1
+ * 9-JP4 P4
+ * 10-JP4 P5
+ * 11-m.2 DEVSLP
+ * 12-SFP_LOS
+ * 13-SFP_TX_FAULT
+ * 14-SFP_TX_DISABLE
+ * 15-SFP_MOD_DEF0
+ */
+ expander0: gpio-expander@20 {
+ /*
+ * This is how it should be:
+ * compatible = "onnn,pca9655",
+ * "nxp,pca9555";
+ * but you can't do this because of
+ * the way I2C works.
+ */
+ compatible = "nxp,pca9555";
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x20>;
+
+ pcie1_0_clkreq {
+ gpio-hog;
+ gpios = <0 GPIO_ACTIVE_LOW>;
+ input;
+ line-name = "pcie1.0-clkreq";
+ };
+ pcie1_0_w_disable {
+ gpio-hog;
+ gpios = <3 GPIO_ACTIVE_LOW>;
+ output-low;
+ line-name = "pcie1.0-w-disable";
+ };
+ pcie2_0_clkreq {
+ gpio-hog;
+ gpios = <4 GPIO_ACTIVE_LOW>;
+ input;
+ line-name = "pcie2.0-clkreq";
+ };
+ pcie2_0_w_disable {
+ gpio-hog;
+ gpios = <7 GPIO_ACTIVE_LOW>;
+ output-low;
+ line-name = "pcie2.0-w-disable";
+ };
+ usb3_ilimit {
+ gpio-hog;
+ gpios = <5 GPIO_ACTIVE_LOW>;
+ input;
+ line-name = "usb3-current-limit";
+ };
+ usb3_power {
+ gpio-hog;
+ gpios = <6 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "usb3-power";
+ };
+ m2_devslp {
+ gpio-hog;
+ gpios = <11 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "m.2 devslp";
+ };
+ };
+
+ mikrobus_adc: mcp3021@4c {
+ compatible = "microchip,mcp3021";
+ reg = <0x4c>;
+ };
+};
+
+&i2c1 {
+ /*
+ * Routed to SFP, mikrobus, and PCIe.
+ * SFP limits this to 100kHz, and requires
+ * an AT24C01A/02/04 with address pins tied
+ * low, which takes addresses 0x50 and 0x51.
+ * Mikrobus doesn't specify beyond an I2C
+ * bus being present.
+ * PCIe uses ARP to assign addresses, or
+ * 0x63-0x64.
+ */
+ clock-frequency = <100000>;
+ pinctrl-0 = <&clearfog_i2c1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&pinctrl {
+ clearfog_i2c1_pins: i2c1-pins {
+ /* SFP, PCIe, mSATA, mikrobus */
+ marvell,pins = "mpp26", "mpp27";
+ marvell,function = "i2c1";
+ };
+ clearfog_sdhci_cd_pins: clearfog-sdhci-cd-pins {
+ marvell,pins = "mpp20";
+ marvell,function = "gpio";
+ };
+ clearfog_spi1_cs_pins: spi1-cs-pins {
+ marvell,pins = "mpp55";
+ marvell,function = "spi1";
+ };
+ mikro_pins: mikro-pins {
+ /* int: mpp22 rst: mpp29 */
+ marvell,pins = "mpp22", "mpp29";
+ marvell,function = "gpio";
+ };
+ mikro_spi_pins: mikro-spi-pins {
+ marvell,pins = "mpp43";
+ marvell,function = "spi1";
+ };
+ mikro_uart_pins: mikro-uart-pins {
+ marvell,pins = "mpp24", "mpp25";
+ marvell,function = "ua1";
+ };
+ rear_button_pins: rear-button-pins {
+ marvell,pins = "mpp34";
+ marvell,function = "gpio";
+ };
+};
+
/*
+#define A38x_CUSTOMER_BOARD_1_MPP16_23 0x00400011
MPP18: gpio ? (pca9655 int?)
diff --git a/arch/arm/dts/armada-388-helios4.dts b/arch/arm/dts/armada-388-helios4.dts
index 049d322964..a154e0f4f4 100644
--- a/arch/arm/dts/armada-388-helios4.dts
+++ b/arch/arm/dts/armada-388-helios4.dts
@@ -248,7 +248,7 @@
bus-width = <4>;
cd-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
no-1-8-v;
- pinctrl-0 = <&helios_sdhci_pins
+ pinctrl-0 = <&microsom_sdhci_pins
&helios_sdhci_cd_pins>;
pinctrl-names = "default";
status = "okay";
@@ -286,12 +286,6 @@
marvell,pins = "mpp20";
marvell,function = "gpio";
};
- helios_sdhci_pins: helios-sdhci-pins {
- marvell,pins = "mpp21", "mpp28",
- "mpp37", "mpp38",
- "mpp39", "mpp40";
- marvell,function = "sd0";
- };
helios_led_pins: helios-led-pins {
marvell,pins = "mpp24", "mpp25",
"mpp49", "mpp50",
diff --git a/arch/arm/dts/armada-38x-solidrun-microsom.dtsi b/arch/arm/dts/armada-38x-solidrun-microsom.dtsi
index a2627223ce..74f58de85c 100644
--- a/arch/arm/dts/armada-38x-solidrun-microsom.dtsi
+++ b/arch/arm/dts/armada-38x-solidrun-microsom.dtsi
@@ -86,7 +86,7 @@
w25q32: spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
- compatible = "w25q32", "jedec,spi-nor";
+ compatible = "w25q32", "jedec,spi-nor", "spi-flash";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <3000000>;
status = "disabled";
diff --git a/arch/arm/dts/avnet-ultra96-rev1.dts b/arch/arm/dts/avnet-ultra96-rev1.dts
new file mode 100644
index 0000000000..88aa06fa78
--- /dev/null
+++ b/arch/arm/dts/avnet-ultra96-rev1.dts
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Avnet Ultra96 rev1
+ *
+ * (C) Copyright 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp-zcu100-revC.dts"
+
+/ {
+ model = "Avnet Ultra96 Rev1";
+ compatible = "avnet,ultra96-rev1", "avnet,ultra96",
+ "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100",
+ "xlnx,zynqmp";
+};
diff --git a/arch/arm/dts/exynos4210-pinctrl-uboot.dtsi b/arch/arm/dts/exynos4210-pinctrl-uboot.dtsi
index ba0fd4d2cd..aeeecd6283 100644
--- a/arch/arm/dts/exynos4210-pinctrl-uboot.dtsi
+++ b/arch/arm/dts/exynos4210-pinctrl-uboot.dtsi
@@ -7,8 +7,6 @@
/{
pinctrl_0: pinctrl@11400000 {
- #address-cells = <1>;
- #size-cells = <1>;
compatible = "samsung,exynos4210-pinctrl";
};
@@ -21,8 +19,6 @@
};
pinctrl_2: pinctrl@03860000 {
- #address-cells = <1>;
- #size-cells = <1>;
};
};
diff --git a/arch/arm/dts/exynos4210-universal_c210.dts b/arch/arm/dts/exynos4210-universal_c210.dts
index 59ea5a633e..610a8ad2e7 100644
--- a/arch/arm/dts/exynos4210-universal_c210.dts
+++ b/arch/arm/dts/exynos4210-universal_c210.dts
@@ -25,8 +25,6 @@
gpio-mosi = <&gpy3 3 0>;
gpio-miso = <&gpy3 0 0>;
spi-delay-us = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
cs@0 {
};
};
diff --git a/arch/arm/dts/exynos4x12-pinctrl-uboot.dtsi b/arch/arm/dts/exynos4x12-pinctrl-uboot.dtsi
index 7409e76a59..955e14ef8f 100644
--- a/arch/arm/dts/exynos4x12-pinctrl-uboot.dtsi
+++ b/arch/arm/dts/exynos4x12-pinctrl-uboot.dtsi
@@ -32,13 +32,9 @@
};
pinctrl_2: pinctrl@03860000 {
- #address-cells = <1>;
- #size-cells = <1>;
};
pinctrl_3: pinctrl@106E0000 {
- #address-cells = <1>;
- #size-cells = <1>;
};
};
diff --git a/arch/arm/dts/exynos5.dtsi b/arch/arm/dts/exynos5.dtsi
index 6102978aa4..cdc965d90d 100644
--- a/arch/arm/dts/exynos5.dtsi
+++ b/arch/arm/dts/exynos5.dtsi
@@ -147,8 +147,6 @@
dp: dp@145b0000 {
compatible = "samsung,exynos5-dp";
reg = <0x145b0000 0x1000>;
- #address-cells = <1>;
- #size-cells = <1>;
};
xhci0: xhci@12000000 {
diff --git a/arch/arm/dts/exynos5250-pinctrl-uboot.dtsi b/arch/arm/dts/exynos5250-pinctrl-uboot.dtsi
index f19ce47b41..b414805319 100644
--- a/arch/arm/dts/exynos5250-pinctrl-uboot.dtsi
+++ b/arch/arm/dts/exynos5250-pinctrl-uboot.dtsi
@@ -18,8 +18,6 @@
};
pinctrl_1: pinctrl@13400000 {
- #address-cells = <1>;
- #size-cells = <1>;
};
pinctrl_2: pinctrl@10d10000 {
@@ -34,8 +32,6 @@
};
pinctrl_3: pinctrl@03860000 {
- #address-cells = <1>;
- #size-cells = <1>;
};
};
diff --git a/arch/arm/dts/exynos5250-spring.dts b/arch/arm/dts/exynos5250-spring.dts
index b73b572e62..7633d36874 100644
--- a/arch/arm/dts/exynos5250-spring.dts
+++ b/arch/arm/dts/exynos5250-spring.dts
@@ -31,7 +31,7 @@
spi2 = "/spi@12d40000";
spi3 = "/spi@131a0000";
spi4 = "/spi@131b0000";
- mmc0 = "/mmc@12000000";
+ mmc0 = "/mmc@12200000";
serial0 = "/serial@12C30000";
console = "/serial@12C30000";
i2s = "/sound@3830000";
diff --git a/arch/arm/dts/exynos54xx-pinctrl-uboot.dtsi b/arch/arm/dts/exynos54xx-pinctrl-uboot.dtsi
index 7265387639..4fcbe71fe5 100644
--- a/arch/arm/dts/exynos54xx-pinctrl-uboot.dtsi
+++ b/arch/arm/dts/exynos54xx-pinctrl-uboot.dtsi
@@ -12,8 +12,6 @@
* numbers are not needed in U-Boot for exynos.
*/
pinctrl@14010000 {
- #address-cells = <1>;
- #size-cells = <1>;
};
pinctrl@13400000 {
#address-cells = <1>;
@@ -26,16 +24,10 @@
};
};
pinctrl@13410000 {
- #address-cells = <1>;
- #size-cells = <1>;
};
pinctrl@14000000 {
- #address-cells = <1>;
- #size-cells = <1>;
};
pinctrl@03860000 {
- #address-cells = <1>;
- #size-cells = <1>;
};
};
diff --git a/arch/arm/dts/kirkwood-atl-sbx81lifxcat.dts b/arch/arm/dts/kirkwood-atl-sbx81lifxcat.dts
new file mode 100644
index 0000000000..c234449936
--- /dev/null
+++ b/arch/arm/dts/kirkwood-atl-sbx81lifxcat.dts
@@ -0,0 +1,145 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "kirkwood.dtsi"
+#include "kirkwood-98dx4122.dtsi"
+
+/ {
+ model = "Allied Telesis SBx81LIFXCAT Board";
+ compatible = "atl,SBx8LIFXCAT", "marvell,kirkwood-98DX4122",
+ "marvell,kirkwood";
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x08000000>; /* 128 MB */
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,115200n8 earlyprintk";
+ stdout-path = &uart0;
+ };
+
+ aliases {
+ ethernet0 = &eth0;
+ i2c0 = &i2c0;
+ spi0 = &spi0;
+ };
+
+ dsa {
+ compatible = "marvell,dsa";
+ #address-cells = <2>;
+ #size-cells = <0>;
+ dsa,ethernet = <&eth0>;
+ dsa,mii-bus = <&mdio>;
+ status = "okay";
+
+ switch@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1 0>;
+
+ port@0 {
+ reg = <0>;
+ label = "internal0";
+ };
+ port@1 {
+ reg = <1>;
+ label = "internal1";
+ };
+ port@8 {
+ reg = <8>;
+ label = "internal8";
+ phy-mode = "rgmii-id";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ port@9 {
+ reg = <9>;
+ label = "internal9";
+ phy-mode = "rgmii-id";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ port@10 {
+ reg = <10>;
+ label = "cpu";
+ };
+ };
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ ledn {
+ label = "status:ledn";
+ gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
+ };
+
+ ledp {
+ label = "status:ledp";
+ gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
+
+&spi0 {
+ status = "okay";
+
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,m25p128", "jedec,spi-nor", "spi-flash";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+ mode = <0>;
+
+ partition@u-boot {
+ reg = <0x00000000 0x00c00000>;
+ label = "u-boot";
+ };
+ partition@u-boot-env {
+ reg = <0x00c00000 0x00040000>;
+ label = "u-boot-env";
+ };
+ partition@unused {
+ reg = <0x00100000 0x00f00000>;
+ label = "unused";
+ };
+ };
+};
+
+&i2c0 {
+ status = "okay";
+
+ eeprom@52 {
+ compatible = "atmel,24c04";
+ reg = <0x52>;
+ };
+
+ gpio3: gpio@76 {
+ #gpio-cells = <2>;
+ compatible = "nxp,pca9539";
+ reg = <0x76>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&mdio {
+ status = "okay";
+};
+
+&eth0 {
+ status = "okay";
+
+ ethernet0-port@0 {
+ speed = <1000>;
+ duplex = <1>;
+ };
+};
diff --git a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
index 39a0ebce90..4898483e1d 100644
--- a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
@@ -13,6 +13,30 @@
mmc1 = &sdmmc2;
i2c3 = &i2c4;
};
+
+ led {
+ compatible = "gpio-leds";
+
+ red {
+ label = "stm32mp:red:status";
+ gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ green {
+ label = "stm32mp:green:user";
+ gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
+ default-state = "on";
+ };
+ orange {
+ label = "stm32mp:orange:status";
+ gpios = <&gpioh 7 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ blue {
+ label = "stm32mp:blue:user";
+ gpios = <&gpiod 11 GPIO_ACTIVE_HIGH>;
+ };
+ };
};
&uart4_pins_a {
diff --git a/arch/arm/dts/zynq-cse-nand.dts b/arch/arm/dts/zynq-cse-nand.dts
index 9b1dd19a85..1e16d7fab9 100644
--- a/arch/arm/dts/zynq-cse-nand.dts
+++ b/arch/arm/dts/zynq-cse-nand.dts
@@ -38,7 +38,7 @@
#size-cells = <1>;
ranges;
- slcr: slcr@f8000000 {
+ slcr: slcr@f8000000 {
u-boot,dm-pre-reloc;
#address-cells = <1>;
#size-cells = <1>;
@@ -72,7 +72,6 @@
};
};
};
-
};
&dcc {
diff --git a/arch/arm/dts/zynq-cse-nor.dts b/arch/arm/dts/zynq-cse-nor.dts
index ba6f9a1a79..9710abadcf 100644
--- a/arch/arm/dts/zynq-cse-nor.dts
+++ b/arch/arm/dts/zynq-cse-nor.dts
@@ -56,7 +56,6 @@
clkc: clkc@100 {
#clock-cells = <1>;
compatible = "xlnx,ps7-clkc";
- fclk-enable = <0xf>;
clock-output-names = "armpll", "ddrpll",
"iopll", "cpu_6or4x",
"cpu_3or2x", "cpu_2x", "cpu_1x",
@@ -80,7 +79,6 @@
};
};
};
-
};
&dcc {
diff --git a/arch/arm/dts/zynq-zed.dts b/arch/arm/dts/zynq-zed.dts
index 24eccf1633..9c505fb7b8 100644
--- a/arch/arm/dts/zynq-zed.dts
+++ b/arch/arm/dts/zynq-zed.dts
@@ -51,6 +51,13 @@
&qspi {
u-boot,dm-pre-reloc;
status = "okay";
+ num-cs = <1>;
+ flash@0 {
+ compatible = "spansion,s25fl256s", "spi-flash";
+ reg = <0>;
+ spi-max-frequency = <30000000>;
+ m25p,fast-read;
+ };
};
&sdhci0 {
diff --git a/arch/arm/dts/zynq-zybo-z7.dts b/arch/arm/dts/zynq-zybo-z7.dts
new file mode 100644
index 0000000000..3f8a3bfa0f
--- /dev/null
+++ b/arch/arm/dts/zynq-zybo-z7.dts
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2011 - 2015 Xilinx
+ * Copyright (C) 2012 National Instruments Corp.
+ */
+/dts-v1/;
+#include "zynq-7000.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "Digilent Zybo Z7 board";
+ compatible = "digilent,zynq-zybo-z7", "xlnx,zynq-7000";
+
+ aliases {
+ ethernet0 = &gem0;
+ serial0 = &uart1;
+ spi0 = &qspi;
+ mmc0 = &sdhci0;
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x40000000>;
+ };
+
+ chosen {
+ bootargs = "";
+ stdout-path = "serial0:115200n8";
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ ld4 {
+ label = "zynq-zybo-z7:green:ld4";
+ gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ usb_phy0: phy0 {
+ #phy-cells = <0>;
+ compatible = "usb-nop-xceiv";
+ reset-gpios = <&gpio0 46 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&clkc {
+ ps-clk-frequency = <33333333>;
+};
+
+&gem0 {
+ status = "okay";
+ phy-mode = "rgmii-id";
+ phy-handle = <&ethernet_phy>;
+
+ ethernet_phy: ethernet-phy@0 {
+ reg = <0>;
+ device_type = "ethernet-phy";
+ };
+};
+
+&qspi {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&sdhci0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&uart1 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+ dr_mode = "host";
+ usb-phy = <&usb_phy0>;
+};
diff --git a/arch/arm/dts/zynqmp-mini-emmc1.dts b/arch/arm/dts/zynqmp-mini-emmc1.dts
index d1549b6dc6..530ab3cdc2 100644
--- a/arch/arm/dts/zynqmp-mini-emmc1.dts
+++ b/arch/arm/dts/zynqmp-mini-emmc1.dts
@@ -52,7 +52,8 @@
compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
status = "disabled";
reg = <0x0 0xff170000 0x0 0x1000>;
- clock-names = "clk_xin", "clk_xin";
+ clock-names = "clk_xin", "clk_ahb";
+ clocks = <&clk_xin &clk_xin>;
xlnx,device_id = <1>;
};
};
generated by cgit (git 2.34.1) at 2025-01-16 14:20:54 +0000