summaryrefslogtreecommitdiff
path: root/arch/arm/dts
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/dts')
-rw-r--r--arch/arm/dts/Makefile2
-rw-r--r--arch/arm/dts/am33xx.dtsi6
-rw-r--r--arch/arm/dts/sama5d2.dtsi28
-rw-r--r--arch/arm/dts/uniphier-ld20.dtsi1
-rw-r--r--arch/arm/dts/uniphier-pro4.dtsi2
-rw-r--r--arch/arm/dts/uniphier-pro5.dtsi2
-rw-r--r--arch/arm/dts/uniphier-pxs2.dtsi2
-rw-r--r--arch/arm/dts/uniphier-sld3-ref.dts100
-rw-r--r--arch/arm/dts/uniphier-sld3.dtsi458
9 files changed, 35 insertions, 566 deletions
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index d07715fc4f..762429c463 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -119,8 +119,6 @@ dtb-$(CONFIG_ARCH_UNIPHIER_PXS2) += \
uniphier-pxs2-vodka.dtb
dtb-$(CONFIG_ARCH_UNIPHIER_PXS3) += \
uniphier-pxs3-ref.dtb
-dtb-$(CONFIG_ARCH_UNIPHIER_SLD3) += \
- uniphier-sld3-ref.dtb
dtb-$(CONFIG_ARCH_UNIPHIER_SLD8) += \
uniphier-sld8-ref.dtb
diff --git a/arch/arm/dts/am33xx.dtsi b/arch/arm/dts/am33xx.dtsi
index b26e21bd7f..14caee7f0d 100644
--- a/arch/arm/dts/am33xx.dtsi
+++ b/arch/arm/dts/am33xx.dtsi
@@ -315,7 +315,6 @@
&edma 25>;
dma-names = "tx", "rx";
interrupts = <64>;
- interrupt-parent = <&intc>;
reg = <0x48060000 0x1000>;
status = "disabled";
};
@@ -328,7 +327,6 @@
&edma 3>;
dma-names = "tx", "rx";
interrupts = <28>;
- interrupt-parent = <&intc>;
reg = <0x481d8000 0x1000>;
status = "disabled";
};
@@ -338,7 +336,6 @@
ti,hwmods = "mmc3";
ti,needs-special-reset;
interrupts = <29>;
- interrupt-parent = <&intc>;
reg = <0x47810000 0x1000>;
status = "disabled";
};
@@ -724,7 +721,6 @@
0x4a101200 0x100>;
#address-cells = <1>;
#size-cells = <1>;
- interrupt-parent = <&intc>;
/*
* c0_rx_thresh_pend
* c0_rx_pend
@@ -787,7 +783,6 @@
lcdc: lcdc@4830e000 {
compatible = "ti,am33xx-tilcdc";
reg = <0x4830e000 0x1000>;
- interrupt-parent = <&intc>;
interrupts = <36>;
ti,hwmods = "lcdc";
status = "disabled";
@@ -796,7 +791,6 @@
tscadc: tscadc@44e0d000 {
compatible = "ti,am3359-tscadc";
reg = <0x44e0d000 0x1000>;
- interrupt-parent = <&intc>;
interrupts = <16>;
ti,hwmods = "adc_tsc";
status = "disabled";
diff --git a/arch/arm/dts/sama5d2.dtsi b/arch/arm/dts/sama5d2.dtsi
index 8d89b83b53..d8a65145d6 100644
--- a/arch/arm/dts/sama5d2.dtsi
+++ b/arch/arm/dts/sama5d2.dtsi
@@ -632,6 +632,34 @@
status = "disabled";
};
+ rstc@f8048000 {
+ compatible = "atmel,sama5d3-rstc";
+ reg = <0xf8048000 0x10>;
+ clocks = <&clk32k>;
+ };
+
+ shdwc@f8048010 {
+ compatible = "atmel,sama5d2-shdwc";
+ reg = <0xf8048010 0x10>;
+ clocks = <&clk32k>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ atmel,wakeup-rtc-timer;
+ };
+
+ pit: timer@f8048030 {
+ compatible = "atmel,at91sam9260-pit";
+ reg = <0xf8048030 0x10>;
+ clocks = <&h32ck>;
+ };
+
+ watchdog@f8048040 {
+ compatible = "atmel,sama5d4-wdt";
+ reg = <0xf8048040 0x10>;
+ clocks = <&clk32k>;
+ status = "disabled";
+ };
+
sckc@f8048050 {
compatible = "atmel,at91sam9x5-sckc";
reg = <0xf8048050 0x4>;
diff --git a/arch/arm/dts/uniphier-ld20.dtsi b/arch/arm/dts/uniphier-ld20.dtsi
index 927340fa48..44257aff35 100644
--- a/arch/arm/dts/uniphier-ld20.dtsi
+++ b/arch/arm/dts/uniphier-ld20.dtsi
@@ -426,6 +426,7 @@
compatible = "snps,dwc3";
reg = <0x65a00000 0x10000>;
interrupts = <0 134 4>;
+ dr_mode = "host";
tx-fifo-resize;
};
};
diff --git a/arch/arm/dts/uniphier-pro4.dtsi b/arch/arm/dts/uniphier-pro4.dtsi
index 60287c478f..cbb848207c 100644
--- a/arch/arm/dts/uniphier-pro4.dtsi
+++ b/arch/arm/dts/uniphier-pro4.dtsi
@@ -587,6 +587,7 @@
compatible = "snps,dwc3";
reg = <0x65a00000 0x10000>;
interrupts = <0 134 4>;
+ dr_mode = "host";
tx-fifo-resize;
};
};
@@ -604,6 +605,7 @@
compatible = "snps,dwc3";
reg = <0x65c00000 0x10000>;
interrupts = <0 137 4>;
+ dr_mode = "host";
tx-fifo-resize;
};
};
diff --git a/arch/arm/dts/uniphier-pro5.dtsi b/arch/arm/dts/uniphier-pro5.dtsi
index a29597ae88..498354c45f 100644
--- a/arch/arm/dts/uniphier-pro5.dtsi
+++ b/arch/arm/dts/uniphier-pro5.dtsi
@@ -598,6 +598,7 @@
compatible = "snps,dwc3";
reg = <0x65a00000 0x10000>;
interrupts = <0 134 4>;
+ dr_mode = "host";
tx-fifo-resize;
};
};
@@ -615,6 +616,7 @@
compatible = "snps,dwc3";
reg = <0x65c00000 0x10000>;
interrupts = <0 137 4>;
+ dr_mode = "host";
tx-fifo-resize;
};
};
diff --git a/arch/arm/dts/uniphier-pxs2.dtsi b/arch/arm/dts/uniphier-pxs2.dtsi
index 2962cb5ae7..32844f781f 100644
--- a/arch/arm/dts/uniphier-pxs2.dtsi
+++ b/arch/arm/dts/uniphier-pxs2.dtsi
@@ -610,6 +610,7 @@
compatible = "snps,dwc3";
reg = <0x65a00000 0x10000>;
interrupts = <0 134 4>;
+ dr_mode = "host";
tx-fifo-resize;
};
};
@@ -627,6 +628,7 @@
compatible = "snps,dwc3";
reg = <0x65c00000 0x10000>;
interrupts = <0 137 4>;
+ dr_mode = "host";
tx-fifo-resize;
};
};
diff --git a/arch/arm/dts/uniphier-sld3-ref.dts b/arch/arm/dts/uniphier-sld3-ref.dts
deleted file mode 100644
index baf706976a..0000000000
--- a/arch/arm/dts/uniphier-sld3-ref.dts
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * Device Tree Source for UniPhier sLD3 Reference Board
- *
- * Copyright (C) 2015-2016 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
-
-/dts-v1/;
-/include/ "uniphier-sld3.dtsi"
-/include/ "uniphier-ref-daughter.dtsi"
-/include/ "uniphier-support-card.dtsi"
-
-/ {
- model = "UniPhier sLD3 Reference Board";
- compatible = "socionext,uniphier-sld3-ref", "socionext,uniphier-sld3";
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- aliases {
- serial0 = &serial0;
- serial1 = &serial1;
- serial2 = &serial2;
- i2c0 = &i2c0;
- i2c1 = &i2c1;
- i2c2 = &i2c2;
- i2c3 = &i2c3;
- i2c4 = &i2c4;
- };
-
- memory@8000000 {
- device_type = "memory";
- reg = <0x80000000 0x20000000
- 0xc0000000 0x20000000>;
- };
-};
-
-&ethsc {
- interrupts = <0 49 4>;
-};
-
-&serial0 {
- status = "okay";
-};
-
-&serial1 {
- status = "okay";
-};
-
-&serial2 {
- status = "okay";
-};
-
-&i2c0 {
- status = "okay";
-};
-
-&emmc {
- status = "okay";
-};
-
-&sd {
- status = "okay";
-};
-
-&usb0 {
- status = "okay";
-};
-
-&usb1 {
- status = "okay";
-};
-
-&usb2 {
- status = "okay";
-};
-
-&usb3 {
- status = "okay";
-};
-
-/* for U-Boot only */
-&serial0 {
- u-boot,dm-pre-reloc;
-};
-
-&emmc {
- u-boot,dm-pre-reloc;
-};
-
-&pinctrl_uart0 {
- u-boot,dm-pre-reloc;
-};
-
-&pinctrl_emmc {
- u-boot,dm-pre-reloc;
-};
diff --git a/arch/arm/dts/uniphier-sld3.dtsi b/arch/arm/dts/uniphier-sld3.dtsi
deleted file mode 100644
index 2bb2e029ee..0000000000
--- a/arch/arm/dts/uniphier-sld3.dtsi
+++ /dev/null
@@ -1,458 +0,0 @@
-/*
- * Device Tree Source for UniPhier sLD3 SoC
- *
- * Copyright (C) 2015-2016 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
-
-/ {
- compatible = "socionext,uniphier-sld3";
- #address-cells = <1>;
- #size-cells = <1>;
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <0>;
- enable-method = "psci";
- next-level-cache = <&l2>;
- };
-
- cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <1>;
- enable-method = "psci";
- next-level-cache = <&l2>;
- };
- };
-
- psci {
- compatible = "arm,psci-0.2";
- method = "smc";
- };
-
- clocks {
- refclk: ref {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <24576000>;
- };
-
- arm_timer_clk: arm_timer_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <50000000>;
- };
- };
-
- soc {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- interrupt-parent = <&intc>;
- u-boot,dm-pre-reloc;
-
- timer@20000200 {
- compatible = "arm,cortex-a9-global-timer";
- reg = <0x20000200 0x20>;
- interrupts = <1 11 0x304>;
- clocks = <&arm_timer_clk>;
- };
-
- timer@20000600 {
- compatible = "arm,cortex-a9-twd-timer";
- reg = <0x20000600 0x20>;
- interrupts = <1 13 0x304>;
- clocks = <&arm_timer_clk>;
- };
-
- intc: interrupt-controller@20001000 {
- compatible = "arm,cortex-a9-gic";
- #interrupt-cells = <3>;
- interrupt-controller;
- reg = <0x20001000 0x1000>,
- <0x20000100 0x100>;
- };
-
- l2: l2-cache@500c0000 {
- compatible = "socionext,uniphier-system-cache";
- reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
- <0x506c0000 0x400>;
- interrupts = <0 174 4>, <0 175 4>;
- cache-unified;
- cache-size = <(512 * 1024)>;
- cache-sets = <256>;
- cache-line-size = <128>;
- cache-level = <2>;
- };
-
- serial0: serial@54006800 {
- compatible = "socionext,uniphier-uart";
- status = "disabled";
- reg = <0x54006800 0x40>;
- interrupts = <0 33 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart0>;
- clocks = <&sys_clk 0>;
- clock-frequency = <36864000>;
- };
-
- serial1: serial@54006900 {
- compatible = "socionext,uniphier-uart";
- status = "disabled";
- reg = <0x54006900 0x40>;
- interrupts = <0 35 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1>;
- clocks = <&sys_clk 0>;
- clock-frequency = <36864000>;
- };
-
- serial2: serial@54006a00 {
- compatible = "socionext,uniphier-uart";
- status = "disabled";
- reg = <0x54006a00 0x40>;
- interrupts = <0 37 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2>;
- clocks = <&sys_clk 0>;
- clock-frequency = <36864000>;
- };
-
- port0x: gpio@55000008 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000008 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port1x: gpio@55000010 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000010 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port2x: gpio@55000018 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000018 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port3x: gpio@55000020 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000020 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port4: gpio@55000028 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000028 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port5x: gpio@55000030 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000030 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port6x: gpio@55000038 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000038 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port7x: gpio@55000040 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000040 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port8x: gpio@55000048 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000048 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port9x: gpio@55000050 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000050 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port10x: gpio@55000058 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000058 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port11x: gpio@55000060 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000060 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port12x: gpio@55000068 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000068 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port13x: gpio@55000070 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000070 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port14x: gpio@55000078 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000078 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port16x: gpio@55000088 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000088 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- i2c0: i2c@58400000 {
- compatible = "socionext,uniphier-i2c";
- status = "disabled";
- reg = <0x58400000 0x40>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 41 1>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c0>;
- clocks = <&sys_clk 1>;
- clock-frequency = <100000>;
- };
-
- i2c1: i2c@58480000 {
- compatible = "socionext,uniphier-i2c";
- status = "disabled";
- reg = <0x58480000 0x40>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 42 1>;
- clocks = <&sys_clk 1>;
- clock-frequency = <100000>;
- };
-
- i2c2: i2c@58500000 {
- compatible = "socionext,uniphier-i2c";
- status = "disabled";
- reg = <0x58500000 0x40>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 43 1>;
- clocks = <&sys_clk 1>;
- clock-frequency = <100000>;
- };
-
- i2c3: i2c@58580000 {
- compatible = "socionext,uniphier-i2c";
- status = "disabled";
- reg = <0x58580000 0x40>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 44 1>;
- clocks = <&sys_clk 1>;
- clock-frequency = <100000>;
- };
-
- /* chip-internal connection for DMD */
- i2c4: i2c@58600000 {
- compatible = "socionext,uniphier-i2c";
- reg = <0x58600000 0x40>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 45 1>;
- clocks = <&sys_clk 1>;
- clock-frequency = <400000>;
- };
-
- system_bus: system-bus@58c00000 {
- compatible = "socionext,uniphier-system-bus";
- status = "disabled";
- reg = <0x58c00000 0x400>;
- #address-cells = <2>;
- #size-cells = <1>;
- };
-
- smpctrl@59801000 {
- compatible = "socionext,uniphier-smpctrl";
- reg = <0x59801000 0x400>;
- };
-
- mioctrl@59810000 {
- compatible = "socionext,uniphier-sld3-mioctrl",
- "simple-mfd", "syscon";
- reg = <0x59810000 0x800>;
- u-boot,dm-pre-reloc;
-
- mio_clk: clock {
- compatible = "socionext,uniphier-sld3-mio-clock";
- #clock-cells = <1>;
- u-boot,dm-pre-reloc;
- };
-
- mio_rst: reset {
- compatible = "socionext,uniphier-sld3-mio-reset";
- #reset-cells = <1>;
- };
- };
-
- emmc: sdhc@5a400000 {
- compatible = "socionext,uniphier-sdhc";
- status = "disabled";
- reg = <0x5a400000 0x200>;
- interrupts = <0 78 4>;
- pinctrl-names = "default", "1.8v";
- pinctrl-0 = <&pinctrl_emmc>;
- pinctrl-1 = <&pinctrl_emmc_1v8>;
- clocks = <&mio_clk 1>;
- reset-names = "host", "bridge";
- resets = <&mio_rst 1>, <&mio_rst 4>;
- bus-width = <8>;
- non-removable;
- cap-mmc-highspeed;
- cap-mmc-hw-reset;
- };
-
- sd: sdhc@5a500000 {
- compatible = "socionext,uniphier-sdhc";
- status = "disabled";
- reg = <0x5a500000 0x200>;
- interrupts = <0 76 4>;
- pinctrl-names = "default", "1.8v";
- pinctrl-0 = <&pinctrl_sd>;
- pinctrl-1 = <&pinctrl_sd_1v8>;
- clocks = <&mio_clk 0>;
- reset-names = "host", "bridge";
- resets = <&mio_rst 0>, <&mio_rst 3>;
- bus-width = <4>;
- cap-sd-highspeed;
- sd-uhs-sdr12;
- sd-uhs-sdr25;
- sd-uhs-sdr50;
- };
-
- usb0: usb@5a800100 {
- compatible = "socionext,uniphier-ehci", "generic-ehci";
- status = "disabled";
- reg = <0x5a800100 0x100>;
- interrupts = <0 80 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb0>;
- clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
- resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
- <&mio_rst 12>;
- };
-
- usb1: usb@5a810100 {
- compatible = "socionext,uniphier-ehci", "generic-ehci";
- status = "disabled";
- reg = <0x5a810100 0x100>;
- interrupts = <0 81 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb1>;
- clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
- resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
- <&mio_rst 13>;
- };
-
- usb2: usb@5a820100 {
- compatible = "socionext,uniphier-ehci", "generic-ehci";
- status = "disabled";
- reg = <0x5a820100 0x100>;
- interrupts = <0 82 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb2>;
- clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
- resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
- <&mio_rst 14>;
- };
-
- usb3: usb@5a830100 {
- compatible = "socionext,uniphier-ehci", "generic-ehci";
- status = "disabled";
- reg = <0x5a830100 0x100>;
- interrupts = <0 83 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb3>;
- clocks = <&mio_clk 7>, <&mio_clk 11>, <&mio_clk 15>;
- resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 11>,
- <&mio_rst 15>;
- };
-
- soc-glue@5f800000 {
- compatible = "socionext,uniphier-sld3-soc-glue",
- "simple-mfd", "syscon";
- reg = <0x5f800000 0x2000>;
- u-boot,dm-pre-reloc;
-
- pinctrl: pinctrl {
- compatible = "socionext,uniphier-sld3-pinctrl";
- u-boot,dm-pre-reloc;
- };
- };
-
- aidet@f1830000 {
- compatible = "simple-mfd", "syscon";
- reg = <0xf1830000 0x200>;
- };
-
- sysctrl@f1840000 {
- compatible = "socionext,uniphier-sld3-sysctrl",
- "simple-mfd", "syscon";
- reg = <0xf1840000 0x10000>;
-
- sys_clk: clock {
- compatible = "socionext,uniphier-sld3-clock";
- #clock-cells = <1>;
- };
-
- sys_rst: reset {
- compatible = "socionext,uniphier-sld3-reset";
- #reset-cells = <1>;
- };
- };
-
- nand: nand@f8000000 {
- compatible = "socionext,uniphier-denali-nand-v5a";
- status = "disabled";
- reg-names = "nand_data", "denali_reg";
- reg = <0xf8000000 0x20>, <0xf8100000 0x1000>;
- interrupts = <0 65 4>;
- clocks = <&sys_clk 2>;
- nand-ecc-strength = <8>;
- };
- };
-};
-
-/include/ "uniphier-pinctrl.dtsi"
generated by cgit (git 2.34.1) at 2025-02-06 02:08:15 +0000