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-rw-r--r--arch/arm/imx-common/timer.c10
1 files changed, 7 insertions, 3 deletions
diff --git a/arch/arm/imx-common/timer.c b/arch/arm/imx-common/timer.c
index 1f7c671ebe..ee6eff2b28 100644
--- a/arch/arm/imx-common/timer.c
+++ b/arch/arm/imx-common/timer.c
@@ -45,7 +45,7 @@ static inline int gpt_has_clk_source_osc(void)
#if defined(CONFIG_MX6)
if (((is_mx6dq()) && (soc_rev() > CHIP_REV_1_0)) ||
is_mx6dqp() || is_mx6sdl() || is_mx6sx() || is_mx6ul() ||
- is_mx6ull())
+ is_mx6ull() || is_mx6sll())
return 1;
return 0;
@@ -84,8 +84,12 @@ int timer_init(void)
if (gpt_has_clk_source_osc()) {
i |= GPTCR_CLKSOURCE_OSC | GPTCR_TEN;
- /* For DL/S, SX, UL, ULL set 24Mhz OSC Enable bit and prescaler */
- if (is_mx6sdl() || is_mx6sx() || is_mx6ul() || is_mx6ull()) {
+ /*
+ * For DL/S, SX, UL, ULL, SLL set 24Mhz OSC
+ * Enable bit and prescaler
+ */
+ if (is_mx6sdl() || is_mx6sx() || is_mx6ul() || is_mx6ull() ||
+ is_mx6sll()) {
i |= GPTCR_24MEN;
/* Produce 3Mhz clock */