diff options
Diffstat (limited to 'arch/arm/include/asm/arch-armada100')
| -rw-r--r-- | arch/arm/include/asm/arch-armada100/armada100.h | 120 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-armada100/config.h | 1 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-armada100/cpu.h | 125 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-armada100/mfp.h | 6 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-armada100/spi.h | 95 |
5 files changed, 231 insertions, 116 deletions
diff --git a/arch/arm/include/asm/arch-armada100/armada100.h b/arch/arm/include/asm/arch-armada100/armada100.h index c449d4e639..0ed3a8ea52 100644 --- a/arch/arm/include/asm/arch-armada100/armada100.h +++ b/arch/arm/include/asm/arch-armada100/armada100.h @@ -26,13 +26,7 @@ #ifndef _ASM_ARCH_ARMADA100_H #define _ASM_ARCH_ARMADA100_H -#ifndef __ASSEMBLY__ -#include <asm/types.h> -#include <asm/io.h> -#endif /* __ASSEMBLY__ */ - #if defined (CONFIG_ARMADA100) -#include <asm/arch/cpu.h> /* Common APB clock register bit definitions */ #define APBC_APBCLK (1<<0) /* APB Bus Clock Enable */ @@ -45,6 +39,10 @@ #define FE_CLK_RST 0x1 #define FE_CLK_ENA 0x8 +/* SSP2 Clock Control */ +#define SSP2_APBCLK 0x01 +#define SSP2_FNCLK 0x02 + /* Register Base Addresses */ #define ARMD1_DRAM_BASE 0xB0000000 #define ARMD1_FEC_BASE 0xC0800000 @@ -65,115 +63,5 @@ #define ARMD1_APMU_BASE 0xD4282800 #define ARMD1_CPU_BASE 0xD4282C00 -/* - * Main Power Management (MPMU) Registers - * Refer Datasheet Appendix A.8 - */ -struct armd1mpmu_registers { - u8 pad0[0x08 - 0x00]; - u32 fccr; /*0x0008*/ - u32 pocr; /*0x000c*/ - u32 posr; /*0x0010*/ - u32 succr; /*0x0014*/ - u8 pad1[0x030 - 0x014 - 4]; - u32 gpcr; /*0x0030*/ - u8 pad2[0x200 - 0x030 - 4]; - u32 wdtpcr; /*0x0200*/ - u8 pad3[0x1000 - 0x200 - 4]; - u32 apcr; /*0x1000*/ - u32 apsr; /*0x1004*/ - u8 pad4[0x1020 - 0x1004 - 4]; - u32 aprr; /*0x1020*/ - u32 acgr; /*0x1024*/ - u32 arsr; /*0x1028*/ -}; - -/* - * Application Subsystem Power Management - * Refer Datasheet Appendix A.9 - */ -struct armd1apmu_registers { - u32 pcr; /* 0x000 */ - u32 ccr; /* 0x004 */ - u32 pad1; - u32 ccsr; /* 0x00C */ - u32 fc_timer; /* 0x010 */ - u32 pad2; - u32 ideal_cfg; /* 0x018 */ - u8 pad3[0x04C - 0x018 - 4]; - u32 lcdcrc; /* 0x04C */ - u32 cciccrc; /* 0x050 */ - u32 sd1crc; /* 0x054 */ - u32 sd2crc; /* 0x058 */ - u32 usbcrc; /* 0x05C */ - u32 nfccrc; /* 0x060 */ - u32 dmacrc; /* 0x064 */ - u32 pad4; - u32 buscrc; /* 0x06C */ - u8 pad5[0x07C - 0x06C - 4]; - u32 wake_clr; /* 0x07C */ - u8 pad6[0x090 - 0x07C - 4]; - u32 core_status; /* 0x090 */ - u32 rfsc; /* 0x094 */ - u32 imr; /* 0x098 */ - u32 irwc; /* 0x09C */ - u32 isr; /* 0x0A0 */ - u8 pad7[0x0B0 - 0x0A0 - 4]; - u32 mhst; /* 0x0B0 */ - u32 msr; /* 0x0B4 */ - u8 pad8[0x0C0 - 0x0B4 - 4]; - u32 msst; /* 0x0C0 */ - u32 pllss; /* 0x0C4 */ - u32 smb; /* 0x0C8 */ - u32 gccrc; /* 0x0CC */ - u8 pad9[0x0D4 - 0x0CC - 4]; - u32 smccrc; /* 0x0D4 */ - u32 pad10; - u32 xdcrc; /* 0x0DC */ - u32 sd3crc; /* 0x0E0 */ - u32 sd4crc; /* 0x0E4 */ - u8 pad11[0x0F0 - 0x0E4 - 4]; - u32 cfcrc; /* 0x0F0 */ - u32 mspcrc; /* 0x0F4 */ - u32 cmucrc; /* 0x0F8 */ - u32 fecrc; /* 0x0FC */ - u32 pciecrc; /* 0x100 */ - u32 epdcrc; /* 0x104 */ -}; - -/* - * APB1 Clock Reset/Control Registers - * Refer Datasheet Appendix A.10 - */ -struct armd1apb1_registers { - u32 uart1; /*0x000*/ - u32 uart2; /*0x004*/ - u32 gpio; /*0x008*/ - u32 pwm1; /*0x00c*/ - u32 pwm2; /*0x010*/ - u32 pwm3; /*0x014*/ - u32 pwm4; /*0x018*/ - u8 pad0[0x028 - 0x018 - 4]; - u32 rtc; /*0x028*/ - u32 twsi0; /*0x02c*/ - u32 kpc; /*0x030*/ - u32 timers; /*0x034*/ - u8 pad1[0x03c - 0x034 - 4]; - u32 aib; /*0x03c*/ - u32 sw_jtag; /*0x040*/ - u32 timer1; /*0x044*/ - u32 onewire; /*0x048*/ - u8 pad2[0x050 - 0x048 - 4]; - u32 asfar; /*0x050 AIB Secure First Access Reg*/ - u32 assar; /*0x054 AIB Secure Second Access Reg*/ - u8 pad3[0x06c - 0x054 - 4]; - u32 twsi1; /*0x06c*/ - u32 uart3; /*0x070*/ - u8 pad4[0x07c - 0x070 - 4]; - u32 timer2; /*0x07C*/ - u8 pad5[0x084 - 0x07c - 4]; - u32 ac97; /*0x084*/ -}; - #endif /* CONFIG_ARMADA100 */ #endif /* _ASM_ARCH_ARMADA100_H */ diff --git a/arch/arm/include/asm/arch-armada100/config.h b/arch/arm/include/asm/arch-armada100/config.h index 1126b38a27..d2094e5303 100644 --- a/arch/arm/include/asm/arch-armada100/config.h +++ b/arch/arm/include/asm/arch-armada100/config.h @@ -31,6 +31,7 @@ #ifndef _ARMD1_CONFIG_H #define _ARMD1_CONFIG_H +#include <asm/arch/armada100.h> #define CONFIG_ARM926EJS 1 /* Basic Architecture */ #define CONFIG_SYS_TCLK (14745600) /* NS16550 clk config */ diff --git a/arch/arm/include/asm/arch-armada100/cpu.h b/arch/arm/include/asm/arch-armada100/cpu.h index 0518a6a4b0..da4277327d 100644 --- a/arch/arm/include/asm/arch-armada100/cpu.h +++ b/arch/arm/include/asm/arch-armada100/cpu.h @@ -29,6 +29,131 @@ #include <asm/system.h> /* + * Main Power Management (MPMU) Registers + * Refer Datasheet Appendix A.8 + */ +struct armd1mpmu_registers { + u8 pad0[0x08 - 0x00]; + u32 fccr; /*0x0008*/ + u32 pocr; /*0x000c*/ + u32 posr; /*0x0010*/ + u32 succr; /*0x0014*/ + u8 pad1[0x030 - 0x014 - 4]; + u32 gpcr; /*0x0030*/ + u8 pad2[0x200 - 0x030 - 4]; + u32 wdtpcr; /*0x0200*/ + u8 pad3[0x1000 - 0x200 - 4]; + u32 apcr; /*0x1000*/ + u32 apsr; /*0x1004*/ + u8 pad4[0x1020 - 0x1004 - 4]; + u32 aprr; /*0x1020*/ + u32 acgr; /*0x1024*/ + u32 arsr; /*0x1028*/ +}; + +/* + * Application Subsystem Power Management + * Refer Datasheet Appendix A.9 + */ +struct armd1apmu_registers { + u32 pcr; /* 0x000 */ + u32 ccr; /* 0x004 */ + u32 pad1; + u32 ccsr; /* 0x00C */ + u32 fc_timer; /* 0x010 */ + u32 pad2; + u32 ideal_cfg; /* 0x018 */ + u8 pad3[0x04C - 0x018 - 4]; + u32 lcdcrc; /* 0x04C */ + u32 cciccrc; /* 0x050 */ + u32 sd1crc; /* 0x054 */ + u32 sd2crc; /* 0x058 */ + u32 usbcrc; /* 0x05C */ + u32 nfccrc; /* 0x060 */ + u32 dmacrc; /* 0x064 */ + u32 pad4; + u32 buscrc; /* 0x06C */ + u8 pad5[0x07C - 0x06C - 4]; + u32 wake_clr; /* 0x07C */ + u8 pad6[0x090 - 0x07C - 4]; + u32 core_status; /* 0x090 */ + u32 rfsc; /* 0x094 */ + u32 imr; /* 0x098 */ + u32 irwc; /* 0x09C */ + u32 isr; /* 0x0A0 */ + u8 pad7[0x0B0 - 0x0A0 - 4]; + u32 mhst; /* 0x0B0 */ + u32 msr; /* 0x0B4 */ + u8 pad8[0x0C0 - 0x0B4 - 4]; + u32 msst; /* 0x0C0 */ + u32 pllss; /* 0x0C4 */ + u32 smb; /* 0x0C8 */ + u32 gccrc; /* 0x0CC */ + u8 pad9[0x0D4 - 0x0CC - 4]; + u32 smccrc; /* 0x0D4 */ + u32 pad10; + u32 xdcrc; /* 0x0DC */ + u32 sd3crc; /* 0x0E0 */ + u32 sd4crc; /* 0x0E4 */ + u8 pad11[0x0F0 - 0x0E4 - 4]; + u32 cfcrc; /* 0x0F0 */ + u32 mspcrc; /* 0x0F4 */ + u32 cmucrc; /* 0x0F8 */ + u32 fecrc; /* 0x0FC */ + u32 pciecrc; /* 0x100 */ + u32 epdcrc; /* 0x104 */ +}; + +/* + * APB1 Clock Reset/Control Registers + * Refer Datasheet Appendix A.10 + */ +struct armd1apb1_registers { + u32 uart1; /*0x000*/ + u32 uart2; /*0x004*/ + u32 gpio; /*0x008*/ + u32 pwm1; /*0x00c*/ + u32 pwm2; /*0x010*/ + u32 pwm3; /*0x014*/ + u32 pwm4; /*0x018*/ + u8 pad0[0x028 - 0x018 - 4]; + u32 rtc; /*0x028*/ + u32 twsi0; /*0x02c*/ + u32 kpc; /*0x030*/ + u32 timers; /*0x034*/ + u8 pad1[0x03c - 0x034 - 4]; + u32 aib; /*0x03c*/ + u32 sw_jtag; /*0x040*/ + u32 timer1; /*0x044*/ + u32 onewire; /*0x048*/ + u8 pad2[0x050 - 0x048 - 4]; + u32 asfar; /*0x050 AIB Secure First Access Reg*/ + u32 assar; /*0x054 AIB Secure Second Access Reg*/ + u8 pad3[0x06c - 0x054 - 4]; + u32 twsi1; /*0x06c*/ + u32 uart3; /*0x070*/ + u8 pad4[0x07c - 0x070 - 4]; + u32 timer2; /*0x07C*/ + u8 pad5[0x084 - 0x07c - 4]; + u32 ac97; /*0x084*/ +}; + +/* +* APB2 Clock Reset/Control Registers +* Refer Datasheet Appendix A.11 +*/ +struct armd1apb2_registers { + u32 pad1[0x01C - 0x000]; + u32 ssp1_clkrst; /* 0x01C */ + u32 ssp2_clkrst; /* 0x020 */ + u32 pad2[0x04C - 0x020 - 4]; + u32 ssp3_clkrst; /* 0x04C */ + u32 pad3[0x058 - 0x04C - 4]; + u32 ssp4_clkrst; /* 0x058 */ + u32 ssp5_clkrst; /* 0x05C */ +}; + +/* * CPU Interface Registers * Refer Datasheet Appendix A.2 */ diff --git a/arch/arm/include/asm/arch-armada100/mfp.h b/arch/arm/include/asm/arch-armada100/mfp.h index da76b58405..d48251af20 100644 --- a/arch/arm/include/asm/arch-armada100/mfp.h +++ b/arch/arm/include/asm/arch-armada100/mfp.h @@ -83,6 +83,12 @@ #define MFP101_ETH_MDIO (MFP_REG(0x194) | MFP_AF5 | MFP_DRIVE_MEDIUM) #define MFP103_ETH_RXDV (MFP_REG(0x19C) | MFP_AF5 | MFP_DRIVE_MEDIUM) +/* SPI */ +#define MFP107_SSP2_RXD (MFP_REG(0x1AC) | MFP_AF4 | MFP_DRIVE_MEDIUM) +#define MFP108_SSP2_TXD (MFP_REG(0x1B0) | MFP_AF4 | MFP_DRIVE_MEDIUM) +#define MFP110_SSP2_CS (MFP_REG(0x1B8) | MFP_AF0 | MFP_DRIVE_MEDIUM) +#define MFP111_SSP2_CLK (MFP_REG(0x1BC) | MFP_AF4 | MFP_DRIVE_MEDIUM) + /* More macros can be defined here... */ #define MFP_PIN_MAX 117 diff --git a/arch/arm/include/asm/arch-armada100/spi.h b/arch/arm/include/asm/arch-armada100/spi.h new file mode 100644 index 0000000000..58f0d8f7f3 --- /dev/null +++ b/arch/arm/include/asm/arch-armada100/spi.h @@ -0,0 +1,95 @@ +/* + * (C) Copyright 2011 + * eInfochips Ltd. <www.einfochips.com> + * Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com> + * + * (C) Copyright 2010 + * Marvell Semiconductor <www.marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef __ARMADA100_SPI_H_ +#define __ARMADA100_SPI_H_ + +#include <asm/arch/armada100.h> + +#define CAT_BASE_ADDR(x) ARMD1_SSP ## x ## _BASE +#define SSP_REG_BASE(x) CAT_BASE_ADDR(x) + +/* + * SSP Serial Port Registers + * refer Appendix A.26 + */ +struct ssp_reg { + u32 sscr0; /* SSP Control Register 0 - 0x000 */ + u32 sscr1; /* SSP Control Register 1 - 0x004 */ + u32 sssr; /* SSP Status Register - 0x008 */ + u32 ssitr; /* SSP Interrupt Test Register - 0x00C */ + u32 ssdr; /* SSP Data Register - 0x010 */ + u32 pad1[5]; + u32 ssto; /* SSP Timeout Register - 0x028 */ + u32 sspsp; /* SSP Programmable Serial Protocol Register - 0x02C */ + u32 sstsa; /* SSP TX Timeslot Active Register - 0x030 */ + u32 ssrsa; /* SSP RX Timeslot Active Register - 0x034 */ + u32 sstss; /* SSP Timeslot Status Register - 0x038 */ +}; + +#define DEFAULT_WORD_LEN 8 +#define SSP_FLUSH_NUM 0x2000 +#define RX_THRESH_DEF 8 +#define TX_THRESH_DEF 8 +#define TIMEOUT_DEF 1000 + +#define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */ +#define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */ +#define SSCR1_LBM (1 << 2) /* Loop-Back Mode */ +#define SSCR1_SPO (1 << 3) /* Motorola SPI SSPSCLK polarity + setting */ +#define SSCR1_SPH (1 << 4) /* Motorola SPI SSPSCLK phase setting */ +#define SSCR1_MWDS (1 << 5) /* Microwire Transmit Data Size */ +#define SSCR1_TFT 0x03c0 /* Transmit FIFO Threshold (mask) */ +#define SSCR1_RFT 0x3c00 /* Receive FIFO Threshold (mask) */ + +#define SSCR1_TXTRESH(x) ((x - 1) << 6) /* level [1..16] */ +#define SSCR1_RXTRESH(x) ((x - 1) << 10) /* level [1..16] */ +#define SSCR1_TINTE (1 << 19) /* Receiver Time-out + Interrupt enable */ + +#define SSCR0_DSS 0x0f /* Data Size Select (mask) */ +#define SSCR0_DATASIZE(x) (x - 1) /* Data Size Select [4..16] */ +#define SSCR0_FRF 0x30 /* FRame Format (mask) */ +#define SSCR0_MOTO (0x0 << 4) /* Motorola's Serial + Peripheral Interface */ +#define SSCR0_TI (0x1 << 4) /* TI's Synchronous + Serial Protocol (SSP) */ +#define SSCR0_NATIONAL (0x2 << 4) /* National Microwire */ +#define SSCR0_ECS (1 << 6) /* External clock select */ +#define SSCR0_SSE (1 << 7) /* Synchronous Serial Port + Enable */ + +#define SSSR_TNF (1 << 2) /* Transmit FIFO Not Full */ +#define SSSR_RNE (1 << 3) /* Receive FIFO Not Empty */ +#define SSSR_BSY (1 << 4) /* SSP Busy */ +#define SSSR_TFS (1 << 5) /* Transmit FIFO Service Request */ +#define SSSR_RFS (1 << 6) /* Receive FIFO Service Request */ +#define SSSR_ROR (1 << 7) /* Receive FIFO Overrun */ +#define SSSR_TINT (1 << 19) /* Receiver Time-out Interrupt */ + +#endif /* __ARMADA100_SPI_H_ */ |