diff options
Diffstat (limited to 'arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h')
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index 2561ead7c3..1ff5cac344 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -23,6 +23,8 @@ #define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000) #define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00ee00b0) #define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000) +#define CONFIG_SYS_FSL_BMAN_ADDR (CONFIG_SYS_IMMR + 0x00890000) +#define CONFIG_SYS_FSL_QMAN_ADDR (CONFIG_SYS_IMMR + 0x00880000) #define CONFIG_SYS_FSL_FMAN_ADDR (CONFIG_SYS_IMMR + 0x00a00000) #define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000) #define CONFIG_SYS_FSL_DCFG_ADDR (CONFIG_SYS_IMMR + 0x00ee0000) @@ -41,6 +43,33 @@ #define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0xe90000) #define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0xe80200) +#define CONFIG_SYS_BMAN_NUM_PORTALS 10 +#define CONFIG_SYS_BMAN_MEM_BASE 0x508000000 +#define CONFIG_SYS_BMAN_MEM_PHYS (0xf00000000ull + \ + CONFIG_SYS_BMAN_MEM_BASE) +#define CONFIG_SYS_BMAN_MEM_SIZE 0x08000000 +#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x10000 +#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x10000 +#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE +#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ + CONFIG_SYS_BMAN_CENA_SIZE) +#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0x3E80 +#define CONFIG_SYS_QMAN_NUM_PORTALS 10 +#define CONFIG_SYS_QMAN_MEM_BASE 0x500000000 +#define CONFIG_SYS_QMAN_MEM_PHYS (0xf00000000ull + \ + CONFIG_SYS_QMAN_MEM_BASE) +#define CONFIG_SYS_QMAN_MEM_SIZE 0x08000000 +#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x10000 +#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x10000 +#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE +#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ + CONFIG_SYS_QMAN_CENA_SIZE) +#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0x3680 + #define CONFIG_SYS_FSL_TIMER_ADDR 0x02b00000 #define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01180000) |