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Diffstat (limited to 'arch/arm/include/asm/arch-fsl-layerscape')
-rw-r--r--arch/arm/include/asm/arch-fsl-layerscape/config.h16
-rw-r--r--arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h8
-rw-r--r--arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h2
-rw-r--r--arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h9
-rw-r--r--arch/arm/include/asm/arch-fsl-layerscape/ns_access.h1
-rw-r--r--arch/arm/include/asm/arch-fsl-layerscape/soc.h4
6 files changed, 27 insertions, 13 deletions
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 527998111f..a5c6c4cd26 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -7,15 +7,18 @@
#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_
#define _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_
+#include <linux/kconfig.h>
#include <fsl_ddrc_version.h>
+#define CONFIG_STANDALONE_LOAD_ADDR 0x80300000
+
#ifdef CONFIG_SYS_FSL_DDR4
#define CONFIG_SYS_FSL_DDRC_GEN4
#else
#define CONFIG_SYS_FSL_DDRC_ARM_GEN3 /* Enable Freescale ARM DDR3 driver */
#endif
-#ifndef CONFIG_LS1012A
+#ifndef CONFIG_ARCH_LS1012A
#define CONFIG_SYS_FSL_DDR /* Freescale DDR driver */
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
#endif
@@ -165,6 +168,7 @@
#define CONFIG_SYS_FSL_SEC_BE
#define CONFIG_SYS_FSL_SRDS_1
+
/* SoC related */
#ifdef CONFIG_LS1043A
#define CONFIG_MAX_CPUS 4
@@ -201,13 +205,13 @@
#define CONFIG_SYS_FSL_ERRATUM_A009942
#define CONFIG_SYS_FSL_ERRATUM_A009660
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
-#elif defined(CONFIG_LS1012A)
+#elif defined(CONFIG_ARCH_LS1012A)
#define CONFIG_MAX_CPUS 1
#undef CONFIG_SYS_FSL_DDRC_ARM_GEN3
#define GICD_BASE 0x01401000
#define GICC_BASE 0x01402000
-#elif defined(CONFIG_LS1046A)
+#elif defined(CONFIG_ARCH_LS1046A)
#define CONFIG_MAX_CPUS 4
#define CONFIG_SYS_FMAN_V3
#define CONFIG_SYS_NUM_FMAN 1
@@ -234,6 +238,12 @@
#define GICC_BASE 0x01420000
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
+
+#define CONFIG_SYS_FSL_ERRATUM_A008511
+#define CONFIG_SYS_FSL_ERRATUM_A009801
+#define CONFIG_SYS_FSL_ERRATUM_A009803
+#define CONFIG_SYS_FSL_ERRATUM_A009942
+#define CONFIG_SYS_FSL_ERRATUM_A010165
#else
#error SoC not defined
#endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
index e1b3f44d85..9f94b4505e 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
@@ -11,6 +11,10 @@
#ifdef CONFIG_LS2080A
enum srds_prtcl {
+ /*
+ * Nobody will check whether the device 'NONE' has been configured,
+ * So use it to indicate if the serdes_prtcl_map has been initialized.
+ */
NONE = 0,
PCIE1,
PCIE2,
@@ -57,6 +61,10 @@ enum srds {
};
#elif defined(CONFIG_FSL_LSCH2)
enum srds_prtcl {
+ /*
+ * Nobody will check whether the device 'NONE' has been configured,
+ * So use it to indicate if the serdes_prtcl_map has been initialized.
+ */
NONE = 0,
PCIE1,
PCIE2,
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 95a42935ca..df5187195d 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -60,7 +60,7 @@
#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x4800000000ULL
#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x5000000000ULL
/* LUT registers */
-#ifdef CONFIG_LS1012A
+#ifdef CONFIG_ARCH_LS1012A
#define PCIE_LUT_BASE 0xC0000
#else
#define PCIE_LUT_BASE 0x10000
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 93e26c1d7f..7acba2730a 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -33,15 +33,6 @@
#define CONFIG_SYS_FSL_WRIOP1_MDIO2 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x17000)
#define CONFIG_SYS_FSL_LSCH3_SERDES_ADDR (CONFIG_SYS_IMMR + 0xEA0000)
-/* SP (Cortex-A5) related */
-#define CONFIG_SYS_FSL_SP_ADDR (CONFIG_SYS_IMMR + 0x00F00000)
-#define CONFIG_SYS_FSL_SP_VSG_GIC_ADDR (CONFIG_SYS_FSL_SP_ADDR)
-#define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR1 (CONFIG_SYS_FSL_SP_ADDR)
-#define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR2 \
- (CONFIG_SYS_FSL_SP_ADDR + 0x0008)
-#define CONFIG_SYS_FSL_SP_LOOPBACK_DUART \
- (CONFIG_SYS_FSL_SP_ADDR + 0x1000)
-
#define CONFIG_SYS_FSL_DCSR_DDR_ADDR 0x70012c000ULL
#define CONFIG_SYS_FSL_DCSR_DDR2_ADDR 0x70012d000ULL
#define CONFIG_SYS_FSL_DCSR_DDR3_ADDR 0x700132000ULL
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
index db76066c80..f46f1d866a 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
@@ -6,6 +6,7 @@
#ifndef __FSL_NS_ACCESS_H_
#define __FSL_NS_ACCESS_H_
+#include <fsl_csu.h>
enum csu_cslx_ind {
CSU_CSLX_PCIE2_IO = 0,
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index 8d4a7adb1d..4512732f79 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -100,6 +100,10 @@ void cpu_name(char *name);
void erratum_a009635(void);
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
+void erratum_a010315(void);
+#endif
+
bool soc_has_dp_ddr(void);
bool soc_has_aiop(void);
#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */