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-rw-r--r--arch/arm/include/asm/arch-keystone/clock-k2hk.h109
-rw-r--r--arch/arm/include/asm/arch-keystone/clock.h17
-rw-r--r--arch/arm/include/asm/arch-keystone/clock_defs.h111
-rw-r--r--arch/arm/include/asm/arch-keystone/emac_defs.h240
-rw-r--r--arch/arm/include/asm/arch-keystone/emif_defs.h73
-rw-r--r--arch/arm/include/asm/arch-keystone/hardware-k2hk.h150
-rw-r--r--arch/arm/include/asm/arch-keystone/hardware.h175
-rw-r--r--arch/arm/include/asm/arch-keystone/i2c_defs.h17
-rw-r--r--arch/arm/include/asm/arch-keystone/keystone_nav.h193
-rw-r--r--arch/arm/include/asm/arch-keystone/nand_defs.h23
-rw-r--r--arch/arm/include/asm/arch-keystone/psc_defs.h90
-rw-r--r--arch/arm/include/asm/arch-keystone/spl.h12
12 files changed, 1210 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-keystone/clock-k2hk.h b/arch/arm/include/asm/arch-keystone/clock-k2hk.h
new file mode 100644
index 0000000000..6a69a8d2be
--- /dev/null
+++ b/arch/arm/include/asm/arch-keystone/clock-k2hk.h
@@ -0,0 +1,109 @@
+/*
+ * K2HK: Clock management APIs
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_CLOCK_K2HK_H
+#define __ASM_ARCH_CLOCK_K2HK_H
+
+#include <asm/arch/hardware.h>
+
+#ifndef __ASSEMBLY__
+
+enum ext_clk_e {
+ sys_clk,
+ alt_core_clk,
+ pa_clk,
+ tetris_clk,
+ ddr3a_clk,
+ ddr3b_clk,
+ mcm_clk,
+ pcie_clk,
+ sgmii_srio_clk,
+ xgmii_clk,
+ usb_clk,
+ rp1_clk,
+ ext_clk_count /* number of external clocks */
+};
+
+extern unsigned int external_clk[ext_clk_count];
+
+enum clk_e {
+ core_pll_clk,
+ pass_pll_clk,
+ tetris_pll_clk,
+ ddr3a_pll_clk,
+ ddr3b_pll_clk,
+ sys_clk0_clk,
+ sys_clk0_1_clk,
+ sys_clk0_2_clk,
+ sys_clk0_3_clk,
+ sys_clk0_4_clk,
+ sys_clk0_6_clk,
+ sys_clk0_8_clk,
+ sys_clk0_12_clk,
+ sys_clk0_24_clk,
+ sys_clk1_clk,
+ sys_clk1_3_clk,
+ sys_clk1_4_clk,
+ sys_clk1_6_clk,
+ sys_clk1_12_clk,
+ sys_clk2_clk,
+ sys_clk3_clk
+};
+
+#define K2HK_CLK1_6 sys_clk0_6_clk
+
+/* PLL identifiers */
+enum pll_type_e {
+ CORE_PLL,
+ PASS_PLL,
+ TETRIS_PLL,
+ DDR3A_PLL,
+ DDR3B_PLL,
+};
+#define MAIN_PLL CORE_PLL
+
+/* PLL configuration data */
+struct pll_init_data {
+ int pll;
+ int pll_m; /* PLL Multiplier */
+ int pll_d; /* PLL divider */
+ int pll_od; /* PLL output divider */
+};
+
+#define CORE_PLL_799 {CORE_PLL, 13, 1, 2}
+#define CORE_PLL_983 {CORE_PLL, 16, 1, 2}
+#define CORE_PLL_1167 {CORE_PLL, 19, 1, 2}
+#define CORE_PLL_1228 {CORE_PLL, 20, 1, 2}
+#define PASS_PLL_1228 {PASS_PLL, 20, 1, 2}
+#define PASS_PLL_983 {PASS_PLL, 16, 1, 2}
+#define PASS_PLL_1050 {PASS_PLL, 205, 12, 2}
+#define TETRIS_PLL_500 {TETRIS_PLL, 8, 1, 2}
+#define TETRIS_PLL_750 {TETRIS_PLL, 12, 1, 2}
+#define TETRIS_PLL_687 {TETRIS_PLL, 11, 1, 2}
+#define TETRIS_PLL_625 {TETRIS_PLL, 10, 1, 2}
+#define TETRIS_PLL_812 {TETRIS_PLL, 13, 1, 2}
+#define TETRIS_PLL_875 {TETRIS_PLL, 14, 1, 2}
+#define TETRIS_PLL_1188 {TETRIS_PLL, 19, 2, 1}
+#define TETRIS_PLL_1200 {TETRIS_PLL, 48, 5, 1}
+#define TETRIS_PLL_1375 {TETRIS_PLL, 22, 2, 1}
+#define TETRIS_PLL_1400 {TETRIS_PLL, 56, 5, 1}
+#define DDR3_PLL_200(x) {DDR3##x##_PLL, 4, 1, 2}
+#define DDR3_PLL_400(x) {DDR3##x##_PLL, 16, 1, 4}
+#define DDR3_PLL_800(x) {DDR3##x##_PLL, 16, 1, 2}
+#define DDR3_PLL_333(x) {DDR3##x##_PLL, 20, 1, 6}
+
+void init_plls(int num_pll, struct pll_init_data *config);
+void init_pll(const struct pll_init_data *data);
+unsigned long clk_get_rate(unsigned int clk);
+unsigned long clk_round_rate(unsigned int clk, unsigned long hz);
+int clk_set_rate(unsigned int clk, unsigned long hz);
+
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/arch-keystone/clock.h b/arch/arm/include/asm/arch-keystone/clock.h
new file mode 100644
index 0000000000..324501b75a
--- /dev/null
+++ b/arch/arm/include/asm/arch-keystone/clock.h
@@ -0,0 +1,17 @@
+/*
+ * keystone2: common clock header file
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_CLOCK_H
+#define __ASM_ARCH_CLOCK_H
+
+#ifdef CONFIG_SOC_K2HK
+#include <asm/arch/clock-k2hk.h>
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/arch-keystone/clock_defs.h b/arch/arm/include/asm/arch-keystone/clock_defs.h
new file mode 100644
index 0000000000..b251aff383
--- /dev/null
+++ b/arch/arm/include/asm/arch-keystone/clock_defs.h
@@ -0,0 +1,111 @@
+/*
+ * keystone2: common pll clock definitions
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _CLOCK_DEFS_H_
+#define _CLOCK_DEFS_H_
+
+#include <asm/arch/hardware.h>
+
+#define BIT(x) (1 << (x))
+
+/* PLL Control Registers */
+struct pllctl_regs {
+ u32 ctl; /* 00 */
+ u32 ocsel; /* 04 */
+ u32 secctl; /* 08 */
+ u32 resv0;
+ u32 mult; /* 10 */
+ u32 prediv; /* 14 */
+ u32 div1; /* 18 */
+ u32 div2; /* 1c */
+ u32 div3; /* 20 */
+ u32 oscdiv1; /* 24 */
+ u32 resv1; /* 28 */
+ u32 bpdiv; /* 2c */
+ u32 wakeup; /* 30 */
+ u32 resv2;
+ u32 cmd; /* 38 */
+ u32 stat; /* 3c */
+ u32 alnctl; /* 40 */
+ u32 dchange; /* 44 */
+ u32 cken; /* 48 */
+ u32 ckstat; /* 4c */
+ u32 systat; /* 50 */
+ u32 ckctl; /* 54 */
+ u32 resv3[2];
+ u32 div4; /* 60 */
+ u32 div5; /* 64 */
+ u32 div6; /* 68 */
+ u32 div7; /* 6c */
+ u32 div8; /* 70 */
+ u32 div9; /* 74 */
+ u32 div10; /* 78 */
+ u32 div11; /* 7c */
+ u32 div12; /* 80 */
+};
+
+static struct pllctl_regs *pllctl_regs[] = {
+ (struct pllctl_regs *)(CLOCK_BASE + 0x100)
+};
+
+#define pllctl_reg(pll, reg) (&(pllctl_regs[pll]->reg))
+#define pllctl_reg_read(pll, reg) __raw_readl(pllctl_reg(pll, reg))
+#define pllctl_reg_write(pll, reg, val) __raw_writel(val, pllctl_reg(pll, reg))
+
+#define pllctl_reg_rmw(pll, reg, mask, val) \
+ pllctl_reg_write(pll, reg, \
+ (pllctl_reg_read(pll, reg) & ~(mask)) | val)
+
+#define pllctl_reg_setbits(pll, reg, mask) \
+ pllctl_reg_rmw(pll, reg, 0, mask)
+
+#define pllctl_reg_clrbits(pll, reg, mask) \
+ pllctl_reg_rmw(pll, reg, mask, 0)
+
+#define pll0div_read(N) ((pllctl_reg_read(CORE_PLL, div##N) & 0xff) + 1)
+
+/* PLLCTL Bits */
+#define PLLCTL_BYPASS BIT(23)
+#define PLL_PLLRST BIT(14)
+#define PLLCTL_PAPLL BIT(13)
+#define PLLCTL_CLKMODE BIT(8)
+#define PLLCTL_PLLSELB BIT(7)
+#define PLLCTL_ENSAT BIT(6)
+#define PLLCTL_PLLENSRC BIT(5)
+#define PLLCTL_PLLDIS BIT(4)
+#define PLLCTL_PLLRST BIT(3)
+#define PLLCTL_PLLPWRDN BIT(1)
+#define PLLCTL_PLLEN BIT(0)
+#define PLLSTAT_GO BIT(0)
+
+#define MAIN_ENSAT_OFFSET 6
+
+#define PLLDIV_ENABLE BIT(15)
+
+#define PLL_DIV_MASK 0x3f
+#define PLL_MULT_MASK 0x1fff
+#define PLL_MULT_SHIFT 6
+#define PLLM_MULT_HI_MASK 0x7f
+#define PLLM_MULT_HI_SHIFT 12
+#define PLLM_MULT_HI_SMASK (PLLM_MULT_HI_MASK << PLLM_MULT_HI_SHIFT)
+#define PLLM_MULT_LO_MASK 0x3f
+#define PLL_CLKOD_MASK 0xf
+#define PLL_CLKOD_SHIFT 19
+#define PLL_CLKOD_SMASK (PLL_CLKOD_MASK << PLL_CLKOD_SHIFT)
+#define PLL_BWADJ_LO_MASK 0xff
+#define PLL_BWADJ_LO_SHIFT 24
+#define PLL_BWADJ_LO_SMASK (PLL_BWADJ_LO_MASK << PLL_BWADJ_LO_SHIFT)
+#define PLL_BWADJ_HI_MASK 0xf
+
+#define PLLM_RATIO_DIV1 (PLLDIV_ENABLE | 0)
+#define PLLM_RATIO_DIV2 (PLLDIV_ENABLE | 0)
+#define PLLM_RATIO_DIV3 (PLLDIV_ENABLE | 1)
+#define PLLM_RATIO_DIV4 (PLLDIV_ENABLE | 4)
+#define PLLM_RATIO_DIV5 (PLLDIV_ENABLE | 17)
+
+#endif /* _CLOCK_DEFS_H_ */
diff --git a/arch/arm/include/asm/arch-keystone/emac_defs.h b/arch/arm/include/asm/arch-keystone/emac_defs.h
new file mode 100644
index 0000000000..0aa2f89d78
--- /dev/null
+++ b/arch/arm/include/asm/arch-keystone/emac_defs.h
@@ -0,0 +1,240 @@
+/*
+ * emac definitions for keystone2 devices
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _EMAC_DEFS_H_
+#define _EMAC_DEFS_H_
+
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+
+#define DEVICE_REG32_R(a) readl(a)
+#define DEVICE_REG32_W(a, v) writel(v, a)
+
+#define EMAC_EMACSL_BASE_ADDR (KS2_PASS_BASE + 0x00090900)
+#define EMAC_MDIO_BASE_ADDR (KS2_PASS_BASE + 0x00090300)
+#define EMAC_SGMII_BASE_ADDR (KS2_PASS_BASE + 0x00090100)
+
+#define KEYSTONE2_EMAC_GIG_ENABLE
+
+#define MAC_ID_BASE_ADDR (KS2_DEVICE_STATE_CTRL_BASE + 0x110)
+
+#ifdef CONFIG_SOC_K2HK
+/* MDIO module input frequency */
+#define EMAC_MDIO_BUS_FREQ (clk_get_rate(pass_pll_clk))
+/* MDIO clock output frequency */
+#define EMAC_MDIO_CLOCK_FREQ 1000000 /* 1.0 MHz */
+#endif
+
+/* MII Status Register */
+#define MII_STATUS_REG 1
+#define MII_STATUS_LINK_MASK (0x4)
+
+/* Marvell 88E1111 PHY ID */
+#define PHY_MARVELL_88E1111 (0x01410cc0)
+
+#define MDIO_CONTROL_IDLE (0x80000000)
+#define MDIO_CONTROL_ENABLE (0x40000000)
+#define MDIO_CONTROL_FAULT_ENABLE (0x40000)
+#define MDIO_CONTROL_FAULT (0x80000)
+#define MDIO_USERACCESS0_GO (0x80000000)
+#define MDIO_USERACCESS0_WRITE_READ (0x0)
+#define MDIO_USERACCESS0_WRITE_WRITE (0x40000000)
+#define MDIO_USERACCESS0_ACK (0x20000000)
+
+#define EMAC_MACCONTROL_MIIEN_ENABLE (0x20)
+#define EMAC_MACCONTROL_FULLDUPLEX_ENABLE (0x1)
+#define EMAC_MACCONTROL_GIGABIT_ENABLE (1 << 7)
+#define EMAC_MACCONTROL_GIGFORCE (1 << 17)
+#define EMAC_MACCONTROL_RMIISPEED_100 (1 << 15)
+
+#define EMAC_MIN_ETHERNET_PKT_SIZE 60
+
+struct mac_sl_cfg {
+ u_int32_t max_rx_len; /* Maximum receive packet length. */
+ u_int32_t ctl; /* Control bitfield */
+};
+
+/*
+ * Definition: Control bitfields used in the ctl field of hwGmacSlCfg_t
+ */
+#define GMACSL_RX_ENABLE_RCV_CONTROL_FRAMES (1 << 24)
+#define GMACSL_RX_ENABLE_RCV_SHORT_FRAMES (1 << 23)
+#define GMACSL_RX_ENABLE_RCV_ERROR_FRAMES (1 << 22)
+#define GMACSL_RX_ENABLE_EXT_CTL (1 << 18)
+#define GMACSL_RX_ENABLE_GIG_FORCE (1 << 17)
+#define GMACSL_RX_ENABLE_IFCTL_B (1 << 16)
+#define GMACSL_RX_ENABLE_IFCTL_A (1 << 15)
+#define GMACSL_RX_ENABLE_CMD_IDLE (1 << 11)
+#define GMACSL_TX_ENABLE_SHORT_GAP (1 << 10)
+#define GMACSL_ENABLE_GIG_MODE (1 << 7)
+#define GMACSL_TX_ENABLE_PACE (1 << 6)
+#define GMACSL_ENABLE (1 << 5)
+#define GMACSL_TX_ENABLE_FLOW_CTL (1 << 4)
+#define GMACSL_RX_ENABLE_FLOW_CTL (1 << 3)
+#define GMACSL_ENABLE_LOOPBACK (1 << 1)
+#define GMACSL_ENABLE_FULL_DUPLEX (1 << 0)
+
+/*
+ * DEFINTITION: function return values
+ */
+#define GMACSL_RET_OK 0
+#define GMACSL_RET_INVALID_PORT -1
+#define GMACSL_RET_WARN_RESET_INCOMPLETE -2
+#define GMACSL_RET_WARN_MAXLEN_TOO_BIG -3
+#define GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE -4
+
+/* Register offsets */
+#define CPGMACSL_REG_ID 0x00
+#define CPGMACSL_REG_CTL 0x04
+#define CPGMACSL_REG_STATUS 0x08
+#define CPGMACSL_REG_RESET 0x0c
+#define CPGMACSL_REG_MAXLEN 0x10
+#define CPGMACSL_REG_BOFF 0x14
+#define CPGMACSL_REG_RX_PAUSE 0x18
+#define CPGMACSL_REG_TX_PAURSE 0x1c
+#define CPGMACSL_REG_EM_CTL 0x20
+#define CPGMACSL_REG_PRI 0x24
+
+/* Soft reset register values */
+#define CPGMAC_REG_RESET_VAL_RESET_MASK (1 << 0)
+#define CPGMAC_REG_RESET_VAL_RESET (1 << 0)
+
+/* Maxlen register values */
+#define CPGMAC_REG_MAXLEN_LEN 0x3fff
+
+/* Control bitfields */
+#define CPSW_CTL_P2_PASS_PRI_TAGGED (1 << 5)
+#define CPSW_CTL_P1_PASS_PRI_TAGGED (1 << 4)
+#define CPSW_CTL_P0_PASS_PRI_TAGGED (1 << 3)
+#define CPSW_CTL_P0_ENABLE (1 << 2)
+#define CPSW_CTL_VLAN_AWARE (1 << 1)
+#define CPSW_CTL_FIFO_LOOPBACK (1 << 0)
+
+#define DEVICE_CPSW_NUM_PORTS 5 /* 5 switch ports */
+#define DEVICE_CPSW_BASE (0x02090800)
+#define target_get_switch_ctl() CPSW_CTL_P0_ENABLE /* Enable port 0 */
+#define SWITCH_MAX_PKT_SIZE 9000
+
+/* Register offsets */
+#define CPSW_REG_CTL 0x004
+#define CPSW_REG_STAT_PORT_EN 0x00c
+#define CPSW_REG_MAXLEN 0x040
+#define CPSW_REG_ALE_CONTROL 0x608
+#define CPSW_REG_ALE_PORTCTL(x) (0x640 + (x)*4)
+
+/* Register values */
+#define CPSW_REG_VAL_STAT_ENABLE_ALL 0xf
+#define CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE ((u_int32_t)0xc0000000)
+#define CPSW_REG_VAL_ALE_CTL_BYPASS ((u_int32_t)0x00000010)
+#define CPSW_REG_VAL_PORTCTL_FORWARD_MODE 0x3
+
+#define SGMII_REG_STATUS_LOCK BIT(4)
+#define SGMII_REG_STATUS_LINK BIT(0)
+#define SGMII_REG_STATUS_AUTONEG BIT(2)
+#define SGMII_REG_CONTROL_AUTONEG BIT(0)
+#define SGMII_REG_CONTROL_MASTER BIT(5)
+#define SGMII_REG_MR_ADV_ENABLE BIT(0)
+#define SGMII_REG_MR_ADV_LINK BIT(15)
+#define SGMII_REG_MR_ADV_FULL_DUPLEX BIT(12)
+#define SGMII_REG_MR_ADV_GIG_MODE BIT(11)
+
+#define SGMII_LINK_MAC_MAC_AUTONEG 0
+#define SGMII_LINK_MAC_PHY 1
+#define SGMII_LINK_MAC_MAC_FORCED 2
+#define SGMII_LINK_MAC_FIBER 3
+#define SGMII_LINK_MAC_PHY_FORCED 4
+
+#define TARGET_SGMII_BASE KS2_PASS_BASE + 0x00090100
+#define TARGET_SGMII_BASE_ADDRESSES {KS2_PASS_BASE + 0x00090100, \
+ KS2_PASS_BASE + 0x00090200, \
+ KS2_PASS_BASE + 0x00090400, \
+ KS2_PASS_BASE + 0x00090500}
+
+#define SGMII_OFFSET(x) ((x <= 1) ? (x * 0x100) : ((x * 0x100) + 0x100))
+
+/*
+ * SGMII registers
+ */
+#define SGMII_IDVER_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x000)
+#define SGMII_SRESET_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x004)
+#define SGMII_CTL_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x010)
+#define SGMII_STATUS_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x014)
+#define SGMII_MRADV_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x018)
+#define SGMII_LPADV_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x020)
+#define SGMII_TXCFG_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x030)
+#define SGMII_RXCFG_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x034)
+#define SGMII_AUXCFG_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x038)
+
+#define DEVICE_EMACSL_BASE(x) (KS2_PASS_BASE + 0x00090900 + (x) * 0x040)
+#define DEVICE_N_GMACSL_PORTS 4
+#define DEVICE_EMACSL_RESET_POLL_COUNT 100
+
+#define DEVICE_PSTREAM_CFG_REG_ADDR (KS2_PASS_BASE + 0x604)
+
+#ifdef CONFIG_SOC_K2HK
+#define DEVICE_PSTREAM_CFG_REG_VAL_ROUTE_CPPI 0x06060606
+#endif
+
+#define hw_config_streaming_switch() \
+ DEVICE_REG32_W(DEVICE_PSTREAM_CFG_REG_ADDR, \
+ DEVICE_PSTREAM_CFG_REG_VAL_ROUTE_CPPI);
+
+/* EMAC MDIO Registers Structure */
+struct mdio_regs {
+ dv_reg version;
+ dv_reg control;
+ dv_reg alive;
+ dv_reg link;
+ dv_reg linkintraw;
+ dv_reg linkintmasked;
+ u_int8_t rsvd0[8];
+ dv_reg userintraw;
+ dv_reg userintmasked;
+ dv_reg userintmaskset;
+ dv_reg userintmaskclear;
+ u_int8_t rsvd1[80];
+ dv_reg useraccess0;
+ dv_reg userphysel0;
+ dv_reg useraccess1;
+ dv_reg userphysel1;
+};
+
+/* Ethernet MAC Registers Structure */
+struct emac_regs {
+ dv_reg idver;
+ dv_reg maccontrol;
+ dv_reg macstatus;
+ dv_reg soft_reset;
+ dv_reg rx_maxlen;
+ u32 rsvd0;
+ dv_reg rx_pause;
+ dv_reg tx_pause;
+ dv_reg emcontrol;
+ dv_reg pri_map;
+ u32 rsvd1[6];
+};
+
+#define SGMII_ACCESS(port, reg) \
+ *((volatile unsigned int *)(sgmiis[port] + reg))
+
+struct eth_priv_t {
+ char int_name[32];
+ int rx_flow;
+ int phy_addr;
+ int slave_port;
+ int sgmii_link_type;
+};
+
+extern struct eth_priv_t eth_priv_cfg[];
+
+int keystone2_emac_initialize(struct eth_priv_t *eth_priv);
+void sgmii_serdes_setup_156p25mhz(void);
+void sgmii_serdes_shutdown(void);
+
+#endif /* _EMAC_DEFS_H_ */
diff --git a/arch/arm/include/asm/arch-keystone/emif_defs.h b/arch/arm/include/asm/arch-keystone/emif_defs.h
new file mode 100644
index 0000000000..a3378aa30e
--- /dev/null
+++ b/arch/arm/include/asm/arch-keystone/emif_defs.h
@@ -0,0 +1,73 @@
+/*
+ * emif definitions to re-use davinci emif driver on Keystone2
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ * (C) Copyright 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _EMIF_DEFS_H_
+#define _EMIF_DEFS_H_
+
+#include <asm/arch/hardware.h>
+
+struct davinci_emif_regs {
+ uint32_t ercsr;
+ uint32_t awccr;
+ uint32_t sdbcr;
+ uint32_t sdrcr;
+ uint32_t abncr[4];
+ uint32_t sdtimr;
+ uint32_t ddrsr;
+ uint32_t ddrphycr;
+ uint32_t ddrphysr;
+ uint32_t totar;
+ uint32_t totactr;
+ uint32_t ddrphyid_rev;
+ uint32_t sdsretr;
+ uint32_t eirr;
+ uint32_t eimr;
+ uint32_t eimsr;
+ uint32_t eimcr;
+ uint32_t ioctrlr;
+ uint32_t iostatr;
+ uint32_t rsvd0;
+ uint32_t one_nand_cr;
+ uint32_t nandfcr;
+ uint32_t nandfsr;
+ uint32_t rsvd1[2];
+ uint32_t nandfecc[4];
+ uint32_t rsvd2[15];
+ uint32_t nand4biteccload;
+ uint32_t nand4bitecc[4];
+ uint32_t nanderradd1;
+ uint32_t nanderradd2;
+ uint32_t nanderrval1;
+ uint32_t nanderrval2;
+};
+
+#define davinci_emif_regs \
+ ((struct davinci_emif_regs *)DAVINCI_ASYNC_EMIF_CNTRL_BASE)
+
+#define DAVINCI_NANDFCR_NAND_ENABLE(n) (1 << ((n) - 2))
+#define DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK (3 << 4)
+#define DAVINCI_NANDFCR_4BIT_ECC_SEL(n) (((n) - 2) << 4)
+#define DAVINCI_NANDFCR_1BIT_ECC_START(n) (1 << (8 + ((n) - 2)))
+#define DAVINCI_NANDFCR_4BIT_ECC_START (1 << 12)
+#define DAVINCI_NANDFCR_4BIT_CALC_START (1 << 13)
+
+/* Chip Select setup */
+#define DAVINCI_ABCR_STROBE_SELECT (1 << 31)
+#define DAVINCI_ABCR_EXT_WAIT (1 << 30)
+#define DAVINCI_ABCR_WSETUP(n) ((n) << 26)
+#define DAVINCI_ABCR_WSTROBE(n) ((n) << 20)
+#define DAVINCI_ABCR_WHOLD(n) ((n) << 17)
+#define DAVINCI_ABCR_RSETUP(n) ((n) << 13)
+#define DAVINCI_ABCR_RSTROBE(n) ((n) << 7)
+#define DAVINCI_ABCR_RHOLD(n) ((n) << 4)
+#define DAVINCI_ABCR_TA(n) ((n) << 2)
+#define DAVINCI_ABCR_ASIZE_16BIT 1
+#define DAVINCI_ABCR_ASIZE_8BIT 0
+
+#endif
diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
new file mode 100644
index 0000000000..50ff13a3b2
--- /dev/null
+++ b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
@@ -0,0 +1,150 @@
+/*
+ * K2HK: SoC definitions
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef __ASM_ARCH_HARDWARE_K2HK_H
+#define __ASM_ARCH_HARDWARE_K2HK_H
+
+#define K2HK_ASYNC_EMIF_CNTRL_BASE 0x21000a00
+#define DAVINCI_ASYNC_EMIF_CNTRL_BASE K2HK_ASYNC_EMIF_CNTRL_BASE
+#define K2HK_ASYNC_EMIF_DATA_CE0_BASE 0x30000000
+#define K2HK_ASYNC_EMIF_DATA_CE1_BASE 0x34000000
+#define K2HK_ASYNC_EMIF_DATA_CE2_BASE 0x38000000
+#define K2HK_ASYNC_EMIF_DATA_CE3_BASE 0x3c000000
+
+#define K2HK_PLL_CNTRL_BASE 0x02310000
+#define CLOCK_BASE K2HK_PLL_CNTRL_BASE
+#define KS2_RSTCTRL (K2HK_PLL_CNTRL_BASE + 0xe8)
+#define KS2_RSTCTRL_KEY 0x5a69
+#define KS2_RSTCTRL_MASK 0xffff0000
+#define KS2_RSTCTRL_SWRST 0xfffe0000
+
+#define K2HK_PSC_BASE 0x02350000
+#define KS2_DEVICE_STATE_CTRL_BASE 0x02620000
+#define JTAG_ID_REG (KS2_DEVICE_STATE_CTRL_BASE + 0x18)
+#define K2HK_DEVSTAT (KS2_DEVICE_STATE_CTRL_BASE + 0x20)
+
+#define K2HK_MISC_CTRL (KS2_DEVICE_STATE_CTRL_BASE + 0xc7c)
+
+#define ARM_PLL_EN BIT(13)
+
+#define K2HK_SPI0_BASE 0x21000400
+#define K2HK_SPI1_BASE 0x21000600
+#define K2HK_SPI2_BASE 0x21000800
+#define K2HK_SPI_BASE K2HK_SPI0_BASE
+
+/* Chip configuration unlock codes and registers */
+#define KEYSTONE_KICK0 (KS2_DEVICE_STATE_CTRL_BASE + 0x38)
+#define KEYSTONE_KICK1 (KS2_DEVICE_STATE_CTRL_BASE + 0x3c)
+#define KEYSTONE_KICK0_MAGIC 0x83e70b13
+#define KEYSTONE_KICK1_MAGIC 0x95a4f1e0
+
+/* PA SS Registers */
+#define KS2_PASS_BASE 0x02000000
+
+/* PLL control registers */
+#define K2HK_MAINPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x350)
+#define K2HK_MAINPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x354)
+#define K2HK_PASSPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x358)
+#define K2HK_PASSPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x35C)
+#define K2HK_DDR3APLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x360)
+#define K2HK_DDR3APLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x364)
+#define K2HK_DDR3BPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x368)
+#define K2HK_DDR3BPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x36C)
+#define K2HK_ARMPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x370)
+#define K2HK_ARMPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x374)
+
+/* Power and Sleep Controller (PSC) Domains */
+#define K2HK_LPSC_MOD 0
+#define K2HK_LPSC_DUMMY1 1
+#define K2HK_LPSC_USB 2
+#define K2HK_LPSC_EMIF25_SPI 3
+#define K2HK_LPSC_TSIP 4
+#define K2HK_LPSC_DEBUGSS_TRC 5
+#define K2HK_LPSC_TETB_TRC 6
+#define K2HK_LPSC_PKTPROC 7
+#define KS2_LPSC_PA K2HK_LPSC_PKTPROC
+#define K2HK_LPSC_SGMII 8
+#define KS2_LPSC_CPGMAC K2HK_LPSC_SGMII
+#define K2HK_LPSC_CRYPTO 9
+#define K2HK_LPSC_PCIE 10
+#define K2HK_LPSC_SRIO 11
+#define K2HK_LPSC_VUSR0 12
+#define K2HK_LPSC_CHIP_SRSS 13
+#define K2HK_LPSC_MSMC 14
+#define K2HK_LPSC_GEM_0 15
+#define K2HK_LPSC_GEM_1 16
+#define K2HK_LPSC_GEM_2 17
+#define K2HK_LPSC_GEM_3 18
+#define K2HK_LPSC_GEM_4 19
+#define K2HK_LPSC_GEM_5 20
+#define K2HK_LPSC_GEM_6 21
+#define K2HK_LPSC_GEM_7 22
+#define K2HK_LPSC_EMIF4F_DDR3A 23
+#define K2HK_LPSC_EMIF4F_DDR3B 24
+#define K2HK_LPSC_TAC 25
+#define K2HK_LPSC_RAC 26
+#define K2HK_LPSC_RAC_1 27
+#define K2HK_LPSC_FFTC_A 28
+#define K2HK_LPSC_FFTC_B 29
+#define K2HK_LPSC_FFTC_C 30
+#define K2HK_LPSC_FFTC_D 31
+#define K2HK_LPSC_FFTC_E 32
+#define K2HK_LPSC_FFTC_F 33
+#define K2HK_LPSC_AI2 34
+#define K2HK_LPSC_TCP3D_0 35
+#define K2HK_LPSC_TCP3D_1 36
+#define K2HK_LPSC_TCP3D_2 37
+#define K2HK_LPSC_TCP3D_3 38
+#define K2HK_LPSC_VCP2X4_A 39
+#define K2HK_LPSC_CP2X4_B 40
+#define K2HK_LPSC_VCP2X4_C 41
+#define K2HK_LPSC_VCP2X4_D 42
+#define K2HK_LPSC_VCP2X4_E 43
+#define K2HK_LPSC_VCP2X4_F 44
+#define K2HK_LPSC_VCP2X4_G 45
+#define K2HK_LPSC_VCP2X4_H 46
+#define K2HK_LPSC_BCP 47
+#define K2HK_LPSC_DXB 48
+#define K2HK_LPSC_VUSR1 49
+#define K2HK_LPSC_XGE 50
+#define K2HK_LPSC_ARM_SREFLEX 51
+#define K2HK_LPSC_TETRIS 52
+
+#define K2HK_UART0_BASE 0x02530c00
+
+/* DDR3A definitions */
+#define K2HK_DDR3A_EMIF_CTRL_BASE 0x21010000
+#define K2HK_DDR3A_EMIF_DATA_BASE 0x80000000
+#define K2HK_DDR3A_DDRPHYC 0x02329000
+/* DDR3B definitions */
+#define K2HK_DDR3B_EMIF_CTRL_BASE 0x21020000
+#define K2HK_DDR3B_EMIF_DATA_BASE 0x60000000
+#define K2HK_DDR3B_DDRPHYC 0x02328000
+
+/* Queue manager */
+#define DEVICE_QM_MANAGER_BASE 0x02a02000
+#define DEVICE_QM_DESC_SETUP_BASE 0x02a03000
+#define DEVICE_QM_MANAGER_QUEUES_BASE 0x02a80000
+#define DEVICE_QM_MANAGER_Q_PROXY_BASE 0x02ac0000
+#define DEVICE_QM_QUEUE_STATUS_BASE 0x02a40000
+#define DEVICE_QM_NUM_LINKRAMS 2
+#define DEVICE_QM_NUM_MEMREGIONS 20
+
+#define DEVICE_PA_CDMA_GLOBAL_CFG_BASE 0x02004000
+#define DEVICE_PA_CDMA_TX_CHAN_CFG_BASE 0x02004400
+#define DEVICE_PA_CDMA_RX_CHAN_CFG_BASE 0x02004800
+#define DEVICE_PA_CDMA_RX_FLOW_CFG_BASE 0x02005000
+
+#define DEVICE_PA_CDMA_RX_NUM_CHANNELS 24
+#define DEVICE_PA_CDMA_RX_NUM_FLOWS 32
+#define DEVICE_PA_CDMA_TX_NUM_CHANNELS 9
+
+/* MSMC control */
+#define K2HK_MSMC_CTRL_BASE 0x0bc00000
+
+#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/include/asm/arch-keystone/hardware.h b/arch/arm/include/asm/arch-keystone/hardware.h
new file mode 100644
index 0000000000..a305a0cc09
--- /dev/null
+++ b/arch/arm/include/asm/arch-keystone/hardware.h
@@ -0,0 +1,175 @@
+/*
+ * Keystone2: Common SoC definitions, structures etc.
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include <config.h>
+
+#ifndef __ASSEMBLY__
+
+#include <linux/sizes.h>
+#include <asm/io.h>
+
+#define REG(addr) (*(volatile unsigned int *)(addr))
+#define REG_P(addr) ((volatile unsigned int *)(addr))
+
+typedef volatile unsigned int dv_reg;
+typedef volatile unsigned int *dv_reg_p;
+
+#define ASYNC_EMIF_NUM_CS 4
+#define ASYNC_EMIF_MODE_NOR 0
+#define ASYNC_EMIF_MODE_NAND 1
+#define ASYNC_EMIF_MODE_ONENAND 2
+#define ASYNC_EMIF_PRESERVE -1
+
+struct async_emif_config {
+ unsigned mode;
+ unsigned select_strobe;
+ unsigned extend_wait;
+ unsigned wr_setup;
+ unsigned wr_strobe;
+ unsigned wr_hold;
+ unsigned rd_setup;
+ unsigned rd_strobe;
+ unsigned rd_hold;
+ unsigned turn_around;
+ enum {
+ ASYNC_EMIF_8 = 0,
+ ASYNC_EMIF_16 = 1,
+ ASYNC_EMIF_32 = 2,
+ } width;
+};
+
+void init_async_emif(int num_cs, struct async_emif_config *config);
+
+struct ddr3_phy_config {
+ unsigned int pllcr;
+ unsigned int pgcr1_mask;
+ unsigned int pgcr1_val;
+ unsigned int ptr0;
+ unsigned int ptr1;
+ unsigned int ptr2;
+ unsigned int ptr3;
+ unsigned int ptr4;
+ unsigned int dcr_mask;
+ unsigned int dcr_val;
+ unsigned int dtpr0;
+ unsigned int dtpr1;
+ unsigned int dtpr2;
+ unsigned int mr0;
+ unsigned int mr1;
+ unsigned int mr2;
+ unsigned int dtcr;
+ unsigned int pgcr2;
+ unsigned int zq0cr1;
+ unsigned int zq1cr1;
+ unsigned int zq2cr1;
+ unsigned int pir_v1;
+ unsigned int pir_v2;
+};
+
+struct ddr3_emif_config {
+ unsigned int sdcfg;
+ unsigned int sdtim1;
+ unsigned int sdtim2;
+ unsigned int sdtim3;
+ unsigned int sdtim4;
+ unsigned int zqcfg;
+ unsigned int sdrfc;
+};
+
+#endif
+
+#define BIT(x) (1 << (x))
+
+#define KS2_DDRPHY_PIR_OFFSET 0x04
+#define KS2_DDRPHY_PGCR0_OFFSET 0x08
+#define KS2_DDRPHY_PGCR1_OFFSET 0x0C
+#define KS2_DDRPHY_PGSR0_OFFSET 0x10
+#define KS2_DDRPHY_PGSR1_OFFSET 0x14
+#define KS2_DDRPHY_PLLCR_OFFSET 0x18
+#define KS2_DDRPHY_PTR0_OFFSET 0x1C
+#define KS2_DDRPHY_PTR1_OFFSET 0x20
+#define KS2_DDRPHY_PTR2_OFFSET 0x24
+#define KS2_DDRPHY_PTR3_OFFSET 0x28
+#define KS2_DDRPHY_PTR4_OFFSET 0x2C
+#define KS2_DDRPHY_DCR_OFFSET 0x44
+
+#define KS2_DDRPHY_DTPR0_OFFSET 0x48
+#define KS2_DDRPHY_DTPR1_OFFSET 0x4C
+#define KS2_DDRPHY_DTPR2_OFFSET 0x50
+
+#define KS2_DDRPHY_MR0_OFFSET 0x54
+#define KS2_DDRPHY_MR1_OFFSET 0x58
+#define KS2_DDRPHY_MR2_OFFSET 0x5C
+#define KS2_DDRPHY_DTCR_OFFSET 0x68
+#define KS2_DDRPHY_PGCR2_OFFSET 0x8C
+
+#define KS2_DDRPHY_ZQ0CR1_OFFSET 0x184
+#define KS2_DDRPHY_ZQ1CR1_OFFSET 0x194
+#define KS2_DDRPHY_ZQ2CR1_OFFSET 0x1A4
+#define KS2_DDRPHY_ZQ3CR1_OFFSET 0x1B4
+
+#define KS2_DDRPHY_DATX8_8_OFFSET 0x3C0
+
+#define IODDRM_MASK 0x00000180
+#define ZCKSEL_MASK 0x01800000
+#define CL_MASK 0x00000072
+#define WR_MASK 0x00000E00
+#define BL_MASK 0x00000003
+#define RRMODE_MASK 0x00040000
+#define UDIMM_MASK 0x20000000
+#define BYTEMASK_MASK 0x0003FC00
+#define MPRDQ_MASK 0x00000080
+#define PDQ_MASK 0x00000070
+#define NOSRA_MASK 0x08000000
+#define ECC_MASK 0x00000001
+
+#define KS2_DDR3_MIDR_OFFSET 0x00
+#define KS2_DDR3_STATUS_OFFSET 0x04
+#define KS2_DDR3_SDCFG_OFFSET 0x08
+#define KS2_DDR3_SDRFC_OFFSET 0x10
+#define KS2_DDR3_SDTIM1_OFFSET 0x18
+#define KS2_DDR3_SDTIM2_OFFSET 0x1C
+#define KS2_DDR3_SDTIM3_OFFSET 0x20
+#define KS2_DDR3_SDTIM4_OFFSET 0x28
+#define KS2_DDR3_PMCTL_OFFSET 0x38
+#define KS2_DDR3_ZQCFG_OFFSET 0xC8
+
+#ifdef CONFIG_SOC_K2HK
+#include <asm/arch/hardware-k2hk.h>
+#endif
+
+#ifndef __ASSEMBLY__
+static inline int cpu_is_k2hk(void)
+{
+ unsigned int jtag_id = __raw_readl(JTAG_ID_REG);
+ unsigned int part_no = (jtag_id >> 12) & 0xffff;
+
+ return (part_no == 0xb981) ? 1 : 0;
+}
+
+static inline int cpu_revision(void)
+{
+ unsigned int jtag_id = __raw_readl(JTAG_ID_REG);
+ unsigned int rev = (jtag_id >> 28) & 0xf;
+
+ return rev;
+}
+
+void share_all_segments(int priv_id);
+int cpu_to_bus(u32 *ptr, u32 length);
+void init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg);
+void init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg);
+void init_ddr3(void);
+void sdelay(unsigned long);
+
+#endif
+
+#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/include/asm/arch-keystone/i2c_defs.h b/arch/arm/include/asm/arch-keystone/i2c_defs.h
new file mode 100644
index 0000000000..d4256526cc
--- /dev/null
+++ b/arch/arm/include/asm/arch-keystone/i2c_defs.h
@@ -0,0 +1,17 @@
+/*
+ * keystone: i2c driver definitions
+ *
+ * (C) Copyright 2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _I2C_DEFS_H_
+#define _I2C_DEFS_H_
+
+#define I2C0_BASE 0x02530000
+#define I2C1_BASE 0x02530400
+#define I2C2_BASE 0x02530800
+#define I2C_BASE I2C0_BASE
+
+#endif
diff --git a/arch/arm/include/asm/arch-keystone/keystone_nav.h b/arch/arm/include/asm/arch-keystone/keystone_nav.h
new file mode 100644
index 0000000000..ab81eaf1fd
--- /dev/null
+++ b/arch/arm/include/asm/arch-keystone/keystone_nav.h
@@ -0,0 +1,193 @@
+/*
+ * Multicore Navigator definitions
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _KEYSTONE_NAV_H_
+#define _KEYSTONE_NAV_H_
+
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+
+enum soc_type_t {
+ k2hk
+};
+
+#define QM_OK 0
+#define QM_ERR -1
+#define QM_DESC_TYPE_HOST 0
+#define QM_DESC_PSINFO_IN_DESCR 0
+#define QM_DESC_DEFAULT_DESCINFO (QM_DESC_TYPE_HOST << 30) | \
+ (QM_DESC_PSINFO_IN_DESCR << 22)
+
+/* Packet Info */
+#define QM_DESC_PINFO_EPIB 1
+#define QM_DESC_PINFO_RETURN_OWN 1
+#define QM_DESC_DEFAULT_PINFO (QM_DESC_PINFO_EPIB << 31) | \
+ (QM_DESC_PINFO_RETURN_OWN << 15)
+
+struct qm_cfg_reg {
+ u32 revision;
+ u32 __pad1;
+ u32 divert;
+ u32 link_ram_base0;
+ u32 link_ram_size0;
+ u32 link_ram_base1;
+ u32 link_ram_size1;
+ u32 link_ram_base2;
+ u32 starvation[0];
+};
+
+struct descr_mem_setup_reg {
+ u32 base_addr;
+ u32 start_idx;
+ u32 desc_reg_size;
+ u32 _res0;
+};
+
+struct qm_reg_queue {
+ u32 entry_count;
+ u32 byte_count;
+ u32 packet_size;
+ u32 ptr_size_thresh;
+};
+
+struct qm_config {
+ /* QM module addresses */
+ u32 stat_cfg; /* status and config */
+ struct qm_reg_queue *queue; /* management region */
+ u32 mngr_vbusm; /* management region (VBUSM) */
+ u32 i_lram; /* internal linking RAM */
+ struct qm_reg_queue *proxy;
+ u32 status_ram;
+ struct qm_cfg_reg *mngr_cfg;
+ /* Queue manager config region */
+ u32 intd_cfg; /* QMSS INTD config region */
+ struct descr_mem_setup_reg *desc_mem;
+ /* descritor memory setup region*/
+ u32 region_num;
+ u32 pdsp_cmd; /* PDSP1 command interface */
+ u32 pdsp_ctl; /* PDSP1 control registers */
+ u32 pdsp_iram;
+ /* QM configuration parameters */
+
+ u32 qpool_num; /* */
+};
+
+struct qm_host_desc {
+ u32 desc_info;
+ u32 tag_info;
+ u32 packet_info;
+ u32 buff_len;
+ u32 buff_ptr;
+ u32 next_bdptr;
+ u32 orig_buff_len;
+ u32 orig_buff_ptr;
+ u32 timestamp;
+ u32 swinfo[3];
+ u32 ps_data[20];
+};
+
+#define HDESC_NUM 256
+
+int qm_init(void);
+void qm_close(void);
+void qm_push(struct qm_host_desc *hd, u32 qnum);
+struct qm_host_desc *qm_pop(u32 qnum);
+
+void qm_buff_push(struct qm_host_desc *hd, u32 qnum,
+ void *buff_ptr, u32 buff_len);
+
+struct qm_host_desc *qm_pop_from_free_pool(void);
+void queue_close(u32 qnum);
+
+/*
+ * DMA API
+ */
+#define CPDMA_REG_VAL_MAKE_RX_FLOW_A(einfo, psinfo, rxerr, desc, \
+ psloc, sopoff, qmgr, qnum) \
+ (((einfo & 1) << 30) | \
+ ((psinfo & 1) << 29) | \
+ ((rxerr & 1) << 28) | \
+ ((desc & 3) << 26) | \
+ ((psloc & 1) << 25) | \
+ ((sopoff & 0x1ff) << 16) | \
+ ((qmgr & 3) << 12) | \
+ ((qnum & 0xfff) << 0))
+
+#define CPDMA_REG_VAL_MAKE_RX_FLOW_D(fd0qm, fd0qnum, fd1qm, fd1qnum) \
+ (((fd0qm & 3) << 28) | \
+ ((fd0qnum & 0xfff) << 16) | \
+ ((fd1qm & 3) << 12) | \
+ ((fd1qnum & 0xfff) << 0))
+
+#define CPDMA_CHAN_A_ENABLE ((u32)1 << 31)
+#define CPDMA_CHAN_A_TDOWN (1 << 30)
+#define TDOWN_TIMEOUT_COUNT 100
+
+struct global_ctl_regs {
+ u32 revision;
+ u32 perf_control;
+ u32 emulation_control;
+ u32 priority_control;
+ u32 qm_base_addr[4];
+};
+
+struct tx_chan_regs {
+ u32 cfg_a;
+ u32 cfg_b;
+ u32 res[6];
+};
+
+struct rx_chan_regs {
+ u32 cfg_a;
+ u32 res[7];
+};
+
+struct rx_flow_regs {
+ u32 control;
+ u32 tags;
+ u32 tag_sel;
+ u32 fdq_sel[2];
+ u32 thresh[3];
+};
+
+struct pktdma_cfg {
+ struct global_ctl_regs *global;
+ struct tx_chan_regs *tx_ch;
+ u32 tx_ch_num;
+ struct rx_chan_regs *rx_ch;
+ u32 rx_ch_num;
+ u32 *tx_sched;
+ struct rx_flow_regs *rx_flows;
+ u32 rx_flow_num;
+
+ u32 rx_free_q;
+ u32 rx_rcv_q;
+ u32 tx_snd_q;
+
+ u32 rx_flow; /* flow that is used for RX */
+};
+
+/*
+ * packet dma user allocates memory for rx buffers
+ * and describe it in the following structure
+ */
+struct rx_buff_desc {
+ u8 *buff_ptr;
+ u32 num_buffs;
+ u32 buff_len;
+ u32 rx_flow;
+};
+
+int netcp_close(void);
+int netcp_init(struct rx_buff_desc *rx_buffers);
+int netcp_send(u32 *pkt, int num_bytes, u32 swinfo2);
+void *netcp_recv(u32 **pkt, int *num_bytes);
+void netcp_release_rxhd(void *hd);
+
+#endif /* _KEYSTONE_NAV_H_ */
diff --git a/arch/arm/include/asm/arch-keystone/nand_defs.h b/arch/arm/include/asm/arch-keystone/nand_defs.h
new file mode 100644
index 0000000000..58417dbc0b
--- /dev/null
+++ b/arch/arm/include/asm/arch-keystone/nand_defs.h
@@ -0,0 +1,23 @@
+/*
+ * nand driver definitions to re-use davinci nand driver on Keystone2
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ * (C) Copyright 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _NAND_DEFS_H_
+#define _NAND_DEFS_H_
+
+#include <asm/arch/hardware.h>
+#include <linux/mtd/nand.h>
+
+#define MASK_CLE 0x4000
+#define MASK_ALE 0x2000
+
+#define NAND_READ_START 0x00
+#define NAND_READ_END 0x30
+#define NAND_STATUS 0x70
+
+#endif
diff --git a/arch/arm/include/asm/arch-keystone/psc_defs.h b/arch/arm/include/asm/arch-keystone/psc_defs.h
new file mode 100644
index 0000000000..70d22cf217
--- /dev/null
+++ b/arch/arm/include/asm/arch-keystone/psc_defs.h
@@ -0,0 +1,90 @@
+/*
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _PSC_DEFS_H_
+#define _PSC_DEFS_H_
+
+#include <asm/arch/hardware.h>
+
+/*
+ * FILE PURPOSE: Local Power Sleep Controller definitions
+ *
+ * FILE NAME: psc_defs.h
+ *
+ * DESCRIPTION: Provides local definitions for the power saver controller
+ *
+ */
+
+/* Register offsets */
+#define PSC_REG_PTCMD 0x120
+#define PSC_REG_PSTAT 0x128
+#define PSC_REG_PDSTAT(x) (0x200 + (4 * (x)))
+#define PSC_REG_PDCTL(x) (0x300 + (4 * (x)))
+#define PSC_REG_MDCFG(x) (0x600 + (4 * (x)))
+#define PSC_REG_MDSTAT(x) (0x800 + (4 * (x)))
+#define PSC_REG_MDCTL(x) (0xa00 + (4 * (x)))
+
+#define BOOTBITMASK(x, y) ((((((u32)1 << (((u32)x) - ((u32)y) + (u32)1)) - \
+ (u32)1)) << ((u32)y)))
+
+#define BOOT_READ_BITFIELD(z, x, y) (((u32)z) & BOOTBITMASK(x, y)) >> (y)
+#define BOOT_SET_BITFIELD(z, f, x, y) (((u32)z) & ~BOOTBITMASK(x, y)) | \
+ ((((u32)f) << (y)) & BOOTBITMASK(x, y))
+
+/* PDCTL */
+#define PSC_REG_PDCTL_SET_NEXT(x, y) BOOT_SET_BITFIELD((x), (y), 0, 0)
+#define PSC_REG_PDCTL_SET_PDMODE(x, y) BOOT_SET_BITFIELD((x), (y), 15, 12)
+
+/* PDSTAT */
+#define PSC_REG_PDSTAT_GET_STATE(x) BOOT_READ_BITFIELD((x), 4, 0)
+
+/* MDCFG */
+#define PSC_REG_MDCFG_GET_PD(x) BOOT_READ_BITFIELD((x), 20, 16)
+#define PSC_REG_MDCFG_GET_RESET_ISO(x) BOOT_READ_BITFIELD((x), 14, 14)
+
+/* MDCTL */
+#define PSC_REG_MDCTL_SET_NEXT(x, y) BOOT_SET_BITFIELD((x), (y), 4, 0)
+#define PSC_REG_MDCTL_SET_LRSTZ(x, y) BOOT_SET_BITFIELD((x), (y), 8, 8)
+#define PSC_REG_MDCTL_GET_LRSTZ(x) BOOT_READ_BITFIELD((x), 8, 8)
+#define PSC_REG_MDCTL_SET_RESET_ISO(x, y) BOOT_SET_BITFIELD((x), (y), \
+ 12, 12)
+
+/* MDSTAT */
+#define PSC_REG_MDSTAT_GET_STATUS(x) BOOT_READ_BITFIELD((x), 5, 0)
+#define PSC_REG_MDSTAT_GET_LRSTZ(x) BOOT_READ_BITFIELD((x), 8, 8)
+#define PSC_REG_MDSTAT_GET_LRSTDONE(x) BOOT_READ_BITFIELD((x), 9, 9)
+
+/* PDCTL states */
+#define PSC_REG_VAL_PDCTL_NEXT_ON 1
+#define PSC_REG_VAL_PDCTL_NEXT_OFF 0
+
+#define PSC_REG_VAL_PDCTL_PDMODE_SLEEP 0
+
+/* MDCTL states */
+#define PSC_REG_VAL_MDCTL_NEXT_SWRSTDISABLE 0
+#define PSC_REG_VAL_MDCTL_NEXT_OFF 2
+#define PSC_REG_VAL_MDCTL_NEXT_ON 3
+
+/* MDSTAT states */
+#define PSC_REG_VAL_MDSTAT_STATE_ON 3
+#define PSC_REG_VAL_MDSTAT_STATE_ENABLE_IN_PROG 0x24
+#define PSC_REG_VAL_MDSTAT_STATE_OFF 2
+#define PSC_REG_VAL_MDSTAT_STATE_DISABLE_IN_PROG1 0x20
+#define PSC_REG_VAL_MDSTAT_STATE_DISABLE_IN_PROG2 0x21
+#define PSC_REG_VAL_MDSTAT_STATE_DISABLE_IN_PROG3 0x22
+
+/*
+ * Timeout limit on checking PTSTAT. This is the number of times the
+ * wait function will be called before giving up.
+ */
+#define PSC_PTSTAT_TIMEOUT_LIMIT 100
+
+u32 psc_get_domain_num(u32 mod_num);
+int psc_enable_module(u32 mod_num);
+int psc_disable_module(u32 mod_num);
+int psc_disable_domain(u32 domain_num);
+
+#endif /* _PSC_DEFS_H_ */
diff --git a/arch/arm/include/asm/arch-keystone/spl.h b/arch/arm/include/asm/arch-keystone/spl.h
new file mode 100644
index 0000000000..7012ea7ff0
--- /dev/null
+++ b/arch/arm/include/asm/arch-keystone/spl.h
@@ -0,0 +1,12 @@
+/*
+ * (C) Copyright 2012-2014
+ * Texas Instruments, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _ASM_ARCH_SPL_H_
+#define _ASM_SPL_H_
+
+#define BOOT_DEVICE_SPI 2
+
+#endif
generated by cgit (git 2.34.1) at 2024-12-26 04:40:53 +0000