diff options
Diffstat (limited to 'arch/arm/include/asm/arch-meson')
| -rw-r--r-- | arch/arm/include/asm/arch-meson/axg.h | 52 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-meson/boot.h | 20 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-meson/clock-axg.h | 104 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-meson/clock-gx.h (renamed from arch/arm/include/asm/arch-meson/clock.h) | 4 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-meson/eth.h | 6 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-meson/gx.h | 1 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-meson/mem.h | 3 |
7 files changed, 184 insertions, 6 deletions
diff --git a/arch/arm/include/asm/arch-meson/axg.h b/arch/arm/include/asm/arch-meson/axg.h new file mode 100644 index 0000000000..d293f2a839 --- /dev/null +++ b/arch/arm/include/asm/arch-meson/axg.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 BayLibre, SAS + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +#ifndef __AXG_H__ +#define __AXG_H__ + +#define AXG_AOBUS_BASE 0xff800000 +#define AXG_PERIPHS_BASE 0xff634400 +#define AXG_HIU_BASE 0xff63c000 +#define AXG_ETH_BASE 0xff3f0000 + +/* Always-On Peripherals registers */ +#define AXG_AO_ADDR(off) (AXG_AOBUS_BASE + ((off) << 2)) + +#define AXG_AO_SEC_GP_CFG0 AXG_AO_ADDR(0x90) +#define AXG_AO_SEC_GP_CFG3 AXG_AO_ADDR(0x93) +#define AXG_AO_SEC_GP_CFG4 AXG_AO_ADDR(0x94) +#define AXG_AO_SEC_GP_CFG5 AXG_AO_ADDR(0x95) + +#define AXG_AO_BOOT_DEVICE 0xF +#define AXG_AO_MEM_SIZE_MASK 0xFFFF0000 +#define AXG_AO_MEM_SIZE_SHIFT 16 +#define AXG_AO_BL31_RSVMEM_SIZE_MASK 0xFFFF0000 +#define AXG_AO_BL31_RSVMEM_SIZE_SHIFT 16 +#define AXG_AO_BL32_RSVMEM_SIZE_MASK 0xFFFF + +/* Peripherals registers */ +#define AXG_PERIPHS_ADDR(off) (AXG_PERIPHS_BASE + ((off) << 2)) + +#define AXG_ETH_REG_0 AXG_PERIPHS_ADDR(0x50) +#define AXG_ETH_REG_1 AXG_PERIPHS_ADDR(0x51) + +#define AXG_ETH_REG_0_PHY_INTF_RGMII BIT(0) +#define AXG_ETH_REG_0_PHY_INTF_RMII BIT(2) +#define AXG_ETH_REG_0_TX_PHASE(x) (((x) & 3) << 5) +#define AXG_ETH_REG_0_TX_RATIO(x) (((x) & 7) << 7) +#define AXG_ETH_REG_0_PHY_CLK_EN BIT(10) +#define AXG_ETH_REG_0_INVERT_RMII_CLK BIT(11) +#define AXG_ETH_REG_0_CLK_EN BIT(12) + +/* HIU registers */ +#define AXG_HIU_ADDR(off) (AXG_HIU_BASE + ((off) << 2)) + +#define AXG_MEM_PD_REG_0 AXG_HIU_ADDR(0x40) + +/* Ethernet memory power domain */ +#define AXG_MEM_PD_REG_0_ETH_MASK (BIT(2) | BIT(3)) + +#endif /* __AXG_H__ */ diff --git a/arch/arm/include/asm/arch-meson/boot.h b/arch/arm/include/asm/arch-meson/boot.h new file mode 100644 index 0000000000..a90fe55081 --- /dev/null +++ b/arch/arm/include/asm/arch-meson/boot.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 BayLibre, SAS + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +#ifndef __MESON_BOOT_H__ +#define __MESON_BOOT_H__ + +/* Boot device */ +#define BOOT_DEVICE_RESERVED 0 +#define BOOT_DEVICE_EMMC 1 +#define BOOT_DEVICE_NAND 2 +#define BOOT_DEVICE_SPI 3 +#define BOOT_DEVICE_SD 4 +#define BOOT_DEVICE_USB 5 + +int meson_get_boot_device(void); + +#endif /* __MESON_BOOT_H__ */ diff --git a/arch/arm/include/asm/arch-meson/clock-axg.h b/arch/arm/include/asm/arch-meson/clock-axg.h new file mode 100644 index 0000000000..1ef88e4fad --- /dev/null +++ b/arch/arm/include/asm/arch-meson/clock-axg.h @@ -0,0 +1,104 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2016 - AmLogic, Inc. + * Copyright 2018 - Beniamino Galvani <b.galvani@gmail.com> + * Copyright 2018 - BayLibre, SAS + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ +#ifndef _ARCH_MESON_CLOCK_AXG_H_ +#define _ARCH_MESON_CLOCK_AXG_H_ + +/* + * Clock controller register offsets + * + * Register offsets from the data sheet are listed in comment blocks below. + * Those offsets must be multiplied by 4 before adding them to the base address + * to get the right value + */ +#define HHI_GP0_PLL_CNTL 0x40 +#define HHI_GP0_PLL_CNTL2 0x44 +#define HHI_GP0_PLL_CNTL3 0x48 +#define HHI_GP0_PLL_CNTL4 0x4c +#define HHI_GP0_PLL_CNTL5 0x50 +#define HHI_GP0_PLL_STS 0x54 +#define HHI_GP0_PLL_CNTL1 0x58 +#define HHI_HIFI_PLL_CNTL 0x80 +#define HHI_HIFI_PLL_CNTL2 0x84 +#define HHI_HIFI_PLL_CNTL3 0x88 +#define HHI_HIFI_PLL_CNTL4 0x8C +#define HHI_HIFI_PLL_CNTL5 0x90 +#define HHI_HIFI_PLL_STS 0x94 +#define HHI_HIFI_PLL_CNTL1 0x98 + +#define HHI_XTAL_DIVN_CNTL 0xbc +#define HHI_GCLK2_MPEG0 0xc0 +#define HHI_GCLK2_MPEG1 0xc4 +#define HHI_GCLK2_MPEG2 0xc8 +#define HHI_GCLK2_OTHER 0xd0 +#define HHI_GCLK2_AO 0xd4 +#define HHI_PCIE_PLL_CNTL 0xd8 +#define HHI_PCIE_PLL_CNTL1 0xdC +#define HHI_PCIE_PLL_CNTL2 0xe0 +#define HHI_PCIE_PLL_CNTL3 0xe4 +#define HHI_PCIE_PLL_CNTL4 0xe8 +#define HHI_PCIE_PLL_CNTL5 0xec +#define HHI_PCIE_PLL_CNTL6 0xf0 +#define HHI_PCIE_PLL_STS 0xf4 + +#define HHI_MEM_PD_REG0 0x100 +#define HHI_VPU_MEM_PD_REG0 0x104 +#define HHI_VIID_CLK_DIV 0x128 +#define HHI_VIID_CLK_CNTL 0x12c + +#define HHI_GCLK_MPEG0 0x140 +#define HHI_GCLK_MPEG1 0x144 +#define HHI_GCLK_MPEG2 0x148 +#define HHI_GCLK_OTHER 0x150 +#define HHI_GCLK_AO 0x154 +#define HHI_SYS_CPU_CLK_CNTL1 0x15c +#define HHI_SYS_CPU_RESET_CNTL 0x160 +#define HHI_VID_CLK_DIV 0x164 +#define HHI_SPICC_HCLK_CNTL 0x168 + +#define HHI_MPEG_CLK_CNTL 0x174 +#define HHI_VID_CLK_CNTL 0x17c +#define HHI_TS_CLK_CNTL 0x190 +#define HHI_VID_CLK_CNTL2 0x194 +#define HHI_SYS_CPU_CLK_CNTL0 0x19c +#define HHI_VID_PLL_CLK_DIV 0x1a0 +#define HHI_VPU_CLK_CNTL 0x1bC + +#define HHI_VAPBCLK_CNTL 0x1F4 + +#define HHI_GEN_CLK_CNTL 0x228 + +#define HHI_VDIN_MEAS_CLK_CNTL 0x250 +#define HHI_NAND_CLK_CNTL 0x25C +#define HHI_SD_EMMC_CLK_CNTL 0x264 + +#define HHI_MPLL_CNTL 0x280 +#define HHI_MPLL_CNTL2 0x284 +#define HHI_MPLL_CNTL3 0x288 +#define HHI_MPLL_CNTL4 0x28C +#define HHI_MPLL_CNTL5 0x290 +#define HHI_MPLL_CNTL6 0x294 +#define HHI_MPLL_CNTL7 0x298 +#define HHI_MPLL_CNTL8 0x29C +#define HHI_MPLL_CNTL9 0x2A0 +#define HHI_MPLL_CNTL10 0x2A4 + +#define HHI_MPLL3_CNTL0 0x2E0 +#define HHI_MPLL3_CNTL1 0x2E4 +#define HHI_PLL_TOP_MISC 0x2E8 + +#define HHI_SYS_PLL_CNTL1 0x2FC +#define HHI_SYS_PLL_CNTL 0x300 +#define HHI_SYS_PLL_CNTL2 0x304 +#define HHI_SYS_PLL_CNTL3 0x308 +#define HHI_SYS_PLL_CNTL4 0x30c +#define HHI_SYS_PLL_CNTL5 0x310 +#define HHI_SYS_PLL_STS 0x314 +#define HHI_DPLL_TOP_I 0x318 +#define HHI_DPLL_TOP2_I 0x31C + +#endif diff --git a/arch/arm/include/asm/arch-meson/clock.h b/arch/arm/include/asm/arch-meson/clock-gx.h index c0ff00fc9a..13a2e7688f 100644 --- a/arch/arm/include/asm/arch-meson/clock.h +++ b/arch/arm/include/asm/arch-meson/clock-gx.h @@ -3,8 +3,8 @@ * Copyright 2016 - AmLogic, Inc. * Copyright 2018 - Beniamino Galvani <b.galvani@gmail.com> */ -#ifndef _ARCH_MESON_CLOCK_H_ -#define _ARCH_MESON_CLOCK_H_ +#ifndef _ARCH_MESON_CLOCK_GX_H_ +#define _ARCH_MESON_CLOCK_GX_H_ /* * Clock controller register offsets diff --git a/arch/arm/include/asm/arch-meson/eth.h b/arch/arm/include/asm/arch-meson/eth.h index 1aa0872d53..08acc5cbf7 100644 --- a/arch/arm/include/asm/arch-meson/eth.h +++ b/arch/arm/include/asm/arch-meson/eth.h @@ -10,13 +10,13 @@ #include <phy.h> enum { - /* Use GXL Internal RMII PHY */ - MESON_GXL_USE_INTERNAL_RMII_PHY = 1, + /* Use Internal RMII PHY */ + MESON_USE_INTERNAL_RMII_PHY = 1, }; /* Configure the Ethernet MAC with the requested interface mode * with some optional flags. */ -void meson_gx_eth_init(phy_interface_t mode, unsigned int flags); +void meson_eth_init(phy_interface_t mode, unsigned int flags); #endif /* __MESON_ETH_H__ */ diff --git a/arch/arm/include/asm/arch-meson/gx.h b/arch/arm/include/asm/arch-meson/gx.h index 4bc9475d35..b781ba9475 100644 --- a/arch/arm/include/asm/arch-meson/gx.h +++ b/arch/arm/include/asm/arch-meson/gx.h @@ -21,6 +21,7 @@ #define GX_AO_SEC_GP_CFG4 GX_AO_ADDR(0x94) #define GX_AO_SEC_GP_CFG5 GX_AO_ADDR(0x95) +#define GX_AO_BOOT_DEVICE 0xF #define GX_AO_MEM_SIZE_MASK 0xFFFF0000 #define GX_AO_MEM_SIZE_SHIFT 16 #define GX_AO_BL31_RSVMEM_SIZE_MASK 0xFFFF0000 diff --git a/arch/arm/include/asm/arch-meson/mem.h b/arch/arm/include/asm/arch-meson/mem.h index 62818335d9..a65100aeb7 100644 --- a/arch/arm/include/asm/arch-meson/mem.h +++ b/arch/arm/include/asm/arch-meson/mem.h @@ -10,6 +10,7 @@ /* Configure the reserved memory zones exported by the secure registers * into EFI and DTB reserved memory entries. */ -void meson_gx_init_reserved_memory(void *fdt); +void meson_board_add_reserved_memory(void *fdt, u64 start, u64 size); +void meson_init_reserved_memory(void *fdt); #endif /* __MESON_MEM_H__ */ |