diff options
Diffstat (limited to 'arch/arm/include/asm/arch-mx6/imx-regs.h')
| -rw-r--r-- | arch/arm/include/asm/arch-mx6/imx-regs.h | 166 |
1 files changed, 145 insertions, 21 deletions
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 8834c59dcc..dc737ba127 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -200,6 +200,127 @@ struct src { u32 gpr10; }; +/* GPR3 bitfields */ +#define IOMUXC_GPR3_GPU_DBG_OFFSET 29 +#define IOMUXC_GPR3_GPU_DBG_MASK (3<<IOMUXC_GPR3_GPU_DBG_OFFSET) +#define IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET 28 +#define IOMUXC_GPR3_BCH_WR_CACHE_CTL_MASK (1<<IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET) +#define IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET 27 +#define IOMUXC_GPR3_BCH_RD_CACHE_CTL_MASK (1<<IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET) +#define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET 26 +#define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_MASK (1<<IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET) +#define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET 25 +#define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_MASK (1<<IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET) +#define IOMUXC_GPR3_OCRAM_CTL_OFFSET 21 +#define IOMUXC_GPR3_OCRAM_CTL_MASK (0xf<<IOMUXC_GPR3_OCRAM_CTL_OFFSET) +#define IOMUXC_GPR3_OCRAM_STATUS_OFFSET 17 +#define IOMUXC_GPR3_OCRAM_STATUS_MASK (0xf<<IOMUXC_GPR3_OCRAM_STATUS_OFFSET) +#define IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET 16 +#define IOMUXC_GPR3_CORE3_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET) +#define IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET 15 +#define IOMUXC_GPR3_CORE2_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET) +#define IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET 14 +#define IOMUXC_GPR3_CORE1_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET) +#define IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET 13 +#define IOMUXC_GPR3_CORE0_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET) +#define IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET 12 +#define IOMUXC_GPR3_TZASC2_BOOT_LOCK_MASK (1<<IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET) +#define IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET 11 +#define IOMUXC_GPR3_TZASC1_BOOT_LOCK_MASK (1<<IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET) +#define IOMUXC_GPR3_IPU_DIAG_OFFSET 10 +#define IOMUXC_GPR3_IPU_DIAG_MASK (1<<IOMUXC_GPR3_IPU_DIAG_OFFSET) + +#define IOMUXC_GPR3_MUX_SRC_IPU1_DI0 0 +#define IOMUXC_GPR3_MUX_SRC_IPU1_DI1 1 +#define IOMUXC_GPR3_MUX_SRC_IPU2_DI0 2 +#define IOMUXC_GPR3_MUX_SRC_IPU2_DI1 3 + +#define IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET 8 +#define IOMUXC_GPR3_LVDS1_MUX_CTL_MASK (3<<IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET) + +#define IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET 6 +#define IOMUXC_GPR3_LVDS0_MUX_CTL_MASK (3<<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET) + +#define IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET 4 +#define IOMUXC_GPR3_MIPI_MUX_CTL_MASK (3<<IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET) + +#define IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET 2 +#define IOMUXC_GPR3_HDMI_MUX_CTL_MASK (3<<IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET) + + +struct iomuxc { + u32 gpr[14]; + u32 omux[5]; + /* mux and pad registers */ +}; + +#define IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET 20 +#define IOMUXC_GPR2_COUNTER_RESET_VAL_MASK (3<<IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET) +#define IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET 16 +#define IOMUXC_GPR2_LVDS_CLK_SHIFT_MASK (7<<IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET) + +#define IOMUXC_GPR2_BGREF_RRMODE_OFFSET 15 +#define IOMUXC_GPR2_BGREF_RRMODE_MASK (1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET) +#define IOMUXC_GPR2_BGREF_RRMODE_INTERNAL_RES (1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET) +#define IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES (0<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET) +#define IOMUXC_GPR2_VSYNC_ACTIVE_HIGH 0 +#define IOMUXC_GPR2_VSYNC_ACTIVE_LOW 1 + +#define IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET 10 +#define IOMUXC_GPR2_DI1_VS_POLARITY_MASK (1<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET) +#define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET) +#define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW (IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET) + +#define IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET 9 +#define IOMUXC_GPR2_DI0_VS_POLARITY_MASK (1<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET) +#define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET) +#define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW (IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET) + +#define IOMUXC_GPR2_BITMAP_SPWG 0 +#define IOMUXC_GPR2_BITMAP_JEIDA 1 + +#define IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET 8 +#define IOMUXC_GPR2_BIT_MAPPING_CH1_MASK (1<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET) +#define IOMUXC_GPR2_BIT_MAPPING_CH1_JEIDA (IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET) +#define IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG (IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET) + +#define IOMUXC_GPR2_DATA_WIDTH_18 0 +#define IOMUXC_GPR2_DATA_WIDTH_24 1 + +#define IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET 7 +#define IOMUXC_GPR2_DATA_WIDTH_CH1_MASK (1<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET) +#define IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT (IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET) +#define IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT (IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET) + +#define IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET 6 +#define IOMUXC_GPR2_BIT_MAPPING_CH0_MASK (1<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET) +#define IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA (IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET) +#define IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG (IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET) + +#define IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET 5 +#define IOMUXC_GPR2_DATA_WIDTH_CH0_MASK (1<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET) +#define IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT (IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET) +#define IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT (IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET) + +#define IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET 4 +#define IOMUXC_GPR2_SPLIT_MODE_EN_MASK (1<<IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET) + +#define IOMUXC_GPR2_MODE_DISABLED 0 +#define IOMUXC_GPR2_MODE_ENABLED_DI0 1 +#define IOMUXC_GPR2_MODE_ENABLED_DI1 2 + +#define IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET 2 +#define IOMUXC_GPR2_LVDS_CH1_MODE_MASK (3<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET) +#define IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED (IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET) +#define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET) +#define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET) + +#define IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET 0 +#define IOMUXC_GPR2_LVDS_CH0_MODE_MASK (3<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) +#define IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED (IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) +#define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) +#define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) + /* ECSPI registers */ struct cspi_regs { u32 rxdata; @@ -439,6 +560,30 @@ struct anatop_regs { u32 digprog; /* 0x260 */ }; +#define ANATOP_PFD_480_PFD0_FRAC_SHIFT 0 +#define ANATOP_PFD_480_PFD0_FRAC_MASK (0x3f<<ANATOP_PFD_480_PFD0_FRAC_SHIFT) +#define ANATOP_PFD_480_PFD0_STABLE_SHIFT 6 +#define ANATOP_PFD_480_PFD0_STABLE_MASK (1<<ANATOP_PFD_480_PFD0_STABLE_SHIFT) +#define ANATOP_PFD_480_PFD0_CLKGATE_SHIFT 7 +#define ANATOP_PFD_480_PFD0_CLKGATE_MASK (1<<ANATOP_PFD_480_PFD0_CLKGATE_SHIFT) +#define ANATOP_PFD_480_PFD1_FRAC_SHIFT 8 +#define ANATOP_PFD_480_PFD1_FRAC_MASK (0x3f<<ANATOP_PFD_480_PFD1_FRAC_SHIFT) +#define ANATOP_PFD_480_PFD1_STABLE_SHIFT 14 +#define ANATOP_PFD_480_PFD1_STABLE_MASK (1<<ANATOP_PFD_480_PFD1_STABLE_SHIFT) +#define ANATOP_PFD_480_PFD1_CLKGATE_SHIFT 15 +#define ANATOP_PFD_480_PFD1_CLKGATE_MASK (0x3f<<ANATOP_PFD_480_PFD1_CLKGATE_SHIFT) +#define ANATOP_PFD_480_PFD2_FRAC_SHIFT 16 +#define ANATOP_PFD_480_PFD2_FRAC_MASK (1<<ANATOP_PFD_480_PFD2_FRAC_SHIFT) +#define ANATOP_PFD_480_PFD2_STABLE_SHIFT 22 +#define ANATOP_PFD_480_PFD2_STABLE_MASK (1<<ANATOP_PFD_480_PFD2_STABLE_SHIFT) +#define ANATOP_PFD_480_PFD2_CLKGATE_SHIFT 23 +#define ANATOP_PFD_480_PFD2_CLKGATE_MASK (0x3f<<ANATOP_PFD_480_PFD2_CLKGATE_SHIFT) +#define ANATOP_PFD_480_PFD3_FRAC_SHIFT 24 +#define ANATOP_PFD_480_PFD3_FRAC_MASK (1<<ANATOP_PFD_480_PFD3_FRAC_SHIFT) +#define ANATOP_PFD_480_PFD3_STABLE_SHIFT 30 +#define ANATOP_PFD_480_PFD3_STABLE_MASK (1<<ANATOP_PFD_480_PFD3_STABLE_SHIFT) +#define ANATOP_PFD_480_PFD3_CLKGATE_SHIFT 31 + struct iomuxc_base_regs { u32 gpr[14]; /* 0x000 */ u32 obsrv[5]; /* 0x038 */ @@ -448,26 +593,5 @@ struct iomuxc_base_regs { u32 daisy[104]; /* 0x7b0..94c */ }; -struct src_regs { - u32 scr; /* 0x00 */ - u32 sbmr1; /* 0x04 */ - u32 srsr; /* 0x08 */ - u32 reserved1; /* 0x0c */ - u32 reserved2; /* 0x10 */ - u32 sisr; /* 0x14 */ - u32 simr; /* 0x18 */ - u32 sbmr2; /* 0x1c */ - u32 gpr1; /* 0x20 */ - u32 gpr2; /* 0x24 */ - u32 gpr3; /* 0x28 */ - u32 gpr4; /* 0x2c */ - u32 gpr5; /* 0x30 */ - u32 gpr6; /* 0x34 */ - u32 gpr7; /* 0x38 */ - u32 gpr8; /* 0x3c */ - u32 gpr9; /* 0x40 */ - u32 gpr10; /* 0x44 */ -}; - #endif /* __ASSEMBLER__*/ #endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */ |