3 files changed, 25 insertions, 72 deletions
diff --git a/arch/arm/include/asm/arch-stm32f7/rcc.h b/arch/arm/include/asm/arch-stm32f7/rcc.h
deleted file mode 100644
index 6475f9d5c8..0000000000
--- a/arch/arm/include/asm/arch-stm32f7/rcc.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
- * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _STM32_RCC_H
-#define _STM32_RCC_H
-
-#include <dt-bindings/mfd/stm32f7-rcc.h>
-
-/*
- * RCC AHB1ENR specific definitions
- */
-#define RCC_AHB1ENR_ETHMAC_EN		BIT(25)
-#define RCC_AHB1ENR_ETHMAC_TX_EN	BIT(26)
-#define RCC_AHB1ENR_ETHMAC_RX_EN	BIT(27)
-
-/*
- * RCC APB1ENR specific definitions
- */
-#define RCC_APB1ENR_TIM2EN		BIT(0)
-#define RCC_APB1ENR_PWREN		BIT(28)
-
-/*
- * RCC APB2ENR specific definitions
- */
-#define RCC_APB2ENR_SYSCFGEN		BIT(14)
-
-#endif
diff --git a/arch/arm/include/asm/arch-stm32f7/stm32.h b/arch/arm/include/asm/arch-stm32f7/stm32.h
index d6412a00cc..f54e6f1955 100644
--- a/arch/arm/include/asm/arch-stm32f7/stm32.h
+++ b/arch/arm/include/asm/arch-stm32f7/stm32.h
@@ -59,49 +59,8 @@ static const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT] = {
 
 #define STM32_BUS_MASK		GENMASK(31, 16)
 
-struct stm32_rcc_regs {
-	u32 cr;		/* RCC clock control */
-	u32 pllcfgr;	/* RCC PLL configuration */
-	u32 cfgr;	/* RCC clock configuration */
-	u32 cir;	/* RCC clock interrupt */
-	u32 ahb1rstr;	/* RCC AHB1 peripheral reset */
-	u32 ahb2rstr;	/* RCC AHB2 peripheral reset */
-	u32 ahb3rstr;	/* RCC AHB3 peripheral reset */
-	u32 rsv0;
-	u32 apb1rstr;	/* RCC APB1 peripheral reset */
-	u32 apb2rstr;	/* RCC APB2 peripheral reset */
-	u32 rsv1[2];
-	u32 ahb1enr;	/* RCC AHB1 peripheral clock enable */
-	u32 ahb2enr;	/* RCC AHB2 peripheral clock enable */
-	u32 ahb3enr;	/* RCC AHB3 peripheral clock enable */
-	u32 rsv2;
-	u32 apb1enr;	/* RCC APB1 peripheral clock enable */
-	u32 apb2enr;	/* RCC APB2 peripheral clock enable */
-	u32 rsv3[2];
-	u32 ahb1lpenr;	/* RCC AHB1 periph clk enable in low pwr mode */
-	u32 ahb2lpenr;	/* RCC AHB2 periph clk enable in low pwr mode */
-	u32 ahb3lpenr;	/* RCC AHB3 periph clk enable in low pwr mode */
-	u32 rsv4;
-	u32 apb1lpenr;	/* RCC APB1 periph clk enable in low pwr mode */
-	u32 apb2lpenr;	/* RCC APB2 periph clk enable in low pwr mode */
-	u32 rsv5[2];
-	u32 bdcr;	/* RCC Backup domain control */
-	u32 csr;	/* RCC clock control & status */
-	u32 rsv6[2];
-	u32 sscgr;	/* RCC spread spectrum clock generation */
-	u32 plli2scfgr;	/* RCC PLLI2S configuration */
-	u32 pllsaicfgr;	/* PLLSAI configuration */
-	u32 dckcfgr;	/* dedicated clocks configuration register */
-};
 #define STM32_RCC		((struct stm32_rcc_regs *)RCC_BASE)
 
-struct stm32_pwr_regs {
-	u32 cr1;   /* power control register 1 */
-	u32 csr1;  /* power control/status register 2 */
-	u32 cr2;   /* power control register 2 */
-	u32 csr2;  /* power control/status register 2 */
-};
-#define STM32_PWR		((struct stm32_pwr_regs *)PWR_BASE)
 
 void stm32_flash_latency_cfg(int latency);
 
diff --git a/arch/arm/include/asm/arch-stm32f7/stm32_pwr.h b/arch/arm/include/asm/arch-stm32f7/stm32_pwr.h
new file mode 100644
index 0000000000..917dd46d98
--- /dev/null
+++ b/arch/arm/include/asm/arch-stm32f7/stm32_pwr.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+ * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __STM32_PWR_H_
+
+/*
+ * Offsets of some PWR registers
+ */
+#define PWR_CR1_ODEN			BIT(16)
+#define PWR_CR1_ODSWEN			BIT(17)
+#define PWR_CSR1_ODRDY			BIT(16)
+#define PWR_CSR1_ODSWRDY		BIT(17)
+
+struct stm32_pwr_regs {
+	u32 cr1;   /* power control register 1 */
+	u32 csr1;  /* power control/status register 2 */
+	u32 cr2;   /* power control register 2 */
+	u32 csr2;  /* power control/status register 2 */
+};
+
+#endif /* __STM32_PWR_H_ */