diff options
Diffstat (limited to 'arch/arm/include/asm/arch-sunxi/cpu.h')
| -rw-r--r-- | arch/arm/include/asm/arch-sunxi/cpu.h | 32 |
1 files changed, 27 insertions, 5 deletions
diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h b/arch/arm/include/asm/arch-sunxi/cpu.h index 0de79a0d50..82b3d4676f 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu.h +++ b/arch/arm/include/asm/arch-sunxi/cpu.h @@ -37,16 +37,24 @@ #define SUNXI_MMC1_BASE 0x01c10000 #define SUNXI_MMC2_BASE 0x01c11000 #define SUNXI_MMC3_BASE 0x01c12000 +#if !defined CONFIG_MACH_SUN6I && !defined CONFIG_MACH_SUN8I #define SUNXI_USB0_BASE 0x01c13000 #define SUNXI_USB1_BASE 0x01c14000 +#endif #define SUNXI_SS_BASE 0x01c15000 #define SUNXI_HDMI_BASE 0x01c16000 #define SUNXI_SPI2_BASE 0x01c17000 #define SUNXI_SATA_BASE 0x01c18000 +#if !defined CONFIG_MACH_SUN6I && !defined CONFIG_MACH_SUN8I #define SUNXI_PATA_BASE 0x01c19000 #define SUNXI_ACE_BASE 0x01c1a000 #define SUNXI_TVE1_BASE 0x01c1b000 #define SUNXI_USB2_BASE 0x01c1c000 +#else +#define SUNXI_USB0_BASE 0x01c19000 +#define SUNXI_USB1_BASE 0x01c1a000 +#define SUNXI_USB2_BASE 0x01c1b000 +#endif #define SUNXI_CSI1_BASE 0x01c1d000 #define SUNXI_TZASC_BASE 0x01c1e000 #define SUNXI_SPI3_BASE 0x01c1f000 @@ -70,7 +78,7 @@ #define SUNXI_TP_BASE 0x01c25000 #define SUNXI_PMU_BASE 0x01c25400 -#define SUNXI_CPUCFG_BASE 0x01c25c00 +#define SUN7I_CPUCFG_BASE 0x01c25c00 #define SUNXI_UART0_BASE 0x01c28000 #define SUNXI_UART1_BASE 0x01c28400 @@ -91,14 +99,19 @@ #define SUNXI_SCR_BASE 0x01c2c400 +#ifndef CONFIG_MACH_SUN6I #define SUNXI_GPS_BASE 0x01c30000 #define SUNXI_MALI400_BASE 0x01c40000 #define SUNXI_GMAC_BASE 0x01c50000 +#else +#define SUNXI_GMAC_BASE 0x01c30000 +#endif #define SUNXI_DRAM_COM_BASE 0x01c62000 -#define SUNXI_DRAM_CTL_BASE 0x01c63000 -#define SUNXI_DRAM_PHY_CH1_BASE 0x01c65000 -#define SUNXI_DRAM_PHY_CH2_BASE 0x01c66000 +#define SUNXI_DRAM_CTL0_BASE 0x01c63000 +#define SUNXI_DRAM_CTL1_BASE 0x01c64000 +#define SUNXI_DRAM_PHY0_BASE 0x01c65000 +#define SUNXI_DRAM_PHY1_BASE 0x01c66000 /* module sram */ #define SUNXI_SRAM_C_BASE 0x01d00000 @@ -110,10 +123,13 @@ #define SUNXI_MP_BASE 0x01e80000 #define SUNXI_AVG_BASE 0x01ea0000 +#define SUNXI_RTC_BASE 0x01f00000 #define SUNXI_PRCM_BASE 0x01f01400 +#define SUN6I_CPUCFG_BASE 0x01f01c00 #define SUNXI_R_UART_BASE 0x01f02800 #define SUNXI_R_PIO_BASE 0x01f02c00 -#define SUNXI_P2WI_BASE 0x01f03400 +#define SUN6I_P2WI_BASE 0x01f03400 +#define SUNXI_RSB_BASE 0x01f03400 /* CoreSight Debug Module */ #define SUNXI_CSDM_BASE 0x3f500000 @@ -124,9 +140,15 @@ #define SUNXI_CPU_CFG (SUNXI_TIMER_BASE + 0x13c) +/* SS bonding ids used for cpu identification */ +#define SUNXI_SS_BOND_ID_A31 4 +#define SUNXI_SS_BOND_ID_A31S 5 + #ifndef __ASSEMBLY__ void sunxi_board_init(void); void sunxi_reset(void); +int sunxi_get_ss_bonding_id(void); +int sunxi_get_sid(unsigned int *sid); #endif /* __ASSEMBLY__ */ #endif /* _CPU_H */ |