8 files changed, 36 insertions, 2 deletions
diff --git a/arch/arm/include/asm/arch-sunxi/clock.h b/arch/arm/include/asm/arch-sunxi/clock.h
index 8ca58ae521..6c0573fe58 100644
--- a/arch/arm/include/asm/arch-sunxi/clock.h
+++ b/arch/arm/include/asm/arch-sunxi/clock.h
@@ -30,6 +30,7 @@ int clock_init(void);
 int clock_twi_onoff(int port, int state);
 void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz);
 void clock_init_safe(void);
+void clock_init_sec(void);
 void clock_init_uart(void);
 #endif
 
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index 5c76275112..554d8589ed 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -137,6 +137,8 @@ struct sunxi_ccm_reg {
 	u32 apb1_reset_cfg;	/* 0x2d0 APB1 Reset config */
 	u32 reserved24;
 	u32 apb2_reset_cfg;	/* 0x2d8 APB2 Reset config */
+	u32 reserved25[5];
+	u32 ccu_sec_switch;	/* 0x2f0 CCU Security Switch, H3 only */
 };
 
 /* apb2 bit field */
@@ -375,6 +377,11 @@ struct sunxi_ccm_reg {
 #define CCM_DE_CTRL_PLL10		(5 << 24)
 #define CCM_DE_CTRL_GATE		(1 << 31)
 
+/* CCU security switch, H3 only */
+#define CCM_SEC_SWITCH_MBUS_NONSEC	(1 << 2)
+#define CCM_SEC_SWITCH_BUS_NONSEC	(1 << 1)
+#define CCM_SEC_SWITCH_PLL_NONSEC	(1 << 0)
+
 #ifndef __ASSEMBLY__
 void clock_set_pll1(unsigned int hz);
 void clock_set_pll3(unsigned int hz);
diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
index 63b161ab03..0cdefdcdf4 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
@@ -134,6 +134,7 @@
 #define SUNXI_RTC_BASE			0x01f00000
 #define SUNXI_PRCM_BASE			0x01f01400
 #define SUN6I_CPUCFG_BASE		0x01f01c00
+#define SUNXI_R_TWI_BASE		0x01f02400
 #define SUNXI_R_UART_BASE		0x01f02800
 #define SUNXI_R_PIO_BASE		0x01f02c00
 #define SUN6I_P2WI_BASE			0x01f03400
diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun8i_a83t.h b/arch/arm/include/asm/arch-sunxi/dram_sun8i_a83t.h
index 2891b71b33..842ad3cc63 100644
--- a/arch/arm/include/asm/arch-sunxi/dram_sun8i_a83t.h
+++ b/arch/arm/include/asm/arch-sunxi/dram_sun8i_a83t.h
@@ -186,7 +186,7 @@ struct sunxi_mctl_ctl_reg {
 #define MCTL_CR_BUSW8			(0 << 12)
 #define MCTL_CR_BUSW16			(1 << 12)
 #define MCTL_CR_SEQUENCE		(1 << 15)
-#define MCTL_CR_DDR3			(3 << 16)
+#define MCTL_CR_DRAM_TYPE(x)		((x) << 16)
 #define MCTL_CR_CHANNEL_MASK		(1 << 19)
 #define MCTL_CR_CHANNEL(x)		(((x) - 1) << 19)
 #define MCTL_CR_UNKNOWN			(0x4 << 20)
@@ -198,4 +198,11 @@ struct sunxi_mctl_ctl_reg {
 #define MCTL_MR2			0x18 /* CWL=8 */
 #define MCTL_MR3			0x0
 
+#define MCTL_LPDDR3_MR0			0x0
+#define MCTL_LPDDR3_MR1			0xc3	/* twr=8, bl=8 */
+#define MCTL_LPDDR3_MR2			0xa	/* RL=12, CWL=6 */
+#define MCTL_LPDDR3_MR3			0x0
+
+#define DRAM_TYPE_DDR3		3
+#define DRAM_TYPE_LPDDR3	7
 #endif /* _SUNXI_DRAM_SUN8I_A83T_H */
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h
index a2a9a38dbe..649f6cd840 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -199,6 +199,8 @@ enum sunxi_gpio_number {
 #define SUN6I_GPL1_R_P2WI_SDA	3
 
 #define SUN8I_GPL_R_RSB		2
+#define SUN8I_H3_GPL_R_TWI	2
+#define SUN8I_A23_GPL_R_TWI	3
 #define SUN8I_GPL_R_UART	2
 
 #define SUN9I_GPN_R_RSB		3
diff --git a/arch/arm/include/asm/arch-sunxi/i2c.h b/arch/arm/include/asm/arch-sunxi/i2c.h
index 561cd2be16..4dfd313f1a 100644
--- a/arch/arm/include/asm/arch-sunxi/i2c.h
+++ b/arch/arm/include/asm/arch-sunxi/i2c.h
@@ -23,6 +23,9 @@
 #ifdef CONFIG_I2C4_ENABLE
 #define CONFIG_I2C_MVTWSI_BASE4	SUNXI_TWI4_BASE
 #endif
+#ifdef CONFIG_R_I2C_ENABLE
+#define CONFIG_I2C_MVTWSI_BASE5 SUNXI_R_TWI_BASE
+#endif
 
 /* This is abp0-clk on sun4i/5i/7i / abp1-clk on sun6i/sun8i which is 24MHz */
 #define CONFIG_SYS_TCLK		24000000
diff --git a/arch/arm/include/asm/arch-sunxi/prcm.h b/arch/arm/include/asm/arch-sunxi/prcm.h
index 82ed541e91..556c1af600 100644
--- a/arch/arm/include/asm/arch-sunxi/prcm.h
+++ b/arch/arm/include/asm/arch-sunxi/prcm.h
@@ -236,5 +236,7 @@ struct sunxi_prcm_reg {
 };
 
 void prcm_apb0_enable(u32 flags);
+void prcm_apb0_disable(u32 flags);
+
 #endif /* __ASSEMBLY__ */
 #endif /* _PRCM_H */
diff --git a/arch/arm/include/asm/arch-sunxi/tzpc.h b/arch/arm/include/asm/arch-sunxi/tzpc.h
index ba4d43bc3a..95c55cd4d1 100644
--- a/arch/arm/include/asm/arch-sunxi/tzpc.h
+++ b/arch/arm/include/asm/arch-sunxi/tzpc.h
@@ -13,10 +13,21 @@ struct sunxi_tzpc {
 	u32 decport0_status;	/* 0x04 Status of decode protection port 0 */
 	u32 decport0_set;	/* 0x08 Set decode protection port 0 */
 	u32 decport0_clear;	/* 0x0c Clear decode protection port 0 */
+	/* For A80 and later SoCs */
+	u32 decport1_status;	/* 0x10 Status of decode protection port 1 */
+	u32 decport1_set;	/* 0x14 Set decode protection port 1 */
+	u32 decport1_clear;	/* 0x18 Clear decode protection port 1 */
+	u32 decport2_status;	/* 0x1c Status of decode protection port 2 */
+	u32 decport2_set;	/* 0x20 Set decode protection port 2 */
+	u32 decport2_clear;	/* 0x24 Clear decode protection port 2 */
 };
 #endif
 
-#define SUNXI_TZPC_DECPORT0_RTC	(1 << 1)
+#define SUN6I_TZPC_DECPORT0_RTC	(1 << 1)
+
+#define SUN8I_H3_TZPC_DECPORT0_ALL  0xbe
+#define SUN8I_H3_TZPC_DECPORT1_ALL  0xff
+#define SUN8I_H3_TZPC_DECPORT2_ALL  0x7f
 
 void tzpc_init(void);