4 files changed, 68 insertions, 38 deletions
diff --git a/arch/arm/include/asm/arch-tegra/ap.h b/arch/arm/include/asm/arch-tegra/ap.h
index 76773b7ec7..8c2586c6f5 100644
--- a/arch/arm/include/asm/arch-tegra/ap.h
+++ b/arch/arm/include/asm/arch-tegra/ap.h
@@ -64,15 +64,6 @@ int tegra_get_sku_info(void);
 /* Do any chip-specific cache config */
 void config_cache(void);
 
-#if defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210)
-/* Do chip-specific vpr config */
-void config_vpr(void);
-#else
-static inline void config_vpr(void)
-{
-}
-#endif
-
 #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
 bool tegra_cpu_is_non_secure(void);
 #endif
diff --git a/arch/arm/include/asm/arch-tegra/clk_rst.h b/arch/arm/include/asm/arch-tegra/clk_rst.h
index f69026002b..ee9436e2e5 100644
--- a/arch/arm/include/asm/arch-tegra/clk_rst.h
+++ b/arch/arm/include/asm/arch-tegra/clk_rst.h
@@ -249,17 +249,6 @@ struct clk_rst_ctlr {
 #define PLL_LOCK_SHIFT		27
 #define PLL_LOCK_MASK		(1U << PLL_LOCK_SHIFT)
 
-#define PLL_DIVP_SHIFT		20
-#define PLL_DIVP_MASK		(7U << PLL_DIVP_SHIFT)
-/* Special case for T210 PLLU DIVP */
-#define PLLU_DIVP_SHIFT		16
-
-#define PLL_DIVN_SHIFT		8
-#define PLL_DIVN_MASK		(0x3ffU << PLL_DIVN_SHIFT)
-
-#define PLL_DIVM_SHIFT		0
-#define PLL_DIVM_MASK		(0x1f << PLL_DIVM_SHIFT)
-
 /* CLK_RST_CONTROLLER_PLLx_OUTx_0 */
 #define PLL_OUT_RSTN		(1 << 0)
 #define PLL_OUT_CLKEN		(1 << 1)
@@ -272,24 +261,6 @@ struct clk_rst_ctlr {
 #define PLL_DCCON_SHIFT		20
 #define PLL_DCCON_MASK		(1U << PLL_DCCON_SHIFT)
 
-#define PLL_LOCK_ENABLE_SHIFT	18
-#define PLL_LOCK_ENABLE_MASK	(1U << PLL_LOCK_ENABLE_SHIFT)
-
-#define PLL_CPCON_SHIFT		8
-#define PLL_CPCON_MASK		(15U << PLL_CPCON_SHIFT)
-
-#define PLL_LFCON_SHIFT		4
-#define PLL_LFCON_MASK		(15U << PLL_LFCON_SHIFT)
-
-/* CPCON/LFCON replaced by KCP/KVCO in T210 PLLU */
-#define PLLU_KVCO_SHIFT		24
-#define PLLU_KVCO_MASK		(3U << PLLU_KVCO_SHIFT)
-#define PLLU_KCP_SHIFT		25
-#define PLLU_KCP_MASK		(1U << PLLU_KCP_SHIFT)
-
-#define PLLU_VCO_FREQ_SHIFT	20
-#define PLLU_VCO_FREQ_MASK	(1U << PLLU_VCO_FREQ_SHIFT)
-
 #define PLLP_OUT1_OVR		(1 << 2)
 #define PLLP_OUT2_OVR		(1 << 18)
 #define PLLP_OUT3_OVR		(1 << 2)
@@ -475,4 +446,7 @@ enum {
 #define PLLDP_SS_CFG_UNDOCUMENTED	(1 << 24)
 #define PLLDP_SS_CFG_DITHER		(1 << 28)
 
+/* CLK_RST_PLLD_MISC */
+#define PLLD_CLKENABLE			30
+
 #endif	/* _TEGRA_CLK_RST_H_ */
diff --git a/arch/arm/include/asm/arch-tegra/clock.h b/arch/arm/include/asm/arch-tegra/clock.h
index f9dd3c817d..d570d7f134 100644
--- a/arch/arm/include/asm/arch-tegra/clock.h
+++ b/arch/arm/include/asm/arch-tegra/clock.h
@@ -16,6 +16,8 @@ enum clock_osc_freq {
 	CLOCK_OSC_FREQ_19_2,
 	CLOCK_OSC_FREQ_12_0,
 	CLOCK_OSC_FREQ_26_0,
+	CLOCK_OSC_FREQ_38_4,
+	CLOCK_OSC_FREQ_48_0,
 
 	CLOCK_OSC_FREQ_COUNT,
 };
@@ -336,6 +338,27 @@ void arch_timer_init(void);
 
 void tegra30_set_up_pllp(void);
 
+/* Number of PLL-based clocks (i.e. not OSC or 32KHz) */
+#define CLOCK_ID_PLL_COUNT	(CLOCK_ID_COUNT - 2)
+
+struct clk_pll_info {
+	u32	m_shift:5;	/* DIVM_SHIFT */
+	u32	n_shift:5;	/* DIVN_SHIFT */
+	u32	p_shift:5;	/* DIVP_SHIFT */
+	u32	kcp_shift:5;	/* KCP/cpcon SHIFT */
+	u32	kvco_shift:5;	/* KVCO/lfcon SHIFT */
+	u32	lock_ena:6;	/* LOCK_ENABLE/EN_LOCKDET shift */
+	u32	rsvd:1;
+	u32	m_mask:10;	/* DIVM_MASK */
+	u32	n_mask:12;	/* DIVN_MASK */
+	u32	p_mask:10;	/* DIVP_MASK or VCO_MASK */
+	u32	kcp_mask:10;	/* KCP/CPCON MASK */
+	u32	kvco_mask:10;	/* KVCO/LFCON MASK */
+	u32	lock_det:6;	/* LOCK_DETECT/LOCKED shift */
+	u32	rsvd2:6;
+};
+extern struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT];
+
 /**
  * Enable output clock for external peripherals
  *
diff --git a/arch/arm/include/asm/arch-tegra/gpu.h b/arch/arm/include/asm/arch-tegra/gpu.h
new file mode 100644
index 0000000000..52280f40ce
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra/gpu.h
@@ -0,0 +1,42 @@
+/*
+ *  (C) Copyright 2015
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_TEGRA_GPU_H
+#define __ASM_ARCH_TEGRA_GPU_H
+
+#if defined(CONFIG_TEGRA_GPU)
+
+void config_gpu(void);
+bool gpu_configured(void);
+
+#else /* CONFIG_TEGRA_GPU */
+
+static inline void config_gpu(void)
+{
+}
+
+static inline bool gpu_configured(void)
+{
+	return false;
+}
+
+#endif /* CONFIG_TEGRA_GPU */
+
+#if defined(CONFIG_OF_LIBFDT)
+
+int gpu_enable_node(void *blob, const char *gpupath);
+
+#else /* CONFIG_OF_LIBFDT */
+
+static inline int gpu_enable_node(void *blob, const char *gpupath)
+{
+	return 0;
+}
+
+#endif /* CONFIG_OF_LIBFDT */
+
+#endif	/* __ASM_ARCH_TEGRA_GPU_H */