4 files changed, 79 insertions, 40 deletions

diff --git a/arch/arm/include/asm/arch-uniphier/boot-device.h b/arch/arm/include/asm/arch-uniphier/boot-device.h
index 6987f57669..7a10f1c5b2 100644
--- a/arch/arm/include/asm/arch-uniphier/boot-device.h
+++ b/arch/arm/include/asm/arch-uniphier/boot-device.h
@@ -8,7 +8,7 @@
 #ifndef _ASM_BOOT_DEVICE_H_
 #define _ASM_BOOT_DEVICE_H_
 
-u32 get_boot_mode_sel(void);
+int get_boot_mode_sel(void);
 
 struct boot_device_info {
 	u32 type;
diff --git a/arch/arm/include/asm/arch-uniphier/ddrphy-regs.h b/arch/arm/include/asm/arch-uniphier/ddrphy-regs.h
index 484559c6cd..6b7d600a9c 100644
--- a/arch/arm/include/asm/arch-uniphier/ddrphy-regs.h
+++ b/arch/arm/include/asm/arch-uniphier/ddrphy-regs.h
@@ -72,7 +72,7 @@ struct ddrphy {
 		u32 gtr;	/* General Timing Register */
 		u32 rsv[3];	/* Reserved */
 	} dx[9];
-} __packed;
+};
 
 #endif /* __ASSEMBLY__ */
 
diff --git a/arch/arm/include/asm/arch-uniphier/gpio.h b/arch/arm/include/asm/arch-uniphier/gpio.h
deleted file mode 100644
index 1fc4e19a61..0000000000
--- a/arch/arm/include/asm/arch-uniphier/gpio.h
+++ /dev/null
@@ -1,6 +0,0 @@
-/*
- * Dummy header file to enable CONFIG_OF_CONTROL.
- * If CONFIG_OF_CONTROL is enabled, lib/fdtdec.c is compiled.
- * It includes <asm/arch/gpio.h> via <asm/gpio.h>, so those SoCs that enable
- * OF_CONTROL must have arch/gpio.h even if GPIO is not supported.
- */
diff --git a/arch/arm/include/asm/arch-uniphier/sg-regs.h b/arch/arm/include/asm/arch-uniphier/sg-regs.h
index fa5e6ae0f2..4ae67c8adb 100644
--- a/arch/arm/include/asm/arch-uniphier/sg-regs.h
+++ b/arch/arm/include/asm/arch-uniphier/sg-regs.h
@@ -25,22 +25,29 @@
 /* Memory Configuration */
 #define SG_MEMCONF			(SG_CTRL_BASE | 0x0400)
 
-#define SG_MEMCONF_CH0_SIZE_64MB	((0x0 << 10) | (0x01 << 0))
-#define SG_MEMCONF_CH0_SIZE_128MB	((0x0 << 10) | (0x02 << 0))
-#define SG_MEMCONF_CH0_SIZE_256MB	((0x0 << 10) | (0x03 << 0))
-#define SG_MEMCONF_CH0_SIZE_512MB	((0x1 << 10) | (0x00 << 0))
-#define SG_MEMCONF_CH0_SIZE_1024MB	((0x1 << 10) | (0x01 << 0))
+#define SG_MEMCONF_CH0_SZ_64M		((0x0 << 10) | (0x01 << 0))
+#define SG_MEMCONF_CH0_SZ_128M		((0x0 << 10) | (0x02 << 0))
+#define SG_MEMCONF_CH0_SZ_256M		((0x0 << 10) | (0x03 << 0))
+#define SG_MEMCONF_CH0_SZ_512M		((0x1 << 10) | (0x00 << 0))
+#define SG_MEMCONF_CH0_SZ_1G		((0x1 << 10) | (0x01 << 0))
 #define SG_MEMCONF_CH0_NUM_1		(0x1 << 8)
 #define SG_MEMCONF_CH0_NUM_2		(0x0 << 8)
 
-#define SG_MEMCONF_CH1_SIZE_64MB	((0x0 << 11) | (0x01 << 2))
-#define SG_MEMCONF_CH1_SIZE_128MB	((0x0 << 11) | (0x02 << 2))
-#define SG_MEMCONF_CH1_SIZE_256MB	((0x0 << 11) | (0x03 << 2))
-#define SG_MEMCONF_CH1_SIZE_512MB	((0x1 << 11) | (0x00 << 2))
-#define SG_MEMCONF_CH1_SIZE_1024MB	((0x1 << 11) | (0x01 << 2))
+#define SG_MEMCONF_CH1_SZ_64M		((0x0 << 11) | (0x01 << 2))
+#define SG_MEMCONF_CH1_SZ_128M		((0x0 << 11) | (0x02 << 2))
+#define SG_MEMCONF_CH1_SZ_256M		((0x0 << 11) | (0x03 << 2))
+#define SG_MEMCONF_CH1_SZ_512M		((0x1 << 11) | (0x00 << 2))
+#define SG_MEMCONF_CH1_SZ_1G		((0x1 << 11) | (0x01 << 2))
 #define SG_MEMCONF_CH1_NUM_1		(0x1 << 9)
 #define SG_MEMCONF_CH1_NUM_2		(0x0 << 9)
 
+#define SG_MEMCONF_CH2_SZ_64M		((0x0 << 26) | (0x01 << 16))
+#define SG_MEMCONF_CH2_SZ_128M		((0x0 << 26) | (0x02 << 16))
+#define SG_MEMCONF_CH2_SZ_256M		((0x0 << 26) | (0x03 << 16))
+#define SG_MEMCONF_CH2_SZ_512M		((0x1 << 26) | (0x00 << 16))
+#define SG_MEMCONF_CH2_NUM_1		(0x1 << 24)
+#define SG_MEMCONF_CH2_NUM_2		(0x0 << 24)
+
 #define SG_MEMCONF_SPARSEMEM		(0x1 << 4)
 
 /* Pin Control */
@@ -101,6 +108,7 @@
 #else
 
 #include <linux/types.h>
+#include <linux/sizes.h>
 #include <asm/io.h>
 
 static inline void sg_set_pinsel(int n, int value)
@@ -111,24 +119,24 @@ static inline void sg_set_pinsel(int n, int value)
 
 static inline u32 sg_memconf_val_ch0(unsigned long size, int num)
 {
-	int size_mb = (size >> 20) / num;
+	int size_mb = size / num;
 	u32 ret;
 
 	switch (size_mb) {
-	case 64:
-		ret = SG_MEMCONF_CH0_SIZE_64MB;
+	case SZ_64M:
+		ret = SG_MEMCONF_CH0_SZ_64M;
 		break;
-	case 128:
-		ret = SG_MEMCONF_CH0_SIZE_128MB;
+	case SZ_128M:
+		ret = SG_MEMCONF_CH0_SZ_128M;
 		break;
-	case 256:
-		ret = SG_MEMCONF_CH0_SIZE_256MB;
+	case SZ_256M:
+		ret = SG_MEMCONF_CH0_SZ_256M;
 		break;
-	case 512:
-		ret = SG_MEMCONF_CH0_SIZE_512MB;
+	case SZ_512M:
+		ret = SG_MEMCONF_CH0_SZ_512M;
 		break;
-	case 1024:
-		ret = SG_MEMCONF_CH0_SIZE_1024MB;
+	case SZ_1G:
+		ret = SG_MEMCONF_CH0_SZ_1G;
 		break;
 	default:
 		BUG();
@@ -151,24 +159,24 @@ static inline u32 sg_memconf_val_ch0(unsigned long size, int num)
 
 static inline u32 sg_memconf_val_ch1(unsigned long size, int num)
 {
-	int size_mb = (size >> 20) / num;
+	int size_mb = size / num;
 	u32 ret;
 
 	switch (size_mb) {
-	case 64:
-		ret = SG_MEMCONF_CH1_SIZE_64MB;
+	case SZ_64M:
+		ret = SG_MEMCONF_CH1_SZ_64M;
 		break;
-	case 128:
-		ret = SG_MEMCONF_CH1_SIZE_128MB;
+	case SZ_128M:
+		ret = SG_MEMCONF_CH1_SZ_128M;
 		break;
-	case 256:
-		ret = SG_MEMCONF_CH1_SIZE_256MB;
+	case SZ_256M:
+		ret = SG_MEMCONF_CH1_SZ_256M;
 		break;
-	case 512:
-		ret = SG_MEMCONF_CH1_SIZE_512MB;
+	case SZ_512M:
+		ret = SG_MEMCONF_CH1_SZ_512M;
 		break;
-	case 1024:
-		ret = SG_MEMCONF_CH1_SIZE_1024MB;
+	case SZ_1G:
+		ret = SG_MEMCONF_CH1_SZ_1G;
 		break;
 	default:
 		BUG();
@@ -188,6 +196,43 @@ static inline u32 sg_memconf_val_ch1(unsigned long size, int num)
 	}
 	return ret;
 }
+
+static inline u32 sg_memconf_val_ch2(unsigned long size, int num)
+{
+	int size_mb = size / num;
+	u32 ret;
+
+	switch (size_mb) {
+	case SZ_64M:
+		ret = SG_MEMCONF_CH2_SZ_64M;
+		break;
+	case SZ_128M:
+		ret = SG_MEMCONF_CH2_SZ_128M;
+		break;
+	case SZ_256M:
+		ret = SG_MEMCONF_CH2_SZ_256M;
+		break;
+	case SZ_512M:
+		ret = SG_MEMCONF_CH2_SZ_512M;
+		break;
+	default:
+		BUG();
+		break;
+	}
+
+	switch (num) {
+	case 1:
+		ret |= SG_MEMCONF_CH2_NUM_1;
+		break;
+	case 2:
+		ret |= SG_MEMCONF_CH2_NUM_2;
+		break;
+	default:
+		BUG();
+		break;
+	}
+	return ret;
+}
 #endif /* __ASSEMBLY__ */
 
 #endif /* ARCH_SG_REGS_H */