diff options
Diffstat (limited to 'arch/arm/include/asm/mach-imx')
| -rw-r--r-- | arch/arm/include/asm/mach-imx/dma.h | 16 | ||||
| -rw-r--r-- | arch/arm/include/asm/mach-imx/imx-nandbcb.h | 4 | ||||
| -rw-r--r-- | arch/arm/include/asm/mach-imx/iomux-v3.h | 2 | ||||
| -rw-r--r-- | arch/arm/include/asm/mach-imx/module_fuse.h | 127 | ||||
| -rw-r--r-- | arch/arm/include/asm/mach-imx/regs-apbh.h | 9 | ||||
| -rw-r--r-- | arch/arm/include/asm/mach-imx/regs-bch.h | 20 | ||||
| -rw-r--r-- | arch/arm/include/asm/mach-imx/sys_proto.h | 26 |
7 files changed, 177 insertions, 27 deletions
diff --git a/arch/arm/include/asm/mach-imx/dma.h b/arch/arm/include/asm/mach-imx/dma.h index ca70731b9e..55eb84cb8e 100644 --- a/arch/arm/include/asm/mach-imx/dma.h +++ b/arch/arm/include/asm/mach-imx/dma.h @@ -7,11 +7,13 @@ * * Based on code from LTIB: * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2020 NXP */ #ifndef __DMA_H__ #define __DMA_H__ +#include <asm/cache.h> #include <linux/list.h> #include <linux/compiler.h> @@ -53,7 +55,7 @@ enum { MXS_DMA_CHANNEL_AHB_APBH_RESERVED1, MXS_MAX_DMA_CHANNELS, }; -#elif defined(CONFIG_MX6) || defined(CONFIG_MX7) +#else enum { MXS_DMA_CHANNEL_AHB_APBH_GPMI0 = 0, MXS_DMA_CHANNEL_AHB_APBH_GPMI1, @@ -95,13 +97,13 @@ enum { #define MXS_DMA_DESC_BYTES_OFFSET 16 struct mxs_dma_cmd { - unsigned long next; - unsigned long data; + u32 next; + u32 data; union { - dma_addr_t address; - unsigned long alternate; + u32 address; + u32 alternate; }; - unsigned long pio_words[DMA_PIO_WORDS]; + u32 pio_words[DMA_PIO_WORDS]; }; /* @@ -117,7 +119,7 @@ struct mxs_dma_cmd { struct mxs_dma_desc { struct mxs_dma_cmd cmd; unsigned int flags; - dma_addr_t address; + u32 address; void *buffer; struct list_head node; } __aligned(MXS_DMA_ALIGNMENT); diff --git a/arch/arm/include/asm/mach-imx/imx-nandbcb.h b/arch/arm/include/asm/mach-imx/imx-nandbcb.h index 907e7ed8f9..74c9031d4e 100644 --- a/arch/arm/include/asm/mach-imx/imx-nandbcb.h +++ b/arch/arm/include/asm/mach-imx/imx-nandbcb.h @@ -9,9 +9,11 @@ #define FCB_FINGERPRINT 0x20424346 /* 'FCB' */ #define FCB_VERSION_1 0x01000000 +#define FCB_FINGERPRINT_OFF 0x4 /* FCB fingerprint offset*/ -#define DBBT_FINGERPRINT2 0x54424244 /* 'DBBT' */ +#define DBBT_FINGERPRINT 0x54424244 /* 'DBBT' */ #define DBBT_VERSION_1 0x01000000 +#define DBBT_FINGERPRINT_OFF 0x4 /* DBBT fingerprint offset*/ struct dbbt_block { u32 checksum; /* reserved on i.MX6 */ diff --git a/arch/arm/include/asm/mach-imx/iomux-v3.h b/arch/arm/include/asm/mach-imx/iomux-v3.h index 06dbd8d943..1de7093355 100644 --- a/arch/arm/include/asm/mach-imx/iomux-v3.h +++ b/arch/arm/include/asm/mach-imx/iomux-v3.h @@ -10,7 +10,7 @@ #ifndef __MACH_IOMUX_V3_H__ #define __MACH_IOMUX_V3_H__ -#include <common.h> +#include <linux/types.h> /* * build IOMUX_PAD structure diff --git a/arch/arm/include/asm/mach-imx/module_fuse.h b/arch/arm/include/asm/mach-imx/module_fuse.h new file mode 100644 index 0000000000..a46fc3f1f8 --- /dev/null +++ b/arch/arm/include/asm/mach-imx/module_fuse.h @@ -0,0 +1,127 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 NXP + */ + +#ifndef __MODULE_FUSE_H__ +#define __MODULE_FUSE_H__ + +enum fuse_module_type { + MODULE_TSC, + MODULE_ADC1, + MODULE_ADC2, + MODULE_SIM1, + MODULE_SIM2, + MODULE_FLEXCAN1, + MODULE_FLEXCAN2, + MODULE_SPDIF, + MODULE_EIM, + MODULE_SD1, + MODULE_SD2, + MODULE_SD3, + MODULE_SD4, + MODULE_QSPI1, + MODULE_QSPI2, + MODULE_GPMI, + MODULE_APBHDMA, + MODULE_LCDIF, + MODULE_PXP, + MODULE_CSI, + MODULE_ENET1, + MODULE_ENET2, + MODULE_CAAM, + MODULE_USB_OTG1, + MODULE_USB_OTG2, + MODULE_SAI2, + MODULE_SAI3, + MODULE_BEE, + MODULE_UART1, + MODULE_UART2, + MODULE_UART3, + MODULE_UART4, + MODULE_UART5, + MODULE_UART6, + MODULE_UART7, + MODULE_UART8, + MODULE_PWM5, + MODULE_PWM6, + MODULE_PWM7, + MODULE_PWM8, + MODULE_ECSPI1, + MODULE_ECSPI2, + MODULE_ECSPI3, + MODULE_ECSPI4, + MODULE_ECSPI5, + MODULE_I2C1, + MODULE_I2C2, + MODULE_I2C3, + MODULE_I2C4, + MODULE_GPT1, + MODULE_GPT2, + MODULE_EPIT1, + MODULE_EPIT2, + MODULE_EPDC, + MODULE_ESAI, + MODULE_DCP, + MODULE_DCP_CRYPTO, +}; + +struct fuse_entry_desc { + enum fuse_module_type module; + const char *node_path; + u32 fuse_word_offset; + u32 fuse_bit_offset; + u32 status; +}; + +#if !CONFIG_IS_ENABLED(IMX_MODULE_FUSE) +static inline u32 check_module_fused(enum fuse_module_type module) +{ + return 0; +}; + +static inline u32 esdhc_fused(ulong base_addr) +{ + return 0; +}; + +static inline u32 ecspi_fused(ulong base_addr) +{ + return 0; +}; + +static inline u32 uart_fused(ulong base_addr) +{ + return 0; +}; + +static inline u32 usb_fused(ulong base_addr) +{ + return 0; +}; + +static inline u32 qspi_fused(ulong base_addr) +{ + return 0; +}; + +static inline u32 i2c_fused(ulong base_addr) +{ + return 0; +}; + +static inline u32 enet_fused(ulong base_addr) +{ + return 0; +}; +#else +u32 check_module_fused(enum fuse_module_type module); +u32 esdhc_fused(ulong base_addr); +u32 ecspi_fused(ulong base_addr); +u32 uart_fused(ulong base_addr); +u32 usb_fused(ulong base_addr); +u32 qspi_fused(ulong base_addr); +u32 i2c_fused(ulong base_addr); +u32 enet_fused(ulong base_addr); +#endif +#endif /* __MODULE_FUSE_H__ */ diff --git a/arch/arm/include/asm/mach-imx/regs-apbh.h b/arch/arm/include/asm/mach-imx/regs-apbh.h index d7baf13343..94c330c7f9 100644 --- a/arch/arm/include/asm/mach-imx/regs-apbh.h +++ b/arch/arm/include/asm/mach-imx/regs-apbh.h @@ -7,6 +7,7 @@ * * Based on code from LTIB: * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2020 NXP */ #ifndef __REGS_APBH_H__ @@ -95,7 +96,7 @@ struct mxs_apbh_regs { mxs_reg_32(hw_apbh_version) }; -#elif (defined(CONFIG_MX28) || defined(CONFIG_MX6) || defined(CONFIG_MX7)) +#else struct mxs_apbh_regs { mxs_reg_32(hw_apbh_ctrl0) mxs_reg_32(hw_apbh_ctrl1) @@ -274,7 +275,7 @@ struct mxs_apbh_regs { #define APBH_CTRL0_CLKGATE_CHANNEL_NAND7 0x0800 #define APBH_CTRL0_CLKGATE_CHANNEL_HSADC 0x1000 #define APBH_CTRL0_CLKGATE_CHANNEL_LCDIF 0x2000 -#elif (defined(CONFIG_MX6) || defined(CONFIG_MX7)) +#elif (defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)) #define APBH_CTRL0_CLKGATE_CHANNEL_OFFSET 0 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND0 0x0001 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND1 0x0002 @@ -357,7 +358,6 @@ struct mxs_apbh_regs { #if defined(CONFIG_MX28) #define APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK (0xffff << 16) -#define APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET 16 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP0 (0x0001 << 16) #define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP1 (0x0002 << 16) #define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP2 (0x0004 << 16) @@ -390,9 +390,8 @@ struct mxs_apbh_regs { #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_LCDIF 0x2000 #endif -#if (defined(CONFIG_MX6) || defined(CONFIG_MX7)) +/* Not on i.MX23 */ #define APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET 16 -#endif #if defined(CONFIG_MX23) #define APBH_DEVSEL_CH7_MASK (0xf << 28) diff --git a/arch/arm/include/asm/mach-imx/regs-bch.h b/arch/arm/include/asm/mach-imx/regs-bch.h index 39ac5f4d45..5a149002e2 100644 --- a/arch/arm/include/asm/mach-imx/regs-bch.h +++ b/arch/arm/include/asm/mach-imx/regs-bch.h @@ -6,7 +6,9 @@ * on behalf of DENX Software Engineering GmbH * * Based on code from LTIB: - * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008-2010, 2016 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2020 NXP + * */ #ifndef __MX28_REGS_BCH_H__ @@ -40,6 +42,7 @@ struct mxs_bch_regs { mxs_reg_32(hw_bch_dbgahbmread) mxs_reg_32(hw_bch_blockname) mxs_reg_32(hw_bch_version) + mxs_reg_32(hw_bch_debug1) }; #endif @@ -75,6 +78,9 @@ struct mxs_bch_regs { #define BCH_MODE_ERASE_THRESHOLD_MASK 0xff #define BCH_MODE_ERASE_THRESHOLD_OFFSET 0 +#define BCH_MODE_ERASE_THRESHOLD(v) \ + (((v) << BCH_MODE_ERASE_THRESHOLD_OFFSET) & \ + BCH_MODE_ERASE_THRESHOLD_MASK) #define BCH_ENCODEPTR_ADDR_MASK 0xffffffff #define BCH_ENCODEPTR_ADDR_OFFSET 0 @@ -122,7 +128,7 @@ struct mxs_bch_regs { #define BCH_FLASHLAYOUT0_NBLOCKS_OFFSET 24 #define BCH_FLASHLAYOUT0_META_SIZE_MASK (0xff << 16) #define BCH_FLASHLAYOUT0_META_SIZE_OFFSET 16 -#if (defined(CONFIG_MX6) || defined(CONFIG_MX7)) +#if (defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)) #define BCH_FLASHLAYOUT0_ECC0_MASK (0x1f << 11) #define BCH_FLASHLAYOUT0_ECC0_OFFSET 11 #else @@ -146,14 +152,14 @@ struct mxs_bch_regs { #define BCH_FLASHLAYOUT0_ECC0_ECC28 (0xe << 12) #define BCH_FLASHLAYOUT0_ECC0_ECC30 (0xf << 12) #define BCH_FLASHLAYOUT0_ECC0_ECC32 (0x10 << 12) -#define BCH_FLASHLAYOUT0_GF13_0_GF14_1 (1 << 10) +#define BCH_FLASHLAYOUT0_GF13_0_GF14_1_MASK BIT(10) #define BCH_FLASHLAYOUT0_GF13_0_GF14_1_OFFSET 10 -#define BCH_FLASHLAYOUT0_DATA0_SIZE_MASK 0xfff +#define BCH_FLASHLAYOUT0_DATA0_SIZE_MASK 0x3ff #define BCH_FLASHLAYOUT0_DATA0_SIZE_OFFSET 0 #define BCH_FLASHLAYOUT1_PAGE_SIZE_MASK (0xffff << 16) #define BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET 16 -#if (defined(CONFIG_MX6) || defined(CONFIG_MX7)) +#if (defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)) #define BCH_FLASHLAYOUT1_ECCN_MASK (0x1f << 11) #define BCH_FLASHLAYOUT1_ECCN_OFFSET 11 #else @@ -177,9 +183,9 @@ struct mxs_bch_regs { #define BCH_FLASHLAYOUT1_ECCN_ECC28 (0xe << 12) #define BCH_FLASHLAYOUT1_ECCN_ECC30 (0xf << 12) #define BCH_FLASHLAYOUT1_ECCN_ECC32 (0x10 << 12) -#define BCH_FLASHLAYOUT1_GF13_0_GF14_1 (1 << 10) +#define BCH_FLASHLAYOUT1_GF13_0_GF14_1_MASK BIT(10) #define BCH_FLASHLAYOUT1_GF13_0_GF14_1_OFFSET 10 -#define BCH_FLASHLAYOUT1_DATAN_SIZE_MASK 0xfff +#define BCH_FLASHLAYOUT1_DATAN_SIZE_MASK 0x3ff #define BCH_FLASHLAYOUT1_DATAN_SIZE_OFFSET 0 #define BCH_DEBUG0_RSVD1_MASK (0x1f << 27) diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h index 35b39b1f86..0bc705df17 100644 --- a/arch/arm/include/asm/mach-imx/sys_proto.h +++ b/arch/arm/include/asm/mach-imx/sys_proto.h @@ -9,14 +9,17 @@ #include <asm/io.h> #include <asm/mach-imx/regs-common.h> -#include <common.h> +#include <asm/mach-imx/module_fuse.h> +#include <linux/bitops.h> #include "../arch-imx/cpu.h" +struct bd_info; + #define soc_rev() (get_cpu_rev() & 0xFF) #define is_soc_rev(rev) (soc_rev() == rev) /* returns MXC_CPU_ value */ -#define cpu_type(rev) (((rev) >> 12) & 0xff) +#define cpu_type(rev) (((rev) >> 12) & 0x1ff) #define soc_type(rev) (((rev) >> 12) & 0xf0) /* both macros return/take MXC_CPU_ constants */ #define get_cpu_type() (cpu_type(get_cpu_rev())) @@ -37,13 +40,15 @@ #define is_mx6sl() (is_cpu_type(MXC_CPU_MX6SL)) #define is_mx6solo() (is_cpu_type(MXC_CPU_MX6SOLO)) #define is_mx6ul() (is_cpu_type(MXC_CPU_MX6UL)) -#define is_mx6ull() (is_cpu_type(MXC_CPU_MX6ULL)) +#define is_mx6ull() (is_cpu_type(MXC_CPU_MX6ULL) || is_cpu_type(MXC_CPU_MX6ULZ)) #define is_mx6ulz() (is_cpu_type(MXC_CPU_MX6ULZ)) #define is_mx6sll() (is_cpu_type(MXC_CPU_MX6SLL)) #define is_mx7ulp() (is_cpu_type(MXC_CPU_MX7ULP)) -#define is_imx8mq() (is_cpu_type(MXC_CPU_IMX8MQ)) +#define is_imx8mq() (is_cpu_type(MXC_CPU_IMX8MQ) || is_cpu_type(MXC_CPU_IMX8MD) || is_cpu_type(MXC_CPU_IMX8MQL)) +#define is_imx8md() (is_cpu_type(MXC_CPU_IMX8MD)) +#define is_imx8mql() (is_cpu_type(MXC_CPU_IMX8MQL)) #define is_imx8qm() (is_cpu_type(MXC_CPU_IMX8QM)) #define is_imx8mm() (is_cpu_type(MXC_CPU_IMX8MM) || is_cpu_type(MXC_CPU_IMX8MML) ||\ is_cpu_type(MXC_CPU_IMX8MMD) || is_cpu_type(MXC_CPU_IMX8MMDL) || \ @@ -53,7 +58,14 @@ #define is_imx8mmdl() (is_cpu_type(MXC_CPU_IMX8MMDL)) #define is_imx8mms() (is_cpu_type(MXC_CPU_IMX8MMS)) #define is_imx8mmsl() (is_cpu_type(MXC_CPU_IMX8MMSL)) -#define is_imx8mn() (is_cpu_type(MXC_CPU_IMX8MN)) +#define is_imx8mn() (is_cpu_type(MXC_CPU_IMX8MN) || is_cpu_type(MXC_CPU_IMX8MND) || \ + is_cpu_type(MXC_CPU_IMX8MNS) || is_cpu_type(MXC_CPU_IMX8MNL) || \ + is_cpu_type(MXC_CPU_IMX8MNDL) || is_cpu_type(MXC_CPU_IMX8MNSL)) +#define is_imx8mnd() (is_cpu_type(MXC_CPU_IMX8MND)) +#define is_imx8mns() (is_cpu_type(MXC_CPU_IMX8MNS)) +#define is_imx8mnl() (is_cpu_type(MXC_CPU_IMX8MNL)) +#define is_imx8mndl() (is_cpu_type(MXC_CPU_IMX8MNDL)) +#define is_imx8mnsl() (is_cpu_type(MXC_CPU_IMX8MNSL)) #define is_imx8mp() (is_cpu_type(MXC_CPU_IMX8MP)) #define is_imx8qxp() (is_cpu_type(MXC_CPU_IMX8QXP)) @@ -172,7 +184,7 @@ char nxp_board_rev_string(void); * Initializes on-chip ethernet controllers. * to override, implement board_eth_init() */ -int fecmxc_initialize(bd_t *bis); +int fecmxc_initialize(struct bd_info *bis); u32 get_ahb_clk(void); u32 get_periph_clk(void); @@ -188,4 +200,6 @@ unsigned long call_imx_sip(unsigned long id, unsigned long reg0, unsigned long call_imx_sip_ret2(unsigned long id, unsigned long reg0, unsigned long *reg1, unsigned long reg2, unsigned long reg3); + +void imx_get_mac_from_fuse(int dev_id, unsigned char *mac); #endif |