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-rw-r--r--arch/arm/include/asm/arch-fsl-layerscape/config.h10
-rw-r--r--arch/arm/include/asm/arch-fsl-layerscape/cpu.h3
-rw-r--r--arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h70
-rw-r--r--arch/arm/include/asm/arch-fsl-layerscape/soc.h1
-rw-r--r--arch/arm/include/asm/arch-ls102xa/config.h1
-rw-r--r--arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h2
-rw-r--r--arch/arm/include/asm/arch-zynqmp/clk.h1
-rw-r--r--arch/arm/include/asm/arch-zynqmp/hardware.h30
-rw-r--r--arch/arm/include/asm/fsl_secure_boot.h20
-rw-r--r--arch/arm/include/asm/system.h7
10 files changed, 111 insertions, 34 deletions
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 49b113dc59..ff3b1bee3e 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -118,6 +118,15 @@
#define CONFIG_SYS_FSL_ERRATUM_A008585
#define CONFIG_SYS_FSL_ERRATUM_A008751
#define CONFIG_SYS_FSL_ERRATUM_A009635
+#define CONFIG_SYS_FSL_ERRATUM_A009663
+#define CONFIG_SYS_FSL_ERRATUM_A009942
+
+/* ARM A57 CORE ERRATA */
+#define CONFIG_ARM_ERRATA_826974
+#define CONFIG_ARM_ERRATA_828024
+#define CONFIG_ARM_ERRATA_829520
+#define CONFIG_ARM_ERRATA_833471
+
#elif defined(CONFIG_LS1043A)
#define CONFIG_MAX_CPUS 4
#define CONFIG_SYS_CACHELINE_SIZE 64
@@ -166,6 +175,7 @@
#define GICD_BASE 0x01401000
#define GICC_BASE 0x01402000
+#define CONFIG_SYS_FSL_ERRATUM_A009663
#define CONFIG_SYS_FSL_ERRATUM_A009929
#else
#error SoC not defined
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
index e030430786..15ade84c48 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@@ -12,6 +12,7 @@ static struct cpu_type cpu_type_list[] = {
CPU_TYPE_ENTRY(LS2085, LS2085, 8),
CPU_TYPE_ENTRY(LS2045, LS2045, 4),
CPU_TYPE_ENTRY(LS1043, LS1043, 4),
+ CPU_TYPE_ENTRY(LS2040, LS2040, 4),
};
#ifndef CONFIG_SYS_DCACHE_OFF
@@ -150,6 +151,8 @@ static const struct sys_mmu_table early_mmu_table[] = {
{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE,
PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
+ { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
+ CONFIG_SYS_FSL_QSPI_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
{ CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 21b803ff0f..0bad0c70b8 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -218,6 +218,9 @@ struct ccsr_gur {
#define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK 0x3f
#define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK 0xffff0000
#define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT 16
+#define RCW_SB_EN_REG_INDEX 7
+#define RCW_SB_EN_MASK 0x00200000
+
u8 res_140[0x200-0x140];
u32 scratchrw[4]; /* Scratch Read/Write */
u8 res_210[0x300-0x210];
@@ -451,7 +454,8 @@ struct ccsr_serdes {
u32 res_0c; /* 0x00c */
u32 pllcr3;
u32 pllcr4;
- u8 res_18[0x20-0x18];
+ u32 pllcr5; /* 0x018 SerDes PLL1 Control 5 */
+ u8 res_1c[0x20-0x1c];
} bank[2];
u8 res_40[0x90-0x40];
u32 srdstcalcr; /* 0x90 TX Calibration Control */
@@ -459,25 +463,25 @@ struct ccsr_serdes {
u32 srdsrcalcr; /* 0xa0 RX Calibration Control */
u8 res_a4[0xb0-0xa4];
u32 srdsgr0; /* 0xb0 General Register 0 */
- u8 res_b4[0xe0-0xb4];
- u32 srdspccr0; /* 0xe0 Protocol Converter Config 0 */
- u32 srdspccr1; /* 0xe4 Protocol Converter Config 1 */
- u32 srdspccr2; /* 0xe8 Protocol Converter Config 2 */
- u32 srdspccr3; /* 0xec Protocol Converter Config 3 */
- u32 srdspccr4; /* 0xf0 Protocol Converter Config 4 */
- u8 res_f4[0x100-0xf4];
+ u8 res_b4[0x100-0xb4];
struct {
- u32 lnpssr; /* 0x100, 0x120, ..., 0x1e0 */
+ u32 lnpssr0; /* 0x100, 0x120, 0x140, 0x160 */
u8 res_104[0x120-0x104];
- } srdslnpssr[4];
- u8 res_180[0x300-0x180];
- u32 srdspexeqcr;
- u32 srdspexeqpcr[11];
- u8 res_330[0x400-0x330];
- u32 srdspexapcr;
- u8 res_404[0x440-0x404];
- u32 srdspexbpcr;
- u8 res_444[0x800-0x444];
+ } lnpssr[4]; /* Lane A, B, C, D */
+ u8 res_180[0x200-0x180];
+ u32 srdspccr0; /* 0x200 Protocol Configuration 0 */
+ u32 srdspccr1; /* 0x204 Protocol Configuration 1 */
+ u32 srdspccr2; /* 0x208 Protocol Configuration 2 */
+ u32 srdspccr3; /* 0x20c Protocol Configuration 3 */
+ u32 srdspccr4; /* 0x210 Protocol Configuration 4 */
+ u32 srdspccr5; /* 0x214 Protocol Configuration 5 */
+ u32 srdspccr6; /* 0x218 Protocol Configuration 6 */
+ u32 srdspccr7; /* 0x21c Protocol Configuration 7 */
+ u32 srdspccr8; /* 0x220 Protocol Configuration 8 */
+ u32 srdspccr9; /* 0x224 Protocol Configuration 9 */
+ u32 srdspccra; /* 0x228 Protocol Configuration A */
+ u32 srdspccrb; /* 0x22c Protocol Configuration B */
+ u8 res_230[0x800-0x230];
struct {
u32 gcr0; /* 0x800 General Control Register 0 */
u32 gcr1; /* 0x804 General Control Register 1 */
@@ -490,8 +494,34 @@ struct ccsr_serdes {
u32 ttlcr0; /* 0x820 Transition Tracking Loop Ctrl 0 */
u8 res_824[0x83c-0x824];
u32 tcsr3;
- } lane[4]; /* Lane A, B, C, D, E, F, G, H */
- u8 res_a00[0x1000-0xa00]; /* from 0xa00 to 0xfff */
+ } lane[4]; /* Lane A, B, C, D */
+ u8 res_900[0x1000-0x900]; /* from 0x900 to 0xfff */
+ struct {
+ u32 srdspexcr0; /* 0x1000, 0x1040, 0x1080 */
+ u8 res_1004[0x1040-0x1004];
+ } pcie[3];
+ u8 res_10c0[0x1800-0x10c0];
+ struct {
+ u8 res_1800[0x1804-0x1800];
+ u32 srdssgmiicr1; /* 0x1804 SGMII Protocol Control 1 */
+ u8 res_1808[0x180c-0x1808];
+ u32 srdssgmiicr3; /* 0x180c SGMII Protocol Control 3 */
+ } sgmii[4]; /* Lane A, B, C, D */
+ u8 res_1840[0x1880-0x1840];
+ struct {
+ u8 res_1880[0x1884-0x1880];
+ u32 srdsqsgmiicr1; /* 0x1884 QSGMII Protocol Control 1 */
+ u8 res_1888[0x188c-0x1888];
+ u32 srdsqsgmiicr3; /* 0x188c QSGMII Protocol Control 3 */
+ } qsgmii[2]; /* Lane A, B */
+ u8 res_18a0[0x1980-0x18a0];
+ struct {
+ u8 res_1980[0x1984-0x1980];
+ u32 srdsxficr1; /* 0x1984 XFI Protocol Control 1 */
+ u8 res_1988[0x198c-0x1988];
+ u32 srdsxficr3; /* 0x198c XFI Protocol Control 3 */
+ } xfi[2]; /* Lane A, B */
+ u8 res_19a0[0x2000-0x19a0]; /* from 0x19a0 to 0x1fff */
};
#define CCI400_CTRLORD_TERM_BARRIER 0x00000008
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index 1565592996..ea78e15f49 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -45,6 +45,7 @@ struct cpu_type {
#define SVR_LS2045 0x870120
#define SVR_LS2080 0x870110
#define SVR_LS2085 0x870100
+#define SVR_LS2040 0x870130
#define SVR_MAJ(svr) (((svr) >> 4) & 0xf)
#define SVR_MIN(svr) (((svr) >> 0) & 0xf)
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
index f066480c0c..424fe879dd 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -131,6 +131,7 @@
#define CONFIG_SYS_FSL_SEC_COMPAT 5
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_FSL_ERRATUM_A008378
+#define CONFIG_SYS_FSL_ERRATUM_A009663
#else
#error SoC not defined
#endif
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 89339fe0ef..0a80772b51 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -120,6 +120,8 @@ struct ccsr_gur {
u32 brrl; /* Boot release */
u8 res_0e8[0x100-0xe8];
u32 rcwsr[16]; /* Reset control word status */
+#define RCW_SB_EN_REG_INDEX 7
+#define RCW_SB_EN_MASK 0x00200000
u8 res_140[0x200-0x140];
u32 scratchrw[4]; /* Scratch Read/Write */
u8 res_210[0x300-0x210];
diff --git a/arch/arm/include/asm/arch-zynqmp/clk.h b/arch/arm/include/asm/arch-zynqmp/clk.h
index d55bc31c43..b18333d1ca 100644
--- a/arch/arm/include/asm/arch-zynqmp/clk.h
+++ b/arch/arm/include/asm/arch-zynqmp/clk.h
@@ -9,5 +9,6 @@
#define _ASM_ARCH_CLK_H_
unsigned long get_uart_clk(int dev_id);
+unsigned long zynqmp_get_system_timer_freq(void);
#endif /* _ASM_ARCH_CLK_H_ */
diff --git a/arch/arm/include/asm/arch-zynqmp/hardware.h b/arch/arm/include/asm/arch-zynqmp/hardware.h
index bbf89d9dd7..587938249e 100644
--- a/arch/arm/include/asm/arch-zynqmp/hardware.h
+++ b/arch/arm/include/asm/arch-zynqmp/hardware.h
@@ -41,11 +41,8 @@ struct crlapb_regs {
#define crlapb_base ((struct crlapb_regs *)ZYNQMP_CRL_APB_BASEADDR)
-#if defined(CONFIG_SECURE_IOU)
-#define ZYNQMP_IOU_SCNTR 0xFF260000
-#else
+#define ZYNQMP_IOU_SCNTR_SECURE 0xFF260000
#define ZYNQMP_IOU_SCNTR 0xFF250000
-#endif
#define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN 0x1
#define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG 0x2
@@ -57,9 +54,21 @@ struct iou_scntr {
#define iou_scntr ((struct iou_scntr *)ZYNQMP_IOU_SCNTR)
+struct iou_scntr_secure {
+ u32 counter_control_register;
+ u32 reserved0[7];
+ u32 base_frequency_id_register;
+};
+
+#define iou_scntr_secure ((struct iou_scntr_secure *)ZYNQMP_IOU_SCNTR_SECURE)
+
/* Bootmode setting values */
#define BOOT_MODES_MASK 0x0000000F
-#define SD_MODE 0x00000003
+#define QSPI_MODE_24BIT 0x00000001
+#define QSPI_MODE_32BIT 0x00000002
+#define SD_MODE 0x00000003 /* sd 0 */
+#define SD_MODE1 0x00000005 /* sd 1 */
+#define NAND_MODE 0x00000004
#define EMMC_MODE 0x00000006
#define JTAG_MODE 0x00000000
@@ -106,9 +115,20 @@ struct apu_regs {
#define apu_base ((struct apu_regs *)ZYNQMP_APU_BASEADDR)
/* Board version value */
+#define ZYNQMP_CSU_BASEADDR 0xFFCA0000
#define ZYNQMP_CSU_VERSION_SILICON 0x0
#define ZYNQMP_CSU_VERSION_EP108 0x1
#define ZYNQMP_CSU_VERSION_VELOCE 0x2
#define ZYNQMP_CSU_VERSION_QEMU 0x3
+#define ZYNQMP_SILICON_VER_MASK 0xF000
+#define ZYNQMP_SILICON_VER_SHIFT 12
+
+struct csu_regs {
+ u32 reserved0[17];
+ u32 version;
+};
+
+#define csu_base ((struct csu_regs *)ZYNQMP_CSU_BASEADDR)
+
#endif /* _ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h
index 806302bc61..0da0599738 100644
--- a/arch/arm/include/asm/fsl_secure_boot.h
+++ b/arch/arm/include/asm/fsl_secure_boot.h
@@ -8,7 +8,16 @@
#define __FSL_SECURE_BOOT_H
#ifdef CONFIG_SECURE_BOOT
+
+#ifndef CONFIG_FIT_SIGNATURE
+#define CONFIG_CHAIN_OF_TRUST
+#endif
+
+#endif
+
+#ifdef CONFIG_CHAIN_OF_TRUST
#define CONFIG_CMD_ESBC_VALIDATE
+#define CONFIG_CMD_BLOB
#define CONFIG_FSL_SEC_MON
#define CONFIG_SHA_PROG_HW_ACCEL
#define CONFIG_RSA
@@ -34,7 +43,10 @@
#define CONFIG_FSL_ISBC_KEY_EXT
#endif
-#ifndef CONFIG_FIT_SIGNATURE
+#ifdef CONFIG_LS1043A
+/* For LS1043 (ARMv8), ESBC image Address in Header is 64 bit */
+#define CONFIG_ESBC_ADDR_64BIT
+#endif
#define CONFIG_EXTRA_ENV \
"setenv fdt_high 0xcfffffff;" \
@@ -44,8 +56,6 @@
/* The address needs to be modified according to NOR memory map */
#define CONFIG_BOOTSCRIPT_HDR_ADDR 0x600a0000
-#include <config_fsl_secboot.h>
-#endif
-#endif
-
+#include <config_fsl_chain_trust.h>
+#endif /* #ifdef CONFIG_CHAIN_OF_TRUST */
#endif
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 67cbbc2610..026e7ef83b 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -259,7 +259,7 @@ static inline void set_dacr(unsigned int val)
isb();
}
-#ifdef CONFIG_ARMV7
+#ifdef CONFIG_CPU_V7
/* Short-Descriptor Translation Table Level 1 Bits */
#define TTB_SECT_NS_MASK (1 << 19)
#define TTB_SECT_NG_MASK (1 << 17)
@@ -274,8 +274,7 @@ static inline void set_dacr(unsigned int val)
/* options available for data cache on each page */
enum dcache_option {
- DCACHE_OFF = TTB_SECT_S_MASK | TTB_SECT_DOMAIN(0) |
- TTB_SECT_XN_MASK | TTB_SECT,
+ DCACHE_OFF = TTB_SECT_DOMAIN(0) | TTB_SECT_XN_MASK | TTB_SECT,
DCACHE_WRITETHROUGH = DCACHE_OFF | TTB_SECT_C_MASK,
DCACHE_WRITEBACK = DCACHE_WRITETHROUGH | TTB_SECT_B_MASK,
DCACHE_WRITEALLOC = DCACHE_WRITEBACK | TTB_SECT_TEX(1),
@@ -296,7 +295,7 @@ enum {
MMU_SECTION_SIZE = 1 << MMU_SECTION_SHIFT,
};
-#ifdef CONFIG_ARMV7
+#ifdef CONFIG_CPU_V7
/* TTBR0 bits */
#define TTBR0_BASE_ADDR_MASK 0xFFFFC000
#define TTBR0_RGN_NC (0 << 3)
generated by cgit (git 2.34.1) at 2025-01-07 13:38:47 +0000