diff options
Diffstat (limited to 'arch/arm/include/asm')
| -rw-r--r-- | arch/arm/include/asm/arch-imx/cpu.h | 13 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-mx5/sys_proto.h | 7 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-mx6/clock.h | 1 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-mx6/imx-regs.h | 1 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-mx6/iomux.h | 27 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-mx6/sys_proto.h | 8 | ||||
| -rw-r--r-- | arch/arm/include/asm/pl310.h | 21 |
7 files changed, 65 insertions, 13 deletions
diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h new file mode 100644 index 0000000000..a35940e64f --- /dev/null +++ b/arch/arm/include/asm/arch-imx/cpu.h @@ -0,0 +1,13 @@ +/* + * (C) Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#define MXC_CPU_MX51 0x51 +#define MXC_CPU_MX53 0x53 +#define MXC_CPU_MX6SL 0x60 +#define MXC_CPU_MX6DL 0x61 +#define MXC_CPU_MX6SOLO 0x62 +#define MXC_CPU_MX6Q 0x63 +#define MXC_CPU_MX6D 0x64 diff --git a/arch/arm/include/asm/arch-mx5/sys_proto.h b/arch/arm/include/asm/arch-mx5/sys_proto.h index 9949ad1312..ac7705b3b0 100644 --- a/arch/arm/include/asm/arch-mx5/sys_proto.h +++ b/arch/arm/include/asm/arch-mx5/sys_proto.h @@ -8,12 +8,7 @@ #ifndef _SYS_PROTO_H_ #define _SYS_PROTO_H_ -#define MXC_CPU_MX51 0x51 -#define MXC_CPU_MX53 0x53 -#define MXC_CPU_MX6SL 0x60 -#define MXC_CPU_MX6DL 0x61 -#define MXC_CPU_MX6SOLO 0x62 -#define MXC_CPU_MX6Q 0x63 +#include "../arch-imx/cpu.h" #define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev) u32 get_cpu_rev(void); diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h index e31ba0a955..1b4ded7feb 100644 --- a/arch/arm/include/asm/arch-mx6/clock.h +++ b/arch/arm/include/asm/arch-mx6/clock.h @@ -55,6 +55,7 @@ unsigned int mxc_get_clock(enum mxc_clock clk); void enable_ocotp_clk(unsigned char enable); void enable_usboh3_clk(unsigned char enable); int enable_sata_clock(void); +int enable_pcie_clock(void); int enable_i2c_clk(unsigned char enable, unsigned i2c_num); void enable_ipu_clock(void); int enable_fec_anatop_clock(enum enet_freq freq); diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index f2ad6e9ad3..c2d210a0f3 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -53,6 +53,7 @@ #define GLOBAL_TIMER_BASE_ADDR 0x00A00200 #define PRIVATE_TIMERS_WD_BASE_ADDR 0x00A00600 #define IC_DISTRIBUTOR_BASE_ADDR 0x00A01000 +#define L2_PL310_BASE 0x00A02000 #define GPV0_BASE_ADDR 0x00B00000 #define GPV1_BASE_ADDR 0x00C00000 #define PCIE_ARB_BASE_ADDR 0x01000000 diff --git a/arch/arm/include/asm/arch-mx6/iomux.h b/arch/arm/include/asm/arch-mx6/iomux.h index fe4675e0b7..f9ee0d9839 100644 --- a/arch/arm/include/asm/arch-mx6/iomux.h +++ b/arch/arm/include/asm/arch-mx6/iomux.h @@ -15,6 +15,33 @@ #define IOMUXC_GPR1_OTG_ID_ENET_RX_ERR (0<<13) #define IOMUXC_GPR1_OTG_ID_GPIO1 (1<<13) #define IOMUXC_GPR1_OTG_ID_MASK (1<<13) +#define IOMUXC_GPR1_REF_SSP_EN (1 << 16) +#define IOMUXC_GPR1_TEST_POWERDOWN (1 << 18) + +/* + * IOMUXC_GPR8 bit fields + */ +#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_MASK (0x3f << 0) +#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_OFFSET 0 +#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_MASK (0x3f << 6) +#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_OFFSET 6 +#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB_MASK (0x3f << 12) +#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB_OFFSET 12 +#define IOMUXC_GPR8_PCS_TX_SWING_FULL_MASK (0x7f << 18) +#define IOMUXC_GPR8_PCS_TX_SWING_FULL_OFFSET 18 +#define IOMUXC_GPR8_PCS_TX_SWING_LOW_MASK (0x7f << 25) +#define IOMUXC_GPR8_PCS_TX_SWING_LOW_OFFSET 25 + +/* + * IOMUXC_GPR12 bit fields + */ +#define IOMUXC_GPR12_LOS_LEVEL_9 (0x9 << 4) +#define IOMUXC_GPR12_LOS_LEVEL_MASK (0x1f << 4) +#define IOMUXC_GPR12_APPS_LTSSM_ENABLE (1 << 10) +#define IOMUXC_GPR12_DEVICE_TYPE_EP (0x0 << 12) +#define IOMUXC_GPR12_DEVICE_TYPE_RC (0x2 << 12) +#define IOMUXC_GPR12_DEVICE_TYPE_MASK (0xf << 12) + /* * IOMUXC_GPR13 bit fields */ diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h index 17125a6f3e..38851a135c 100644 --- a/arch/arm/include/asm/arch-mx6/sys_proto.h +++ b/arch/arm/include/asm/arch-mx6/sys_proto.h @@ -9,13 +9,7 @@ #define _SYS_PROTO_H_ #include <asm/imx-common/regs-common.h> - -#define MXC_CPU_MX51 0x51 -#define MXC_CPU_MX53 0x53 -#define MXC_CPU_MX6SL 0x60 -#define MXC_CPU_MX6DL 0x61 -#define MXC_CPU_MX6SOLO 0x62 -#define MXC_CPU_MX6Q 0x63 +#include "../arch-imx/cpu.h" #define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev) u32 get_cpu_rev(void); diff --git a/arch/arm/include/asm/pl310.h b/arch/arm/include/asm/pl310.h index f41ad8c559..ddc245bfd5 100644 --- a/arch/arm/include/asm/pl310.h +++ b/arch/arm/include/asm/pl310.h @@ -12,6 +12,9 @@ /* Register bit fields */ #define PL310_AUX_CTRL_ASSOCIATIVITY_MASK (1 << 16) +#define L2X0_DYNAMIC_CLK_GATING_EN (1 << 1) +#define L2X0_STNDBY_MODE_EN (1 << 0) +#define L2X0_CTRL_EN 1 struct pl310_regs { u32 pl310_cache_id; @@ -47,6 +50,24 @@ struct pl310_regs { u32 pad9[1]; u32 pl310_clean_inv_line_idx; u32 pl310_clean_inv_way; + u32 pad10[64]; + u32 pl310_lockdown_dbase; + u32 pl310_lockdown_ibase; + u32 pad11[190]; + u32 pl310_addr_filter_start; + u32 pl310_addr_filter_end; + u32 pad12[190]; + u32 pl310_test_operation; + u32 pad13[3]; + u32 pl310_line_data; + u32 pad14[7]; + u32 pl310_line_tag; + u32 pad15[3]; + u32 pl310_debug_ctrl; + u32 pad16[7]; + u32 pl310_prefetch_ctrl; + u32 pad17[7]; + u32 pl310_power_ctrl; }; void pl310_inval_all(void); |