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-rw-r--r--arch/arm/include/asm/arch-fsl-layerscape/config.h1
-rw-r--r--arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h4
-rw-r--r--arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h2
-rw-r--r--arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h3
-rw-r--r--arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h29
-rw-r--r--arch/arm/include/asm/arch-ls102xa/ls102xa_sata.h10
6 files changed, 12 insertions, 37 deletions
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 8a05148136..bd4ca88e16 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -195,6 +195,7 @@
/* SoC related */
#ifdef CONFIG_ARCH_LS1043A
#define CONFIG_SYS_FMAN_V3
+#define CONFIG_SYS_FSL_QMAN_V3
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 7
#define CONFIG_SYS_NUM_FM1_10GEC 1
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
index a70c866651..a3f473fe28 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
@@ -68,6 +68,10 @@ void fdt_fixup_icid(void *blob);
#define SET_DEBUG_ICID(streamid) \
SET_SCFG_ICID(NULL, streamid, debug_icid, 0)
+#define SET_QE_ICID(streamid) \
+ SET_SCFG_ICID("fsl,qe", streamid, qe_icid,\
+ QE_BASE_ADDR)
+
#define SET_QMAN_ICID(streamid) \
SET_ICID_ENTRY("fsl,qman", streamid, streamid, \
offsetof(struct ccsr_qman, liodnr) + \
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index be0a6ae363..8c10526a6c 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -85,6 +85,8 @@
#define GPIO3_BASE_ADDR (CONFIG_SYS_IMMR + 0x1320000)
#define GPIO4_BASE_ADDR (CONFIG_SYS_IMMR + 0x1330000)
+#define QE_BASE_ADDR (CONFIG_SYS_IMMR + 0x1400000)
+
#define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000)
#define EDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x01c00000)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
index afea9b8da8..8d002da3ed 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
@@ -35,6 +35,9 @@
* -DPAA2
* -u-boot will allocate a range of stream IDs to be used by the Management
* Complex for containers and will set these values in the MC DPC image.
+ * -u-boot will fixup the iommu-map property in the fsl-mc node in the
+ * device tree (see Documentation/devicetree/bindings/misc/fsl,qoriq-mc.txt
+ * for more info on the msi-map definition)
* -the MC is responsible for allocating and setting up 'isolation context
* IDs (ICIDs) based on the allocated stream IDs for all DPAA2 devices.
*
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 13a282ffe1..137cd61804 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -86,6 +86,8 @@ struct sys_info {
unsigned long freq_localbus;
};
+#define CCSR_DEVDISR1_QE 0x00000001
+
/* Device Configuration and Pin Control */
struct ccsr_gur {
u32 porsr1; /* POR status 1 */
@@ -389,33 +391,6 @@ struct ccsr_serdes {
u8 res_a00[0x1000-0xa00]; /* from 0xa00 to 0xfff */
};
-
-
-/* AHCI (sata) register map */
-struct ccsr_ahci {
- u32 res1[0xa4/4]; /* 0x0 - 0xa4 */
- u32 pcfg; /* port config */
- u32 ppcfg; /* port phy1 config */
- u32 pp2c; /* port phy2 config */
- u32 pp3c; /* port phy3 config */
- u32 pp4c; /* port phy4 config */
- u32 pp5c; /* port phy5 config */
- u32 paxic; /* port AXI config */
- u32 axicc; /* AXI cache control */
- u32 axipc; /* AXI PROT control */
- u32 ptc; /* port Trans Config */
- u32 pts; /* port Trans Status */
- u32 plc; /* port link config */
- u32 plc1; /* port link config1 */
- u32 plc2; /* port link config2 */
- u32 pls; /* port link status */
- u32 pls1; /* port link status1 */
- u32 pcmdc; /* port CMD config */
- u32 ppcs; /* port phy control status */
- u32 pberr; /* port 0/1 BIST error */
- u32 cmds; /* port 0/1 CMD status error */
-};
-
#define RCPM_POWMGTCSR 0x130
#define RCPM_POWMGTCSR_SERDES_PW 0x80000000
#define RCPM_POWMGTCSR_LPM20_REQ 0x00100000
diff --git a/arch/arm/include/asm/arch-ls102xa/ls102xa_sata.h b/arch/arm/include/asm/arch-ls102xa/ls102xa_sata.h
deleted file mode 100644
index 3acc5af6f2..0000000000
--- a/arch/arm/include/asm/arch-ls102xa/ls102xa_sata.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2015 Freescale Semiconductor, Inc.
- */
-
-#ifndef __FSL_SATA_H_
-#define __FSL_SATA_H_
-
-int ls1021a_sata_init(void);
-#endif