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-rw-r--r--arch/arm/include/asm/arch-fsl-layerscape/config.h2
-rw-r--r--arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h2
-rw-r--r--arch/arm/include/asm/armv8/sec_firmware.h4
3 files changed, 5 insertions, 3 deletions
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index a7098be846..95e2791507 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -16,7 +16,7 @@
* Reserve secure memory
* To be aligned with MMU block size
*/
-#define CONFIG_SYS_MEM_RESERVE_SECURE (2048 * 1024) /* 2MB */
+#define CONFIG_SYS_MEM_RESERVE_SECURE (66 * 1024 * 1024) /* 66MB */
#define SPL_TLB_SETBACK 0x1000000 /* 16MB under effective memory top */
#ifdef CONFIG_ARCH_LS2080A
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h b/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h
index 5dfcbf3b01..b4ea2f8cfb 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h
@@ -158,7 +158,7 @@ struct sunxi_ccm_reg {
#define CPU_CLK_SRC_OSC24M 0
#define CPU_CLK_SRC_PLL1 1
-#define CCM_PLL1_CTRL_N(n) ((((n) - 1) & 0xff) << 8)
+#define CCM_PLL1_CTRL_N(n) (((n) & 0xff) << 8)
#define CCM_PLL1_CTRL_P(n) (((n) & 0x1) << 16)
#define CCM_PLL1_CTRL_EN (0x1 << 31)
#define CMM_PLL1_CLOCK_TIME_2 (0x2 << 24)
diff --git a/arch/arm/include/asm/armv8/sec_firmware.h b/arch/arm/include/asm/armv8/sec_firmware.h
index 6d42a7111f..2ba1847a2e 100644
--- a/arch/arm/include/asm/armv8/sec_firmware.h
+++ b/arch/arm/include/asm/armv8/sec_firmware.h
@@ -9,8 +9,10 @@
#define PSCI_INVALID_VER 0xffffffff
#define SEC_JR3_OFFSET 0x40000
+#define WORD_MASK 0xffffffff
+#define WORD_SHIFT 32
-int sec_firmware_init(const void *, u32 *, u32 *);
+int sec_firmware_init(const void *, u32 *, u32 *, u32 *, u32 *);
int _sec_firmware_entry(const void *, u32 *, u32 *);
bool sec_firmware_is_valid(const void *);
bool sec_firmware_support_hwrng(void);